From mboxrd@z Thu Jan 1 00:00:00 1970 From: Geert Uytterhoeven Subject: [PATCH/RFC 06/15] ARM: shmobile: r8a7794 dtsi: Add L2 cache-controller node Date: Thu, 4 Jun 2015 20:53:32 +0200 Message-ID: <1433444021-22167-7-git-send-email-geert+renesas@glider.be> References: <1433444021-22167-1-git-send-email-geert+renesas@glider.be> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1433444021-22167-1-git-send-email-geert+renesas@glider.be> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Simon Horman , Magnus Damm , "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson , Lina Iyer , Mark Rutland , Pawel Moll Cc: devicetree@vger.kernel.org, Geert Uytterhoeven , linux-sh@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Add a device node for the L2 cache: - The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways). Signed-off-by: Geert Uytterhoeven --- What are the DT bindings for a Cortex-A15 L2 cache controller? --- arch/arm/boot/dts/r8a7794.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index d26cce1f609dd7b8..0c3ab5febe0a88d8 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -38,6 +38,17 @@ }; }; + L2_CA7: cache-controller@1 { + compatible = "cache"; + + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <2048>; + cache-block-size = <32>; + cache-line-size = <32>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; -- 1.9.1