From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hans de Goede Subject: [PATCH 07/20] ARM: dts: sun8i: Add support for USB controllers on A23/A33 Date: Fri, 5 Jun 2015 21:02:10 +0200 Message-ID: <1433530943-12599-8-git-send-email-hdegoede@redhat.com> References: <1433530943-12599-1-git-send-email-hdegoede@redhat.com> Reply-To: hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <1433530943-12599-1-git-send-email-hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Maxime Ripard Cc: Chen-Yu Tsai , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree , linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Hans de Goede List-Id: devicetree@vger.kernel.org From: Chen-Yu Tsai A23/A33 has one pair of EHCI/OHCI USB controllers. There are 2 USB PHYs, one for the USB OTG controller, one for the EHCI/OHCI pair. The latter may also support HSIC, though none of the available boards utilize this, so this is not supported yet. Signed-off-by: Chen-Yu Tsai Signed-off-by: Hans de Goede --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 7abd0ae..b9e4d56 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -332,6 +332,28 @@ #size-cells = <0>; }; + ehci0: usb@01c1a000 { + compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = ; + clocks = <&ahb1_gates 26>; + resets = <&ahb1_rst 26>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c1a400 { + compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = ; + clocks = <&ahb1_gates 29>, <&usb_clk 16>; + resets = <&ahb1_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + pio: pinctrl@01c20800 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; -- 2.4.2