From: Kyle Huey <me-OhBmq/TcCDJWk0Htik3J/w@public.gmane.org>
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Kyle Huey <khuey-OhBmq/TcCDJWk0Htik3J/w@public.gmane.org>
Subject: [PATCH] ARM: tegra124: pmu support
Date: Fri, 12 Jun 2015 21:21:23 -0700 [thread overview]
Message-ID: <1434169283-19512-1-git-send-email-khuey@kylehuey.com> (raw)
This patch modifies the device tree for tegra124 based devices to enable the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM DP-06905-001_v03p. This patch was tested on a Jetson TK1.
Signed-off-by: Kyle Huey <khuey-OhBmq/TcCDJWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 4be06c6..9032ccb 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -190,6 +190,14 @@
status = "disabled";
};
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
timer@0,60005000 {
compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
reg = <0x0 0x60005000 0x0 0x400>;
--
1.9.1
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next reply other threads:[~2015-06-13 4:21 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-13 4:21 Kyle Huey [this message]
[not found] ` <1434169283-19512-1-git-send-email-khuey-OhBmq/TcCDJWk0Htik3J/w@public.gmane.org>
2015-06-15 16:45 ` [PATCH] ARM: tegra124: pmu support Jon Hunter
[not found] ` <557F012D.5040509-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-06-15 16:59 ` Stephen Warren
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