From: Gabriel Fernandez <gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
To: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Srinivas Kandagatla
<srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org>,
Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>,
Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
Michael Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Gabriel Fernandez
<gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Peter Griffin
<peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Pankaj Dev <pankaj.dev-qxv4g6HH51o@public.gmane.org>,
Olivier Bideau <olivier.bideau-qxv4g6HH51o@public.gmane.org>,
Geert Uytterhoeven
<geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>,
Fabian Frederick <fabf-AgBVmzD5pcezQB+pC5nmwQ@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
kernel-F5mvAk5X5gdBDgjK7y7TUQ@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH 0/3] ST PLL improvement
Date: Thu, 9 Jul 2015 13:57:37 +0200 [thread overview]
Message-ID: <1436443060-12866-1-git-send-email-gabriel.fernandez@linaro.org> (raw)
This patchset adds:
* Enable/Disable support for Clockgen PLLs.
* A new a9 pll for stih418 platform.
* PLL rate change implementation for DVFS
Gabriel Fernandez (3):
drivers: clk: st: Support for enable/disable in Clockgen PLLs
drivers: clk: st: PLL rate change implementation for DVFS
drivers: clk: st: Correct the pll-type for A9 for stih418
.../devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 +
drivers/clk/st/clkgen-mux.c | 3 +
drivers/clk/st/clkgen-pll.c | 470 ++++++++++++++++++++-
drivers/clk/st/clkgen.h | 2 +
4 files changed, 468 insertions(+), 8 deletions(-)
--
1.9.1
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next reply other threads:[~2015-07-09 11:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-09 11:57 Gabriel Fernandez [this message]
[not found] ` <1436443060-12866-1-git-send-email-gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2015-07-09 11:57 ` [PATCH 1/3] drivers: clk: st: Support for enable/disable in Clockgen PLLs Gabriel Fernandez
[not found] ` <1436443060-12866-2-git-send-email-gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2015-07-15 23:48 ` Stephen Boyd
2015-07-09 11:57 ` [PATCH 2/3] drivers: clk: st: PLL rate change implementation for DVFS Gabriel Fernandez
2015-07-09 11:57 ` [PATCH 3/3] drivers: clk: st: Correct the pll-type for A9 for stih418 Gabriel Fernandez
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