From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yong Wu Subject: Re: [PATCH v3 5/6] iommu/mediatek: Add mt8173 IOMMU driver Date: Fri, 24 Jul 2015 13:43:13 +0800 Message-ID: <1437716593.23932.73.camel@mhfsdcap03> References: <1437037475-9065-1-git-send-email-yong.wu@mediatek.com> <1437037475-9065-6-git-send-email-yong.wu@mediatek.com> <20150721145910.GG31095@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20150721145910.GG31095-5wv7dgnIgG8@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Will Deacon Cc: Mark Rutland , Catalin Marinas , "cloud.chou-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org" , "frederic.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "arnd-r2nGTMty4D4@public.gmane.org" , Tomasz Figa , Rob Herring , "linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , Matthias Brugger , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "pebolle-IWqWACnzNjzz+pZb47iToQ@public.gmane.org" , Thierry Reding , "srv_heupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , Daniel Kurtz , Sasha Hauer List-Id: devicetree@vger.kernel.org On Tue, 2015-07-21 at 15:59 +0100, Will Deacon wrote: > Hi Yong Wu, > > On Thu, Jul 16, 2015 at 10:04:34AM +0100, Yong Wu wrote: > > This patch adds support for mediatek m4u (MultiMedia Memory Management > > Unit). > > [...] > > > +static void mtk_iommu_tlb_flush_all(void *cookie) > > +{ > > + struct mtk_iommu_domain *domain = cookie; > > + void __iomem *base; > > + > > + base = domain->data->base; > > + writel(F_INVLD_EN1 | F_INVLD_EN0, base + REG_MMU_INV_SEL); > > + writel(F_ALL_INVLD, base + REG_MMU_INVALIDATE); > > This needs to be synchronous, so you probably want to call > mtk_iommu_tlb_sync at the end. >>From our spec, we have to wait until HW done after tlb flush range. But it don't need wait after tlb flush all. so It isn't necessary to add mtk_iommu_tlb_sync in tlb_flush_all here. > > > +} > > + > > +static void mtk_iommu_tlb_add_flush(unsigned long iova, size_t size, > > + bool leaf, void *cookie) > > +{ > > + struct mtk_iommu_domain *domain = cookie; > > + void __iomem *base = domain->data->base; > > + unsigned int iova_start = iova, iova_end = iova + size - 1; > > + > > + writel(F_INVLD_EN1 | F_INVLD_EN0, base + REG_MMU_INV_SEL); > > + > > + writel(iova_start, base + REG_MMU_INVLD_START_A); > > + writel(iova_end, base + REG_MMU_INVLD_END_A); > > + writel(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE); > > Why are you using writel instead of writel_relaxed? I asked this before > but I don't think you replied. Sorry, I didn't notice _relax last time. I will improve in next version. Thanks very much. > > Will