[PATCHv2 0/4] reset: socfpga: Add reset driver support for Arria10 platform

[PATCHv2 0/4] reset: socfpga: Add reset driver support for Arria10 platform

[dinguyen]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

v2: For the reset driver, assume a modrst-offset of 0x10 in order to support
    legacy boards that do have the property..

v1:
This patch series adds reset driver support for the SoCFPGA Arria10 SOC. The
reset manager on the Arria10 is very similar to the one on Cyclone5/Arria5,
thus I think it's best to try to re-use the same reset driver.

The biggest difference between the reset manager on Arria10 and Cyclone is
the addition of security features. Since the driver does not support these
security features, it winds down to just a driver that will release IPs from
reset.

The other difference between Arria10 and Cyclone5 are register offsets, and
register bits for different IPs. For the register offset, the main register
offset is the very first register that is needed by the driver for releasing
IPs from reset. To handle this difference, I've introduced a new DTS property,
"altr,modrst-offset", that will represent this register.

The register bits for all the resets are in a new file:

include/dt-bindings/reset/altr,rst-mgr-a10.h

Thanks,

Dinh Nguyen (4):
  dt-bindings: Add reset manager offsets for Arria10
  ARM: socfpga: dts: add "altr,modrst-offset" property
  reset: socfpga: Update reset-socfpga to read the altr,modrst-offset
    property
  ARM: socfpga: dts: Add resets for EMACs on Arria10

 .../devicetree/bindings/reset/socfpga-reset.txt    |   2 +
 arch/arm/boot/dts/socfpga.dtsi                     |   1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi             |   6 ++
 drivers/reset/reset-socfpga.c                      |  19 ++--
 include/dt-bindings/reset/altr,rst-mgr-a10.h       | 110 +++++++++++++++++++++
 5 files changed, 132 insertions(+), 6 deletions(-)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

-- 
2.4.5

[PATCHv2 1/4] dt-bindings: Add reset manager offsets for Arria10

[dinguyen]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

The reset manager for is pretty similar to the one for SoCFPGA
cyclone5/arria5 except for a few offsets. This patch adds those offsets.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 include/dt-bindings/reset/altr,rst-mgr-a10.h | 110 +++++++++++++++++++++++++++
 1 file changed, 110 insertions(+)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 0000000..acb0bbf
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET		0
+#define CPU1_RESET		1
+#define WDS_RESET		2
+#define SCUPER_RESET		3
+
+/* PER0MODRST */
+#define EMAC0_RESET		32
+#define EMAC1_RESET		33
+#define EMAC2_RESET		34
+#define USB0_RESET		35
+#define USB1_RESET		36
+#define NAND_RESET		37
+#define QSPI_RESET		38
+#define SDMMC_RESET		39
+#define EMAC0_OCP_RESET		40
+#define EMAC1_OCP_RESET		41
+#define EMAC2_OCP_RESET		42
+#define USB0_OCP_RESET		43
+#define USB1_OCP_RESET		44
+#define NAND_OCP_RESET		45
+#define QSPI_OCP_RESET		46
+#define SDMMC_OCP_RESET		47
+#define DMA_RESET		48
+#define SPIM0_RESET		49
+#define SPIM1_RESET		50
+#define SPIS0_RESET		51
+#define SPIS1_RESET		52
+#define DMA_OCP_RESET		53
+#define EMAC_PTP_RESET		54
+/* 55 is empty*/
+#define DMAIF0_RESET		56
+#define DMAIF1_RESET		57
+#define DMAIF2_RESET		58
+#define DMAIF3_RESET		59
+#define DMAIF4_RESET		60
+#define DMAIF5_RESET		61
+#define DMAIF6_RESET		62
+#define DMAIF7_RESET		63
+
+/* PER1MODRST */
+#define L4WD0_RESET		64
+#define L4WD1_RESET		65
+#define L4SYSTIMER0_RESET	66
+#define L4SYSTIMER1_RESET	67
+#define SPTIMER0_RESET		68
+#define SPTIMER1_RESET		69
+/* 70-71 is reserved */
+#define I2C0_RESET		72
+#define I2C1_RESET		73
+#define I2C2_RESET		74
+#define I2C3_RESET		75
+#define I2C4_RESET		76
+/* 77-79 is reserved */
+#define UART0_RESET		80
+#define UART1_RESET		81
+/* 82-87 is reserved */
+#define GPIO0_RESET		88
+#define GPIO1_RESET		89
+#define GPIO2_RESET		90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET		96
+#define LWHPS2FPGA_RESET	97
+#define FPGA2HPS_RESET		98
+#define F2SSDRAM0_RESET		99
+#define F2SSDRAM1_RESET		100
+#define F2SSDRAM2_RESET		101
+#define DDRSCH_RESET		102
+
+/* SYSMODRST*/
+#define ROM_RESET		128
+#define OCRAM_RESET		129
+/* 130 is reserved */
+#define FPGAMGR_RESET		131
+#define S2F_RESET		132
+#define SYSDBG_RESET		133
+#define OCRAM_OCP_RESET		134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET	160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET		163
+#define TIMESTAMPCOLD_RESET	164
+#define TAPCOLD_RESET		165
+#define HMCCOLD_RESET		166
+#define IOMGRCOLD_RESET		167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET		192
+
+/* DBGMODRST */
+#define DBG_RESET		224
+#endif
-- 
2.4.5

[PATCHv2 2/4] ARM: socfpga: dts: add "altr,modrst-offset" property

[dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

The "altr,modrst-offset" property represents the offset into the reset manager
that is the first register to be used by the driver to bring peripherals out
of reset.

Signed-off-by: Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
 Documentation/devicetree/bindings/reset/socfpga-reset.txt | 2 ++
 arch/arm/boot/dts/socfpga.dtsi                            | 1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi                    | 1 +
 3 files changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/socfpga-reset.txt b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
index 32c1c8b..98c9f56 100644
--- a/Documentation/devicetree/bindings/reset/socfpga-reset.txt
+++ b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
@@ -3,6 +3,7 @@ Altera SOCFPGA Reset Manager
 Required properties:
 - compatible : "altr,rst-mgr"
 - reg : Should contain 1 register ranges(address and length)
+- altr,modrst-offset : Should contain the offset of the first modrst register.
 - #reset-cells: 1
 
 Example:
@@ -10,4 +11,5 @@ Example:
 		#reset-cells = <1>;
 		compatible = "altr,rst-mgr";
 		reg = <0xffd05000 0x1000>;
+		altr,modrst-offset = <0x10>;
 	};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 86e0fb6..0bda96a 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -783,6 +783,7 @@
 			#reset-cells = <1>;
 			compatible = "altr,rst-mgr";
 			reg = <0xffd05000 0x1000>;
+			altr,modrst-offset = <0x10>;
 		};
 
 		usbphy0: usbphy@0 {
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a252905..22e7d82 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -593,6 +593,7 @@
 			#reset-cells = <1>;
 			compatible = "altr,rst-mgr";
 			reg = <0xffd05000 0x100>;
+			altr,modrst-offset = <0x20>;
 		};
 
 		scu: snoop-control-unit@ffffc000 {
-- 
2.4.5

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[PATCHv2 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

[dinguyen]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

In order for the Arria10 to be able to re-use the reset driver for SoCFPGA
Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the
device tree entry. The 'altr,modrst-offset' property is the first register
into the reset manager that is used for bringing peripherals out of reset.

The driver assumes a modrst-offset of 0x10 in order to support legacy
Cyclone5/Arria5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: assume a modrst-offset of 0x10 if the property is not specified in order
    to support legacy boards that do not have the property.
---
 drivers/reset/reset-socfpga.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 0a8def3..1a6c5d6 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -24,11 +24,11 @@
 #include <linux/types.h>
 
 #define NR_BANKS		4
-#define OFFSET_MODRST		0x10
 
 struct socfpga_reset_data {
 	spinlock_t			lock;
 	void __iomem			*membase;
+	u32				modrst_offset;
 	struct reset_controller_dev	rcdev;
 };
 
@@ -45,8 +45,8 @@ static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
-	writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
+	reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
+	writel(reg | BIT(offset), data->membase + data->modrst_offset +
 				 (bank * NR_BANKS));
 	spin_unlock_irqrestore(&data->lock, flags);
 
@@ -67,8 +67,8 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
-	writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
+	reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
+	writel(reg & ~BIT(offset), data->membase + data->modrst_offset +
 				  (bank * NR_BANKS));
 
 	spin_unlock_irqrestore(&data->lock, flags);
@@ -85,7 +85,7 @@ static int socfpga_reset_status(struct reset_controller_dev *rcdev,
 	int offset = id % BITS_PER_LONG;
 	u32 reg;
 
-	reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
+	reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
 
 	return !(reg & BIT(offset));
 }
@@ -100,6 +100,8 @@ static int socfpga_reset_probe(struct platform_device *pdev)
 {
 	struct socfpga_reset_data *data;
 	struct resource *res;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
 
 	/*
 	 * The binding was mainlined without the required property.
@@ -120,6 +122,11 @@ static int socfpga_reset_probe(struct platform_device *pdev)
 	if (IS_ERR(data->membase))
 		return PTR_ERR(data->membase);
 
+	if (of_property_read_u32(np, "altr,modrst-offset", &data->modrst_offset)) {
+		dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
+		data->modrst_offset = 0x10;
+	}
+
 	spin_lock_init(&data->lock);
 
 	data->rcdev.owner = THIS_MODULE;
-- 
2.4.5

[PATCHv2 4/4] ARM: socfpga: dts: Add resets for EMACs on Arria10

[dinguyen]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add the reset property for the EMAC controllers on Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 22e7d82..2340fcb 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -16,6 +16,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/altr,rst-mgr-a10.h>
 
 / {
 	#address-cells = <1>;
@@ -414,6 +415,8 @@
 			rx-fifo-depth = <16384>;
 			clocks = <&l4_mp_clk>;
 			clock-names = "stmmaceth";
+			resets = <&rst EMAC0_RESET>;
+			reset-names = "stmmaceth";
 			status = "disabled";
 		};
 
@@ -431,6 +434,8 @@
 			rx-fifo-depth = <16384>;
 			clocks = <&l4_mp_clk>;
 			clock-names = "stmmaceth";
+			resets = <&rst EMAC1_RESET>;
+			reset-names = "stmmaceth";
 			status = "disabled";
 		};
 
-- 
2.4.5

Re: [PATCHv2 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

[Philipp Zabel]

Hi Dinh,

Am Freitag, den 31.07.2015, 16:03 -0500 schrieb
dinguyen@opensource.altera.com:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> In order for the Arria10 to be able to re-use the reset driver for SoCFPGA
> Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the
> device tree entry. The 'altr,modrst-offset' property is the first register
> into the reset manager that is used for bringing peripherals out of reset.
> 
> The driver assumes a modrst-offset of 0x10 in order to support legacy
> Cyclone5/Arria5 hardware.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Applied, thanks.

regards
Philipp

> ---
> v2: assume a modrst-offset of 0x10 if the property is not specified in order
>     to support legacy boards that do not have the property.
> ---
>  drivers/reset/reset-socfpga.c | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
> index 0a8def3..1a6c5d6 100644
> --- a/drivers/reset/reset-socfpga.c
> +++ b/drivers/reset/reset-socfpga.c
> @@ -24,11 +24,11 @@
>  #include <linux/types.h>
>  
>  #define NR_BANKS		4
> -#define OFFSET_MODRST		0x10
>  
>  struct socfpga_reset_data {
>  	spinlock_t			lock;
>  	void __iomem			*membase;
> +	u32				modrst_offset;
>  	struct reset_controller_dev	rcdev;
>  };
>  
> @@ -45,8 +45,8 @@ static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
>  
>  	spin_lock_irqsave(&data->lock, flags);
>  
> -	reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> -	writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
> +	reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
> +	writel(reg | BIT(offset), data->membase + data->modrst_offset +
>  				 (bank * NR_BANKS));
>  	spin_unlock_irqrestore(&data->lock, flags);
>  
> @@ -67,8 +67,8 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
>  
>  	spin_lock_irqsave(&data->lock, flags);
>  
> -	reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> -	writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
> +	reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
> +	writel(reg & ~BIT(offset), data->membase + data->modrst_offset +
>  				  (bank * NR_BANKS));
>  
>  	spin_unlock_irqrestore(&data->lock, flags);
> @@ -85,7 +85,7 @@ static int socfpga_reset_status(struct reset_controller_dev *rcdev,
>  	int offset = id % BITS_PER_LONG;
>  	u32 reg;
>  
> -	reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
> +	reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
>  
>  	return !(reg & BIT(offset));
>  }
> @@ -100,6 +100,8 @@ static int socfpga_reset_probe(struct platform_device *pdev)
>  {
>  	struct socfpga_reset_data *data;
>  	struct resource *res;
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
>  
>  	/*
>  	 * The binding was mainlined without the required property.
> @@ -120,6 +122,11 @@ static int socfpga_reset_probe(struct platform_device *pdev)
>  	if (IS_ERR(data->membase))
>  		return PTR_ERR(data->membase);
>  
> +	if (of_property_read_u32(np, "altr,modrst-offset", &data->modrst_offset)) {
> +		dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
> +		data->modrst_offset = 0x10;
> +	}
> +
>  	spin_lock_init(&data->lock);
>  
>  	data->rcdev.owner = THIS_MODULE;