[RFC PATCH v3 0/5]

[RFC PATCH v3 0/5]

[Shawn Lin]

Synopsys DesignWare mobile storage host controller supports three
types of transfer mode: pio, internal dma and external dma. However,
dw_mmc can only supports pio and internal dma now. Thus some platforms
using dw-mshc integrated with generic dma can't work in dma mode. So we
submit this patch to achieve it.

And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
(commit:f95f3850) for the first version of dw_mmc and never be touched from
then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
time. Nowadays, device-tree helps us to support a variety of boards with one
kernel. That's why we need to remove it and decide the transfer mode at runtime.

This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
to make the running.

Patch does the following things:
- remove CONFIG_MMC_DW_IDMAC config option
- add bindings for idmac and edmac used by synopsys-dw-mshc
  at runtime
- add edmac support for synopsys-dw-mshc

Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc


Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

Shawn Lin (5):
  mmc: dw_mmc: Add external dma interface support
  Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
  arm: configs: remove CONFIG_MMC_DW_IDMAC
  mips: configs: remove CONFIG_MMC_DW_IDMAC
  ARM: dts: add supports-idmac property

 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |  41 +++
 arch/arc/configs/axs101_defconfig                  |   1 -
 arch/arc/configs/axs103_defconfig                  |   1 -
 arch/arc/configs/axs103_smp_defconfig              |   1 -
 arch/arm/boot/dts/exynos3250-monk.dts              |   1 +
 arch/arm/boot/dts/exynos3250-rinato.dts            |   1 +
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   1 +
 arch/arm/boot/dts/exynos4412-origen.dts            |   1 +
 arch/arm/boot/dts/exynos4412-trats2.dts            |   1 +
 arch/arm/boot/dts/exynos4x12.dtsi                  |   1 +
 arch/arm/boot/dts/exynos5250-arndale.dts           |   2 +
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |   2 +
 arch/arm/boot/dts/exynos5250-snow.dts              |   3 +
 arch/arm/boot/dts/exynos5250-spring.dts            |   2 +
 arch/arm/boot/dts/exynos5260-xyref5260.dts         |   2 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts          |   2 +
 arch/arm/boot/dts/exynos5420-arndale-octa.dts      |   2 +
 arch/arm/boot/dts/exynos5420-peach-pit.dts         |   3 +
 arch/arm/boot/dts/exynos5420-smdk5420.dts          |   2 +
 arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi |   2 +
 arch/arm/boot/dts/exynos5800-peach-pi.dts          |   3 +
 arch/arm/boot/dts/hisi-x5hd2.dtsi                  |   2 +
 arch/arm/boot/dts/rk3288-evb.dtsi                  |   2 +
 arch/arm/boot/dts/rk3288-firefly.dtsi              |   3 +
 arch/arm/boot/dts/rk3288-popmetal.dts              |   2 +
 arch/arm/configs/exynos_defconfig                  |   1 -
 arch/arm/configs/hisi_defconfig                    |   1 -
 arch/arm/configs/lpc18xx_defconfig                 |   1 -
 arch/arm/configs/multi_v7_defconfig                |   1 -
 arch/arm/configs/zx_defconfig                      |   1 -
 arch/arm64/boot/dts/exynos/exynos7-espresso.dts    |   2 +
 arch/mips/configs/pistachio_defconfig              |   1 -
 drivers/mmc/host/Kconfig                           |  11 +-
 drivers/mmc/host/dw_mmc-pltfm.c                    |   2 +
 drivers/mmc/host/dw_mmc.c                          | 277 +++++++++++++++++----
 include/linux/mmc/dw_mmc.h                         |  28 ++-
 36 files changed, 338 insertions(+), 72 deletions(-)

-- 
2.3.7

[RFC PATCH v3 1/5] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK312x
platform with edmac mode and RK3288 platform with idmac mode.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

---

Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms

Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave

 drivers/mmc/host/Kconfig        |  11 +-
 drivers/mmc/host/dw_mmc-pltfm.c |   2 +
 drivers/mmc/host/dw_mmc.c       | 277 +++++++++++++++++++++++++++++++++-------
 include/linux/mmc/dw_mmc.h      |  28 +++-
 4 files changed, 255 insertions(+), 63 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6a0f9c7..a86c0eb 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -607,15 +607,7 @@ config MMC_DW
 	help
 	  This selects support for the Synopsys DesignWare Mobile Storage IP
 	  block, this provides host support for SD and MMC interfaces, in both
-	  PIO and external DMA modes.
-
-config MMC_DW_IDMAC
-	bool "Internal DMAC interface"
-	depends on MMC_DW
-	help
-	  This selects support for the internal DMAC block within the Synopsys
-	  Designware Mobile Storage IP block. This disables the external DMA
-	  interface.
+	  PIO, internal DMA mode and external DMA modes.
 
 config MMC_DW_PLTFM
 	tristate "Synopsys Designware MCI Support as platform device"
@@ -644,7 +636,6 @@ config MMC_DW_K3
 	tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
 	depends on MMC_DW
 	select MMC_DW_PLTFM
-	select MMC_DW_IDMAC
 	help
 	  This selects support for Hisilicon K3 SoC specific extensions to the
 	  Synopsys DesignWare Memory Card Interface driver. Select this option
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
 	host->pdata = pdev->dev.platform_data;
 
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	/* Get registers' physical base address */
+	host->phy_regs = (void *)(regs->start);
 	host->regs = devm_ioremap_resource(&pdev->dev, regs);
 	if (IS_ERR(host->regs))
 		return PTR_ERR(host->regs);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 40e9d8e..9341879 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -56,7 +56,7 @@
 #define DW_MCI_FREQ_MAX	200000000	/* unit: HZ */
 #define DW_MCI_FREQ_MIN	400000		/* unit: HZ */
 
-#ifdef CONFIG_MMC_DW_IDMAC
+
 #define IDMAC_INT_CLR		(SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
 				 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
 				 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
@@ -99,7 +99,6 @@ struct idmac_desc {
 
 	__le32		des3;	/* buffer 2 physical address */
 };
-#endif /* CONFIG_MMC_DW_IDMAC */
 
 static bool dw_mci_reset(struct dw_mci *host);
 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
@@ -403,7 +402,6 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
 		return DMA_FROM_DEVICE;
 }
 
-#ifdef CONFIG_MMC_DW_IDMAC
 static void dw_mci_dma_cleanup(struct dw_mci *host)
 {
 	struct mmc_data *data = host->data;
@@ -441,8 +439,9 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 	mci_writel(host, BMOD, temp);
 }
 
-static void dw_mci_idmac_complete_dma(struct dw_mci *host)
+static void dw_mci_idmac_complete_dma(void *arg)
 {
+	struct dw_mci *host = arg;
 	struct mmc_data *data = host->data;
 
 	dev_vdbg(host->dev, "DMA complete\n");
@@ -527,7 +526,7 @@ static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 	wmb();
 }
 
-static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
+static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 {
 	u32 temp;
 
@@ -551,6 +550,8 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 
 	/* Start it running */
 	mci_writel(host, PLDMND, 1);
+
+	return 0;
 }
 
 static int dw_mci_idmac_init(struct dw_mci *host)
@@ -632,7 +633,142 @@ static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 	.complete = dw_mci_idmac_complete_dma,
 	.cleanup = dw_mci_dma_cleanup,
 };
-#endif /* CONFIG_MMC_DW_IDMAC */
+
+static void dw_mci_edmac_cleanup(struct dw_mci *host)
+{
+	struct mmc_data *data = host->data;
+
+	if (data && (!data->host_cookie))
+		dma_unmap_sg(host->dev, data->sg,
+			     data->sg_len, dw_mci_get_dma_dir(data));
+}
+
+static void dw_mci_edmac_stop_dma(struct dw_mci *host)
+{
+	dmaengine_terminate_all(host->dms->ch);
+}
+
+static void dw_mci_edmac_complete_dma(void *arg)
+{
+	struct dw_mci *host = arg;
+	struct mmc_data *data = host->data;
+
+	dev_vdbg(host->dev, "DMA complete\n");
+
+	if (data && data->flags & MMC_DATA_READ)
+		/* Invalidate cache after read */
+		dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc), data->sg,
+				    data->sg_len, DMA_FROM_DEVICE);
+
+	host->dma_ops->cleanup(host);
+
+	/*
+	* If the card was removed, data will be NULL. No point in trying to
+	* send the stop command or waiting for NBUSY in this case.
+	*/
+	if (data) {
+		set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
+		tasklet_schedule(&host->tasklet);
+	}
+}
+
+static int dw_mci_edmac_start_dma(struct dw_mci *host,
+					    unsigned int sg_len)
+{
+	struct dma_slave_config cfg;
+	struct dma_async_tx_descriptor *desc = NULL;
+	struct scatterlist *sgl = host->data->sg;
+	const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
+	u32 sg_elems = host->data->sg_len;
+	u32 fifoth_val;
+	u32 fifo_offset = host->fifo_reg - host->regs;
+	int ret = 0;
+
+	/* Set external dma config: burst size, burst width */
+	cfg.dst_addr = (dma_addr_t)(host->phy_regs + fifo_offset);
+	cfg.src_addr = cfg.dst_addr;
+	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+
+	/* Match burst msize with external dma config */
+	fifoth_val = mci_readl(host, FIFOTH);
+	cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
+	cfg.src_maxburst = cfg.dst_maxburst;
+
+	if (host->data->flags & MMC_DATA_WRITE)
+		cfg.direction = DMA_MEM_TO_DEV;
+	else /* MMC_DATA_READ */
+		cfg.direction = DMA_DEV_TO_MEM;
+
+	ret = dmaengine_slave_config(host->dms->ch, &cfg);
+	if (ret) {
+		dev_err(host->dev, "Failed to config edmac.\n");
+		return -EBUSY;
+	}
+
+	desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
+				       sg_len, cfg.direction,
+				       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!desc) {
+		dev_err(host->dev, "Can't prepare slave sg.\n");
+		return -EBUSY;
+	}
+
+	/* Set dw_mci_edmac_complete_dma as callback */
+	desc->callback = dw_mci_edmac_complete_dma;
+	desc->callback_param = (void *)host;
+	dmaengine_submit(desc);
+
+	/* Flush cache before write */
+	if (host->data->flags & MMC_DATA_WRITE)
+		dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
+				       sg_elems, DMA_TO_DEVICE);
+
+	dma_async_issue_pending(host->dms->ch);
+
+	return 0;
+}
+
+static int dw_mci_edmac_init(struct dw_mci *host)
+{
+	/* Request external dma channel */
+	host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
+	if (!host->dms)
+		return -ENOMEM;
+
+	host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
+	if (!host->dms->ch) {
+		dev_err(host->dev,
+			"Failed to get external DMA channel %d\n",
+			host->dms->ch->chan_id);
+		kfree(host->dms);
+		host->dms = NULL;
+		return -ENXIO;
+	}
+
+	return 0;
+}
+
+static void dw_mci_edmac_exit(struct dw_mci *host)
+{
+	if (host->dms) {
+		if (host->dms->ch) {
+			dma_release_channel(host->dms->ch);
+			host->dms->ch = NULL;
+		}
+		kfree(host->dms);
+		host->dms = NULL;
+	}
+}
+
+static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
+	.init = dw_mci_edmac_init,
+	.exit = dw_mci_edmac_exit,
+	.start = dw_mci_edmac_start_dma,
+	.stop = dw_mci_edmac_stop_dma,
+	.complete = dw_mci_edmac_complete_dma,
+	.cleanup = dw_mci_edmac_cleanup,
+};
 
 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 				   struct mmc_data *data,
@@ -712,7 +848,6 @@ static void dw_mci_post_req(struct mmc_host *mmc,
 
 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 {
-#ifdef CONFIG_MMC_DW_IDMAC
 	unsigned int blksz = data->blksz;
 	const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 	u32 fifo_width = 1 << host->data_shift;
@@ -720,6 +855,9 @@ static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 	u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 	int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
 
+	if (host->trans_mode == TRANS_MODE_PIO)
+		return;
+
 	tx_wmark = (host->fifo_depth) / 2;
 	tx_wmark_invers = host->fifo_depth - tx_wmark;
 
@@ -748,7 +886,6 @@ static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 done:
 	fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 	mci_writel(host, FIFOTH, fifoth_val);
-#endif
 }
 
 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
@@ -835,7 +972,11 @@ static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 	mci_writel(host, INTMASK, temp);
 	spin_unlock_irqrestore(&host->irq_lock, irqflags);
 
-	host->dma_ops->start(host, sg_len);
+	if (host->dma_ops->start(host, sg_len)) {
+		/* We can't do DMA */
+		dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
+		return -ENODEV;
+	}
 
 	return 0;
 }
@@ -2256,26 +2397,30 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
 
 	}
 
-#ifdef CONFIG_MMC_DW_IDMAC
-	/* Handle DMA interrupts */
-	if (host->dma_64bit_address == 1) {
-		pending = mci_readl(host, IDSTS64);
-		if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
-			mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
-							SDMMC_IDMAC_INT_RI);
-			mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
-			host->dma_ops->complete(host);
-		}
-	} else {
-		pending = mci_readl(host, IDSTS);
-		if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
-			mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
-							SDMMC_IDMAC_INT_RI);
-			mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
-			host->dma_ops->complete(host);
+	if ((host->trans_mode == TRANS_MODE_IDMAC) && host->use_dma) {
+		/* Handle DMA interrupts */
+		if (host->dma_64bit_address == 1) {
+			pending = mci_readl(host, IDSTS64);
+			if (pending & (SDMMC_IDMAC_INT_TI |
+				       SDMMC_IDMAC_INT_RI)) {
+				mci_writel(host, IDSTS64,
+					   SDMMC_IDMAC_INT_TI |
+					   SDMMC_IDMAC_INT_RI);
+				mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
+				host->dma_ops->complete((void *)host);
+			}
+		} else {
+			pending = mci_readl(host, IDSTS);
+			if (pending & (SDMMC_IDMAC_INT_TI |
+				       SDMMC_IDMAC_INT_RI)) {
+				mci_writel(host, IDSTS,
+					   SDMMC_IDMAC_INT_TI |
+					   SDMMC_IDMAC_INT_RI);
+				mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
+				host->dma_ops->complete((void *)host);
+			}
 		}
 	}
-#endif
 
 	return IRQ_HANDLED;
 }
@@ -2391,19 +2536,29 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
 		mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
 	} else {
 		/* Useful defaults if platform data is unset. */
-#ifdef CONFIG_MMC_DW_IDMAC
-		mmc->max_segs = host->ring_size;
-		mmc->max_blk_size = 65536;
-		mmc->max_seg_size = 0x1000;
-		mmc->max_req_size = mmc->max_seg_size * host->ring_size;
-		mmc->max_blk_count = mmc->max_req_size / 512;
-#else
-		mmc->max_segs = 64;
-		mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
-		mmc->max_blk_count = 512;
-		mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
-		mmc->max_seg_size = mmc->max_req_size;
-#endif /* CONFIG_MMC_DW_IDMAC */
+		if (host->trans_mode == TRANS_MODE_IDMAC && host->use_dma) {
+			mmc->max_segs = host->ring_size;
+			mmc->max_blk_size = 65536;
+			mmc->max_seg_size = 0x1000;
+			mmc->max_req_size = mmc->max_seg_size * host->ring_size;
+			mmc->max_blk_count = mmc->max_req_size / 512;
+		} else if (host->trans_mode == TRANS_MODE_EDMAC &&
+			   host->use_dma) {
+			mmc->max_segs = 64;
+			mmc->max_blk_size = 65536;
+			mmc->max_blk_count = 65535;
+			mmc->max_req_size =
+					mmc->max_blk_size * mmc->max_blk_count;
+			mmc->max_seg_size = mmc->max_req_size;
+		} else {
+			/* TRANS_MODE_PIO */
+			mmc->max_segs = 64;
+			mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
+			mmc->max_blk_count = 512;
+			mmc->max_req_size =
+					mmc->max_blk_size * mmc->max_blk_count;
+			mmc->max_seg_size = mmc->max_req_size;
+		}
 	}
 
 	if (dw_mci_get_cd(mmc))
@@ -2437,6 +2592,11 @@ static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
 static void dw_mci_init_dma(struct dw_mci *host)
 {
 	int addr_config;
+
+	/* Check tansfer mode */
+	if (host->trans_mode == TRANS_MODE_PIO)
+		goto no_dma;
+
 	/* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
 	addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
 
@@ -2462,10 +2622,14 @@ static void dw_mci_init_dma(struct dw_mci *host)
 	}
 
 	/* Determine which DMA interface to use */
-#ifdef CONFIG_MMC_DW_IDMAC
-	host->dma_ops = &dw_mci_idmac_ops;
-	dev_info(host->dev, "Using internal DMA controller.\n");
-#endif
+	if (host->trans_mode == TRANS_MODE_IDMAC) {
+		host->dma_ops = &dw_mci_idmac_ops;
+		dev_info(host->dev, "Using internal DMA controller.\n");
+	} else {
+		/* TRANS_MODE_EDMAC */
+		host->dma_ops = &dw_mci_edmac_ops;
+		dev_info(host->dev, "Using external DMA controller.\n");
+	}
 
 	if (!host->dma_ops)
 		goto no_dma;
@@ -2570,10 +2734,9 @@ static bool dw_mci_reset(struct dw_mci *host)
 		}
 	}
 
-#if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
-	/* It is also recommended that we reset and reprogram idmac */
-	dw_mci_idmac_reset(host);
-#endif
+	if (host->trans_mode == TRANS_MODE_IDMAC)
+		/* It is also recommended that we reset and reprogram idmac */
+		dw_mci_idmac_reset(host);
 
 	ret = true;
 
@@ -2653,6 +2816,21 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
 	if (of_find_property(np, "supports-highspeed", NULL))
 		pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
 
+	if (of_find_property(np, "supports-idmac", NULL)) {
+		host->trans_mode = TRANS_MODE_IDMAC;
+		if (of_find_property(np, "supports-edmac", NULL)) {
+			dev_err(dev, "can't configure idmac & edmac simultaneously\n");
+			/* Force pio mode */
+			host->trans_mode = TRANS_MODE_PIO;
+		}
+
+	} else if (of_find_property(np, "supports-edmac", NULL)) {
+		host->trans_mode = TRANS_MODE_EDMAC;
+	} else {
+		/* Default use pio */
+		host->trans_mode = TRANS_MODE_PIO;
+	}
+
 	return pdata;
 }
 
@@ -2958,6 +3136,9 @@ EXPORT_SYMBOL(dw_mci_remove);
  */
 int dw_mci_suspend(struct dw_mci *host)
 {
+	if (host->use_dma && host->dma_ops->exit)
+		host->dma_ops->exit(host);
+
 	return 0;
 }
 EXPORT_SYMBOL(dw_mci_suspend);
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index 5be9767..6c1c7ea 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -16,6 +16,7 @@
 
 #include <linux/scatterlist.h>
 #include <linux/mmc/core.h>
+#include <linux/dmaengine.h>
 
 #define MAX_MCI_SLOTS	2
 
@@ -40,6 +41,17 @@ enum {
 
 struct mmc_data;
 
+enum {
+	TRANS_MODE_PIO = 0,
+	TRANS_MODE_IDMAC,
+	TRANS_MODE_EDMAC
+};
+
+struct dw_mci_dma_slave {
+	struct dma_chan *ch;
+	enum dma_transfer_direction direction;
+};
+
 /**
  * struct dw_mci - MMC controller state shared between all slots
  * @lock: Spinlock protecting the queue and associated data.
@@ -147,17 +159,23 @@ struct dw_mci {
 
 	/* DMA interface members*/
 	int			use_dma;
+	int			trans_mode;
 	int			using_dma;
 	int			dma_64bit_address;
 
 	dma_addr_t		sg_dma;
 	void			*sg_cpu;
 	const struct dw_mci_dma_ops	*dma_ops;
-#ifdef CONFIG_MMC_DW_IDMAC
+	/* For idmac */
 	unsigned int		ring_size;
-#else
+
+	/* For edmac */
+	struct dw_mci_dma_slave *dms;
+	/* Registers's physical base address */
+	void                    *phy_regs;
+
 	struct dw_mci_dma_data	*dma_data;
-#endif
+
 	u32			cmd_status;
 	u32			data_status;
 	u32			stop_cmdr;
@@ -210,8 +228,8 @@ struct dw_mci {
 struct dw_mci_dma_ops {
 	/* DMA Ops */
 	int (*init)(struct dw_mci *host);
-	void (*start)(struct dw_mci *host, unsigned int sg_len);
-	void (*complete)(struct dw_mci *host);
+	int (*start)(struct dw_mci *host, unsigned int sg_len);
+	void (*complete)(void *host);
 	void (*stop)(struct dw_mci *host);
 	void (*cleanup)(struct dw_mci *host);
 	void (*exit)(struct dw_mci *host);
-- 
2.3.7

[RFC PATCH v3 2/5] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Shawn Lin]

synopsys-dw-mshc supports three types of transfer mode. We add bindings
and description for how to use them at runtime. Without idmac and edmac
property, pio is the default transfer mode. Make sure that Idmac and emdac
should not be used simultaneously.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

Changes in v3: None
Changes in v2: None

 .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   | 41 ++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 346c609..30369cb 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -75,6 +75,25 @@ Optional properties:
 * vmmc-supply: The phandle to the regulator to use for vmmc.  If this is
   specified we'll defer probe until we can find this regulator.
 
+* supports-idmac: Enables support for internal DMAC block within the Synopsys
+  Designware Mobile Storage IP block. If supports-idmac property is present, then
+  we MUST NOT add supports-edmac property since we'd assume that dw-mshc IP is
+  integrated with only one type of dma master.
+
+* supports-edmac: Enables support for external DMAC block outside the Synopsys
+  Designware Mobile Storage IP block. If supports-edmac property is present, then
+  we MUST NOT add supports-idmac property since we'd assume that dw-mshc IP is
+  integrated with only one type of dma master.
+
+  (Without "supports-idmac" and "supports-edmac", use PIO as default transfer mode)
+
+* dmas: List of DMA specifiers with the controller specific format as described
+  in the generic DMA client binding. This property should be combined with
+  supports-edmac. Refer to dma.txt for details.
+
+* dma-names: DMA request names. Must be "rx-tx". And This property should be
+  combined with supports-edmac. Refer to dma.txt for details.
+
 Aliases:
 
 - All the MSHC controller nodes should be represented in the aliases node using
@@ -95,6 +114,8 @@ board specific portions as listed below.
 		#size-cells = <0>;
 	};
 
+[board specific internal DMA resources]
+
 	dwmmc0@12200000 {
 		clock-frequency = <400000000>;
 		clock-freq-min-max = <400000 200000000>;
@@ -106,4 +127,24 @@ board specific portions as listed below.
 		bus-width = <8>;
 		cap-mmc-highspeed;
 		cap-sd-highspeed;
+		supports-idmac;
 	};
+
+[board specific generic DMA request binding]
+
+	dwmmc0@12200000 {
+		clock-frequency = <400000000>;
+		clock-freq-min-max = <400000 200000000>;
+		num-slots = <1>;
+		broken-cd;
+		fifo-depth = <0x80>;
+		card-detect-delay = <200>;
+		vmmc-supply = <&buck8>;
+		bus-width = <8>;
+		cap-mmc-highspeed;
+		cap-sd-highspeed;
+		supports-edmac;
+		dmas = <&pdma 12>;
+		dma-names = "rx-tx";
+	};
+
-- 
2.3.7

[RFC PATCH v3 3/5] arm: configs: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option, and elaborate more in Documentation(synopsys-dw-mshc).

Modify these files:
arch/arc/configs/axs101_defconfig
arch/arc/configs/axs103_defconfig
arch/arc/configs/axs103_smp_defconfig
arch/arm/configs/exynos_defconfig
arch/arm/configs/hisi_defconfig
arch/arm/configs/lpc18xx_defconfig
arch/arm/configs/multi_v7_defconfig
arch/arm/configs/zx_defconfig

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

Changes in v3: None
Changes in v2: None

 arch/arc/configs/axs101_defconfig     | 1 -
 arch/arc/configs/axs103_defconfig     | 1 -
 arch/arc/configs/axs103_smp_defconfig | 1 -
 arch/arm/configs/exynos_defconfig     | 1 -
 arch/arm/configs/hisi_defconfig       | 1 -
 arch/arm/configs/lpc18xx_defconfig    | 1 -
 arch/arm/configs/multi_v7_defconfig   | 1 -
 arch/arm/configs/zx_defconfig         | 1 -
 8 files changed, 8 deletions(-)

diff --git a/arch/arc/configs/axs101_defconfig b/arch/arc/configs/axs101_defconfig
index 562dac6..c92c0ef 100644
--- a/arch/arc/configs/axs101_defconfig
+++ b/arch/arc/configs/axs101_defconfig
@@ -89,7 +89,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_defconfig b/arch/arc/configs/axs103_defconfig
index 83a6d8d..cfac24e 100644
--- a/arch/arc/configs/axs103_defconfig
+++ b/arch/arc/configs/axs103_defconfig
@@ -95,7 +95,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arc/configs/axs103_smp_defconfig b/arch/arc/configs/axs103_smp_defconfig
index f1e1c84..9922a11 100644
--- a/arch/arc/configs/axs103_smp_defconfig
+++ b/arch/arc/configs/axs103_smp_defconfig
@@ -96,7 +96,6 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 9504e77..7e4af6e 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -161,7 +161,6 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_SDHCI_S3C_DMA=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX77686=y
diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index 5997dbc..b2e340b 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -69,7 +69,6 @@ CONFIG_NOP_USB_XCEIV=y
 CONFIG_MMC=y
 CONFIG_RTC_CLASS=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
diff --git a/arch/arm/configs/lpc18xx_defconfig b/arch/arm/configs/lpc18xx_defconfig
index 1c47f86..b7e8cda 100644
--- a/arch/arm/configs/lpc18xx_defconfig
+++ b/arch/arm/configs/lpc18xx_defconfig
@@ -119,7 +119,6 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_PCA9532=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 5fd8df6..a3734b5 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -520,7 +520,6 @@ CONFIG_MMC_ATMELMCI=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_MMC_SDHI=y
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/arch/arm/configs/zx_defconfig b/arch/arm/configs/zx_defconfig
index b200bb0..ab683fb 100644
--- a/arch/arm/configs/zx_defconfig
+++ b/arch/arm/configs/zx_defconfig
@@ -83,7 +83,6 @@ CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
-- 
2.3.7

[RFC PATCH v3 4/5] mips: configs: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option, and elaborate more in Documentation(synopsys-dw-mshc).

Modify this file:
arch/mips/configs/pistachio_defconfig

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

Changes in v3: None
Changes in v2: None

 arch/mips/configs/pistachio_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/mips/configs/pistachio_defconfig b/arch/mips/configs/pistachio_defconfig
index 1646cce..013c62c 100644
--- a/arch/mips/configs/pistachio_defconfig
+++ b/arch/mips/configs/pistachio_defconfig
@@ -257,7 +257,6 @@ CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_TEST=m
 CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_RTC_CLASS=y
-- 
2.3.7

[RFC PATCH v3 5/5] ARM: dts: add supports-idmac property

[Shawn Lin]

DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. Add "supports-idmac" for
all platforms that use internal dma mode to enable this feature
at runtime.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/exynos3250-monk.dts              | 1 +
 arch/arm/boot/dts/exynos3250-rinato.dts            | 1 +
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi    | 1 +
 arch/arm/boot/dts/exynos4412-origen.dts            | 1 +
 arch/arm/boot/dts/exynos4412-trats2.dts            | 1 +
 arch/arm/boot/dts/exynos4x12.dtsi                  | 1 +
 arch/arm/boot/dts/exynos5250-arndale.dts           | 2 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts          | 2 ++
 arch/arm/boot/dts/exynos5250-snow.dts              | 3 +++
 arch/arm/boot/dts/exynos5250-spring.dts            | 2 ++
 arch/arm/boot/dts/exynos5260-xyref5260.dts         | 2 ++
 arch/arm/boot/dts/exynos5410-smdk5410.dts          | 2 ++
 arch/arm/boot/dts/exynos5420-arndale-octa.dts      | 2 ++
 arch/arm/boot/dts/exynos5420-peach-pit.dts         | 3 +++
 arch/arm/boot/dts/exynos5420-smdk5420.dts          | 2 ++
 arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 2 ++
 arch/arm/boot/dts/exynos5800-peach-pi.dts          | 3 +++
 arch/arm/boot/dts/hisi-x5hd2.dtsi                  | 2 ++
 arch/arm/boot/dts/rk3288-evb.dtsi                  | 2 ++
 arch/arm/boot/dts/rk3288-firefly.dtsi              | 3 +++
 arch/arm/boot/dts/rk3288-popmetal.dts              | 2 ++
 arch/arm64/boot/dts/exynos/exynos7-espresso.dts    | 2 ++
 22 files changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
index a5863ac..7bc707d 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -414,6 +414,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
 	bus-width = <8>;
+	supports-idmac;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 031853b..5a14c92 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -591,6 +591,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
 	bus-width = <8>;
+	supports-idmac;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index ca7d168..ff0657a 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -473,6 +473,7 @@
 	samsung,dw-mshc-ddr-timing = <1 2>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	supports-idmac;
 };
 
 &rtc {
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 84c7631..6639d74 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -483,6 +483,7 @@
 	samsung,dw-mshc-ddr-timing = <1 2>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	supports-idmac;
 };
 
 &pinctrl_1 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index afc199d..2edac0b 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -891,6 +891,7 @@
 	status = "okay";
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	supports-idmac;
 };
 
 &pmu_system_controller {
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index b77dac61..f6d3d50 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -204,6 +204,7 @@
 		fifo-depth = <0x80>;
 		clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
 		clock-names = "biu", "ciu";
+		supports-idmac;
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 7e728a1..e2fc6ed 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -531,6 +531,7 @@
 	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	supports-idmac;
 };
 
 &mmc_2 {
@@ -546,6 +547,7 @@
 	bus-width = <4>;
 	disable-wp;
 	cap-sd-highspeed;
+	supports-idmac;
 };
 
 &rtc {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 4fe186d..2bf8d86 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -357,6 +357,7 @@
 	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	supports-idmac;
 };
 
 &mmc_2 {
@@ -371,6 +372,7 @@
 	bus-width = <4>;
 	disable-wp;
 	cap-sd-highspeed;
+	supports-idmac;
 };
 
 &rtc {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index b7f4122..bee1181 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -540,6 +540,7 @@
 	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	supports-idmac;
 };
 
 &mmc_2 {
@@ -554,6 +555,7 @@
 	bus-width = <4>;
 	wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>;
 	cap-sd-highspeed;
+	supports-idmac;
 };
 
 /*
@@ -574,6 +576,7 @@
 	pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4 &wifi_en &wifi_rst>;
 	bus-width = <4>;
 	cap-sd-highspeed;
+	supports-idmac;
 	mmc-pwrseq = <&mmc3_pwrseq>;
 };
 
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index d03f9b8..5b6fdf3 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -439,6 +439,7 @@
 	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	supports-idmac;
 };
 
 /*
@@ -457,6 +458,7 @@
 	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
 	bus-width = <4>;
 	cap-sd-highspeed;
+	supports-idmac;
 };
 
 &pinctrl_0 {
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index 3daef94..061f0af 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -78,6 +78,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
 	bus-width = <8>;
+	supports-idmac;
 };
 
 &mmc_2 {
@@ -92,4 +93,5 @@
 	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
 	bus-width = <4>;
 	disable-wp;
+	supports-idmac;
 };
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index be3e025..e208ef3 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -47,6 +47,7 @@
 	samsung,dw-mshc-sdr-timing = <2 3>;
 	samsung,dw-mshc-ddr-timing = <1 2>;
 	bus-width = <8>;
+	supports-idmac;
 };
 
 &mmc_2 {
@@ -59,6 +60,7 @@
 	samsung,dw-mshc-ddr-timing = <1 2>;
 	bus-width = <4>;
 	disable-wp;
+	supports-idmac;
 };
 
 &uart0 {
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index eeb4ac2..6134efa 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -360,6 +360,7 @@
 	vmmc-supply = <&ldo10_reg>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	supports-idmac;
 };
 
 &mmc_2 {
@@ -374,6 +375,7 @@
 	vqmmc-supply = <&ldo13_reg>;
 	bus-width = <4>;
 	cap-sd-highspeed;
+	supports-idmac;
 };
 
 &pinctrl_0 {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 8f4d76c..1ea4898 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -704,6 +704,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>;
 	bus-width = <8>;
+	supports-idmac;
 };
 
 &mmc_1 {
@@ -724,6 +725,7 @@
 	cap-sd-highspeed;
 	mmc-pwrseq = <&mmc1_pwrseq>;
 	vqmmc-supply = <&buck10_reg>;
+	supports-idmac;
 };
 
 &mmc_2 {
@@ -738,6 +740,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
 	bus-width = <4>;
+	supports-idmac;
 };
 
 
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 98871f9..06b353a 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -371,6 +371,7 @@
 		     &sd0_rclk>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	supports-idmac;
 };
 
 &mmc_2 {
@@ -383,6 +384,7 @@
 	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
 	bus-width = <4>;
 	cap-sd-highspeed;
+	supports-idmac;
 };
 
 &pinctrl_0 {
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 8adf455..05e1324 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -413,6 +413,7 @@
 	cap-mmc-highspeed;
 	mmc-hs200-1_8v;
 	mmc-hs400-1_8v;
+	supports-idmac;
 };
 
 &mmc_2 {
@@ -425,6 +426,7 @@
 	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
 	bus-width = <4>;
 	cap-sd-highspeed;
+	supports-idmac;
 };
 
 &pinctrl_0 {
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7d5b386..1c1f4f1 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -667,6 +667,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>;
 	bus-width = <8>;
+	supports-idmac;
 };
 
 &mmc_1 {
@@ -687,6 +688,7 @@
 	cap-sd-highspeed;
 	mmc-pwrseq = <&mmc1_pwrseq>;
 	vqmmc-supply = <&buck10_reg>;
+	supports-idmac;
 };
 
 &mmc_2 {
@@ -701,6 +703,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
 	bus-width = <4>;
+	supports-idmac;
 };
 
 
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index c52722b..e7ce31d 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -424,6 +424,7 @@
 			clocks = <&clock HIX5HD2_MMC_CIU_RST>,
 				 <&clock HIX5HD2_MMC_BIU_CLK>;
 			clock-names = "ciu", "biu";
+			supports-idmac;
 		};
 
 		sd: mmc@1820000 {
@@ -433,6 +434,7 @@
 			clocks = <&clock HIX5HD2_SD_CIU_RST>,
 				 <&clock HIX5HD2_SD_BIU_CLK>;
 			clock-names = "ciu","biu";
+			supports-idmac;
 		};
 
 		gmac0: ethernet@1840000 {
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 844a6fb..c15d976 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -165,6 +165,7 @@
 	cap-mmc-highspeed;
 	disable-wp;
 	non-removable;
+	supports-idmac;
 	num-slots = <1>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
@@ -182,6 +183,7 @@
 	cap-sd-highspeed;
 	card-detect-delay = <200>;
 	disable-wp;			/* wp not hooked up */
+	supports-idmac;
 	num-slots = <1>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 0b42372..286212b 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -170,6 +170,7 @@
 	bus-width = <8>;
 	cap-mmc-highspeed;
 	disable-wp;
+	supports-idmac;
 	non-removable;
 	num-slots = <1>;
 	pinctrl-names = "default";
@@ -439,6 +440,7 @@
 	bus-width = <4>;
 	disable-wp;
 	non-removable;
+	supports-idmac;
 	num-slots = <1>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>;
@@ -452,6 +454,7 @@
 	cap-sd-highspeed;
 	card-detect-delay = <200>;
 	disable-wp;
+	supports-idmac;
 	num-slots = <1>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index d582811..e39b975 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -104,6 +104,7 @@
 	bus-width = <8>;
 	cap-mmc-highspeed;
 	disable-wp;
+	supports-idmac;
 	non-removable;
 	num-slots = <1>;
 	pinctrl-names = "default";
@@ -117,6 +118,7 @@
 	cap-sd-highspeed;
 	card-detect-delay = <200>;
 	disable-wp;                     /* wp not hooked up */
+	supports-idmac;
 	num-slots = <1>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 5424cc4..399e4d9 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -58,6 +58,7 @@
 	broken-cd;
 	cap-mmc-highspeed;
 	non-removable;
+	supports-idmac;
 	card-detect-delay = <200>;
 	clock-frequency = <800000000>;
 	samsung,dw-mshc-ciu-div = <3>;
@@ -81,4 +82,5 @@
 	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
 	bus-width = <4>;
 	disable-wp;
+	supports-idmac;
 };
-- 
2.3.7

Re: [RFC PATCH v3 2/5] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Krzysztof Kozlowski]

On 05.08.2015 17:17, Shawn Lin wrote:
> synopsys-dw-mshc supports three types of transfer mode. We add bindings
> and description for how to use them at runtime. Without idmac and edmac
> property, pio is the default transfer mode. Make sure that Idmac and emdac
> should not be used simultaneously.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
> 
> Changes in v3: None
> Changes in v2: None
> 
>  .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   | 41 ++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
> index 346c609..30369cb 100644
> --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
> +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
> @@ -75,6 +75,25 @@ Optional properties:
>  * vmmc-supply: The phandle to the regulator to use for vmmc.  If this is
>    specified we'll defer probe until we can find this regulator.
>  
> +* supports-idmac: Enables support for internal DMAC block within the Synopsys
> +  Designware Mobile Storage IP block. If supports-idmac property is present, then
> +  we MUST NOT add supports-edmac property since we'd assume that dw-mshc IP is
> +  integrated with only one type of dma master.
> +
> +* supports-edmac: Enables support for external DMAC block outside the Synopsys
> +  Designware Mobile Storage IP block. If supports-edmac property is present, then
> +  we MUST NOT add supports-idmac property since we'd assume that dw-mshc IP is
> +  integrated with only one type of dma master.
> +
> +  (Without "supports-idmac" and "supports-edmac", use PIO as default transfer mode)

Aren't you breaking here backward compatibility with existing DTB?

Best regards,
Krzysztof

> +
> +* dmas: List of DMA specifiers with the controller specific format as described
> +  in the generic DMA client binding. This property should be combined with
> +  supports-edmac. Refer to dma.txt for details.
> +
> +* dma-names: DMA request names. Must be "rx-tx". And This property should be
> +  combined with supports-edmac. Refer to dma.txt for details.
> +
>  Aliases:
>  
>  - All the MSHC controller nodes should be represented in the aliases node using
> @@ -95,6 +114,8 @@ board specific portions as listed below.
>  		#size-cells = <0>;
>  	};
>  
> +[board specific internal DMA resources]
> +
>  	dwmmc0@12200000 {
>  		clock-frequency = <400000000>;
>  		clock-freq-min-max = <400000 200000000>;
> @@ -106,4 +127,24 @@ board specific portions as listed below.
>  		bus-width = <8>;
>  		cap-mmc-highspeed;
>  		cap-sd-highspeed;
> +		supports-idmac;
>  	};
> +
> +[board specific generic DMA request binding]
> +
> +	dwmmc0@12200000 {
> +		clock-frequency = <400000000>;
> +		clock-freq-min-max = <400000 200000000>;
> +		num-slots = <1>;
> +		broken-cd;
> +		fifo-depth = <0x80>;
> +		card-detect-delay = <200>;
> +		vmmc-supply = <&buck8>;
> +		bus-width = <8>;
> +		cap-mmc-highspeed;
> +		cap-sd-highspeed;
> +		supports-edmac;
> +		dmas = <&pdma 12>;
> +		dma-names = "rx-tx";
> +	};
> +
> 

Re: [RFC PATCH v3 3/5] arm: configs: remove CONFIG_MMC_DW_IDMAC

[Vineet Gupta]

On Wednesday 05 August 2015 01:52 PM, Shawn Lin wrote:
> DesignWare MMC Controller's transfer mode should be decided
> at runtime instead of compile-time. So we remove this config
> option, and elaborate more in Documentation(synopsys-dw-mshc).
>
> Modify these files:
> arch/arc/configs/axs101_defconfig
> arch/arc/configs/axs103_defconfig
> arch/arc/configs/axs103_smp_defconfig

While you remove the config option from ARC defconfigs, you fail to add the
corresponding DT glue in ARC files (like you did for ARM). The pointer to DT is
contained in corresponding defconfig. Please fix that .

-Vineet

Re: [RFC PATCH v3 2/5] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Shawn Lin]

在 2015/8/5 16:27, Krzysztof Kozlowski 写道:
> On 05.08.2015 17:17, Shawn Lin wrote:
>> synopsys-dw-mshc supports three types of transfer mode. We add bindings
>> and description for how to use them at runtime. Without idmac and edmac
>> property, pio is the default transfer mode. Make sure that Idmac and emdac
>> should not be used simultaneously.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>> ---
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>   .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   | 41 ++++++++++++++++++++++
>>   1 file changed, 41 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
>> index 346c609..30369cb 100644
>> --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
>> @@ -75,6 +75,25 @@ Optional properties:
>>   * vmmc-supply: The phandle to the regulator to use for vmmc.  If this is
>>     specified we'll defer probe until we can find this regulator.
>>   
>> +* supports-idmac: Enables support for internal DMAC block within the Synopsys
>> +  Designware Mobile Storage IP block. If supports-idmac property is present, then
>> +  we MUST NOT add supports-edmac property since we'd assume that dw-mshc IP is
>> +  integrated with only one type of dma master.
>> +
>> +* supports-edmac: Enables support for external DMAC block outside the Synopsys
>> +  Designware Mobile Storage IP block. If supports-edmac property is present, then
>> +  we MUST NOT add supports-idmac property since we'd assume that dw-mshc IP is
>> +  integrated with only one type of dma master.
>> +
>> +  (Without "supports-idmac" and "supports-edmac", use PIO as default transfer mode)
> Aren't you breaking here backward compatibility with existing DTB?
>
> Best regards,
> Krzysztof

  Thanks, Krzysztof.
  I guess you mean that I should keep existing DTB w/o these two 
properties work fine using idmac?
>> +
>> +* dmas: List of DMA specifiers with the controller specific format as described
>> +  in the generic DMA client binding. This property should be combined with
>> +  supports-edmac. Refer to dma.txt for details.
>> +
>> +* dma-names: DMA request names. Must be "rx-tx". And This property should be
>> +  combined with supports-edmac. Refer to dma.txt for details.
>> +
>>   Aliases:
>>   
>>   - All the MSHC controller nodes should be represented in the aliases node using
>> @@ -95,6 +114,8 @@ board specific portions as listed below.
>>   		#size-cells = <0>;
>>   	};
>>   
>> +[board specific internal DMA resources]
>> +
>>   	dwmmc0@12200000 {
>>   		clock-frequency = <400000000>;
>>   		clock-freq-min-max = <400000 200000000>;
>> @@ -106,4 +127,24 @@ board specific portions as listed below.
>>   		bus-width = <8>;
>>   		cap-mmc-highspeed;
>>   		cap-sd-highspeed;
>> +		supports-idmac;
>>   	};
>> +
>> +[board specific generic DMA request binding]
>> +
>> +	dwmmc0@12200000 {
>> +		clock-frequency = <400000000>;
>> +		clock-freq-min-max = <400000 200000000>;
>> +		num-slots = <1>;
>> +		broken-cd;
>> +		fifo-depth = <0x80>;
>> +		card-detect-delay = <200>;
>> +		vmmc-supply = <&buck8>;
>> +		bus-width = <8>;
>> +		cap-mmc-highspeed;
>> +		cap-sd-highspeed;
>> +		supports-edmac;
>> +		dmas = <&pdma 12>;
>> +		dma-names = "rx-tx";
>> +	};
>> +
>>
>
>
>


-- 
Shawn Lin

Re: [RFC PATCH v3 2/5] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Heiko Stübner]

Am Mittwoch, 5. August 2015, 16:43:20 schrieb Shawn Lin:
> 在 2015/8/5 16:27, Krzysztof Kozlowski 写道:
> > On 05.08.2015 17:17, Shawn Lin wrote:
> >> synopsys-dw-mshc supports three types of transfer mode. We add bindings
> >> and description for how to use them at runtime. Without idmac and edmac
> >> property, pio is the default transfer mode. Make sure that Idmac and
> >> emdac
> >> should not be used simultaneously.
> >> 
> >> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> >> ---
> >> 
> >> Changes in v3: None
> >> Changes in v2: None
> >> 
> >>   .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   | 41
> >>   ++++++++++++++++++++++ 1 file changed, 41 insertions(+)
> >> 
> >> diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
> >> b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt index
> >> 346c609..30369cb 100644
> >> --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
> >> +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
> >> 
> >> @@ -75,6 +75,25 @@ Optional properties:
> >>   * vmmc-supply: The phandle to the regulator to use for vmmc.  If this
> >>   is
> >>   
> >>     specified we'll defer probe until we can find this regulator.
> >> 
> >> +* supports-idmac: Enables support for internal DMAC block within the
> >> Synopsys +  Designware Mobile Storage IP block. If supports-idmac
> >> property is present, then +  we MUST NOT add supports-edmac property
> >> since we'd assume that dw-mshc IP is +  integrated with only one type of
> >> dma master.
> >> +
> >> +* supports-edmac: Enables support for external DMAC block outside the
> >> Synopsys +  Designware Mobile Storage IP block. If supports-edmac
> >> property is present, then +  we MUST NOT add supports-idmac property
> >> since we'd assume that dw-mshc IP is +  integrated with only one type of
> >> dma master.
> >> +
> >> +  (Without "supports-idmac" and "supports-edmac", use PIO as default
> >> transfer mode)> 
> > Aren't you breaking here backward compatibility with existing DTB?
> > 
> > Best regards,
> > Krzysztof
> 
>   Thanks, Krzysztof.
>   I guess you mean that I should keep existing DTB w/o these two
> properties work fine using idmac?

yep


> >> +
> >> +* dmas: List of DMA specifiers with the controller specific format as
> >> described +  in the generic DMA client binding. This property should be
> >> combined with +  supports-edmac. Refer to dma.txt for details.
> >> +
> >> +* dma-names: DMA request names. Must be "rx-tx". And This property
> >> should be +  combined with supports-edmac. Refer to dma.txt for details.
> >> +

Similarly the use of an external dmac could simply be detected, by the 
presence of the dma-* properties. So when the machine defines dma channels use 
the external dma, otherwise the internal (or none). So you wouldn't need 
separate new properties at all.


> >> 
> >>   Aliases:
> >>   
> >>   - All the MSHC controller nodes should be represented in the aliases
> >>   node using>> 
> >> @@ -95,6 +114,8 @@ board specific portions as listed below.
> >> 
> >>   		#size-cells = <0>;
> >>   	
> >>   	};
> >> 
> >> +[board specific internal DMA resources]
> >> +
> >> 
> >>   	dwmmc0@12200000 {
> >>   	
> >>   		clock-frequency = <400000000>;
> >>   		clock-freq-min-max = <400000 200000000>;
> >> 
> >> @@ -106,4 +127,24 @@ board specific portions as listed below.
> >> 
> >>   		bus-width = <8>;
> >>   		cap-mmc-highspeed;
> >>   		cap-sd-highspeed;
> >> 
> >> +		supports-idmac;
> >> 
> >>   	};
> >> 
> >> +
> >> +[board specific generic DMA request binding]
> >> +
> >> +	dwmmc0@12200000 {
> >> +		clock-frequency = <400000000>;
> >> +		clock-freq-min-max = <400000 200000000>;
> >> +		num-slots = <1>;
> >> +		broken-cd;
> >> +		fifo-depth = <0x80>;
> >> +		card-detect-delay = <200>;
> >> +		vmmc-supply = <&buck8>;
> >> +		bus-width = <8>;
> >> +		cap-mmc-highspeed;
> >> +		cap-sd-highspeed;
> >> +		supports-edmac;
> >> +		dmas = <&pdma 12>;
> >> +		dma-names = "rx-tx";
> >> +	};
> >> +

Re: [RFC PATCH v3 3/5] arm: configs: remove CONFIG_MMC_DW_IDMAC

[Shawn Lin]

在 2015/8/5 16:34, Vineet Gupta 写道:
> On Wednesday 05 August 2015 01:52 PM, Shawn Lin wrote:
>> DesignWare MMC Controller's transfer mode should be decided
>> at runtime instead of compile-time. So we remove this config
>> option, and elaborate more in Documentation(synopsys-dw-mshc).
>>
>> Modify these files:
>> arch/arc/configs/axs101_defconfig
>> arch/arc/configs/axs103_defconfig
>> arch/arc/configs/axs103_smp_defconfig
> While you remove the config option from ARC defconfigs, you fail to add the
> corresponding DT glue in ARC files (like you did for ARM). The pointer to DT is
> contained in corresponding defconfig. Please fix that .

Yes,  I will fix it ASAP.
Thanks, Vineet.

> -Vineet
>
>
>


-- 
Shawn Lin

Re: [RFC PATCH v3 1/5] mmc: dw_mmc: Add external dma interface support

[Heiko Stübner]

Am Mittwoch, 5. August 2015, 16:17:28 schrieb Shawn Lin:
> DesignWare MMC Controller can supports two types of DMA
> mode: external dma and internal dma. We get a RK312x platform
> integrated dw_mmc and ARM pl330 dma controller. This patch add
> edmac ops to support these platforms. I've tested it on RK312x
> platform with edmac mode and RK3288 platform with idmac mode.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> 
> ---

[...]

> diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
> index 5be9767..6c1c7ea 100644
> --- a/include/linux/mmc/dw_mmc.h
> +++ b/include/linux/mmc/dw_mmc.h
> @@ -16,6 +16,7 @@
> 
>  #include <linux/scatterlist.h>
>  #include <linux/mmc/core.h>
> +#include <linux/dmaengine.h>
> 
>  #define MAX_MCI_SLOTS	2
> 
> @@ -40,6 +41,17 @@ enum {
> 
>  struct mmc_data;
> 
> +enum {
> +	TRANS_MODE_PIO = 0,
> +	TRANS_MODE_IDMAC,
> +	TRANS_MODE_EDMAC
> +};
> +
> +struct dw_mci_dma_slave {
> +	struct dma_chan *ch;
> +	enum dma_transfer_direction direction;
> +};
> +
>  /**
>   * struct dw_mci - MMC controller state shared between all slots
>   * @lock: Spinlock protecting the queue and associated data.
> @@ -147,17 +159,23 @@ struct dw_mci {
> 
>  	/* DMA interface members*/
>  	int			use_dma;
> +	int			trans_mode;

you're introducing this new trans_mode, but we have "use_dma" already.

So you could just define

enum {
	TRANS_DMA_PIO = 0,
	TRANS_DMA_IDMAC,
	TRANS_DMA_EDMAC
};

and fill use_dma appropriately. "0" is meaning PIO already, which I also did fix 
up some days ago in "[PATCH] mmc: dw_mmc: fix pio mode when internal dmac is 
enabled" [0].


Heiko

[0] https://lkml.org/lkml/2015/8/3/407

Re: [RFC PATCH v3 5/5] ARM: dts: add supports-idmac property

[Alexey Brodkin]

Hi Shawn,

On Wed, 2015-08-05 at 16:18 +0800, Shawn Lin wrote:
> DesignWare MMC Controller's transfer mode should be decided
> at runtime instead of compile-time. Add "supports-idmac" for
> all platforms that use internal dma mode to enable this feature
> at runtime.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
> 
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm/boot/dts/exynos3250-monk.dts              | 1 +
>  arch/arm/boot/dts/exynos3250-rinato.dts            | 1 +
>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi    | 1 +
>  arch/arm/boot/dts/exynos4412-origen.dts            | 1 +
>  arch/arm/boot/dts/exynos4412-trats2.dts            | 1 +
>  arch/arm/boot/dts/exynos4x12.dtsi                  | 1 +
>  arch/arm/boot/dts/exynos5250-arndale.dts           | 2 ++
>  arch/arm/boot/dts/exynos5250-smdk5250.dts          | 2 ++
>  arch/arm/boot/dts/exynos5250-snow.dts              | 3 +++
>  arch/arm/boot/dts/exynos5250-spring.dts            | 2 ++
>  arch/arm/boot/dts/exynos5260-xyref5260.dts         | 2 ++
>  arch/arm/boot/dts/exynos5410-smdk5410.dts          | 2 ++
>  arch/arm/boot/dts/exynos5420-arndale-octa.dts      | 2 ++
>  arch/arm/boot/dts/exynos5420-peach-pit.dts         | 3 +++
>  arch/arm/boot/dts/exynos5420-smdk5420.dts          | 2 ++
>  arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 2 ++
>  arch/arm/boot/dts/exynos5800-peach-pi.dts          | 3 +++
>  arch/arm/boot/dts/hisi-x5hd2.dtsi                  | 2 ++
>  arch/arm/boot/dts/rk3288-evb.dtsi                  | 2 ++
>  arch/arm/boot/dts/rk3288-firefly.dtsi              | 3 +++
>  arch/arm/boot/dts/rk3288-popmetal.dts              | 2 ++
>  arch/arm64/boot/dts/exynos/exynos7-espresso.dts    | 2 ++
>  22 files changed, 42 insertions(+)

I'm wondering if you're going to care about other platforms
that use DW MMC?

Just grep for "snps,dw-mshc", "altr,socfpga-dw-mshc",
"img,pistachio-dw-mshc" and you'll see more dt* files to
be updated.

-Alexey

Re: [RFC PATCH v3 2/5] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Shawn Lin]

在 2015/8/5 16:45, Heiko Stübner 写道:
> Am Mittwoch, 5. August 2015, 16:43:20 schrieb Shawn Lin:
>> 在 2015/8/5 16:27, Krzysztof Kozlowski 写道:
>>> On 05.08.2015 17:17, Shawn Lin wrote:
>>>> synopsys-dw-mshc supports three types of transfer mode. We add bindings
>>>> and description for how to use them at runtime. Without idmac and edmac
>>>> property, pio is the default transfer mode. Make sure that Idmac and
>>>> emdac
>>>> should not be used simultaneously.
>>>>
>>>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>>>> ---
>>>>
>>>> Changes in v3: None
>>>> Changes in v2: None
>>>>
>>>>    .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   | 41
>>>>    ++++++++++++++++++++++ 1 file changed, 41 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
>>>> b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt index
>>>> 346c609..30369cb 100644
>>>> --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
>>>> +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
>>>>
>>>> @@ -75,6 +75,25 @@ Optional properties:
>>>>    * vmmc-supply: The phandle to the regulator to use for vmmc.  If this
>>>>    is
>>>>    
>>>>      specified we'll defer probe until we can find this regulator.
>>>>
>>>> +* supports-idmac: Enables support for internal DMAC block within the
>>>> Synopsys +  Designware Mobile Storage IP block. If supports-idmac
>>>> property is present, then +  we MUST NOT add supports-edmac property
>>>> since we'd assume that dw-mshc IP is +  integrated with only one type of
>>>> dma master.
>>>> +
>>>> +* supports-edmac: Enables support for external DMAC block outside the
>>>> Synopsys +  Designware Mobile Storage IP block. If supports-edmac
>>>> property is present, then +  we MUST NOT add supports-idmac property
>>>> since we'd assume that dw-mshc IP is +  integrated with only one type of
>>>> dma master.
>>>> +
>>>> +  (Without "supports-idmac" and "supports-edmac", use PIO as default
>>>> transfer mode)>
>>> Aren't you breaking here backward compatibility with existing DTB?
>>>
>>> Best regards,
>>> Krzysztof
>>    Thanks, Krzysztof.
>>    I guess you mean that I should keep existing DTB w/o these two
>> properties work fine using idmac?
> yep
   Okay, I got it.
>
>>>> +
>>>> +* dmas: List of DMA specifiers with the controller specific format as
>>>> described +  in the generic DMA client binding. This property should be
>>>> combined with +  supports-edmac. Refer to dma.txt for details.
>>>> +
>>>> +* dma-names: DMA request names. Must be "rx-tx". And This property
>>>> should be +  combined with supports-edmac. Refer to dma.txt for details.
>>>> +
> Similarly the use of an external dmac could simply be detected, by the
> presence of the dma-* properties. So when the machine defines dma channels use
> the external dma, otherwise the internal (or none). So you wouldn't need
> separate new properties at all.
   Thanks, Heiko.  I understand your point.
   It will be done in v4.
>
>>>>    Aliases:
>>>>    
>>>>    - All the MSHC controller nodes should be represented in the aliases
>>>>    node using>>
>>>> @@ -95,6 +114,8 @@ board specific portions as listed below.
>>>>
>>>>    		#size-cells = <0>;
>>>>    	
>>>>    	};
>>>>
>>>> +[board specific internal DMA resources]
>>>> +
>>>>
>>>>    	dwmmc0@12200000 {
>>>>    	
>>>>    		clock-frequency = <400000000>;
>>>>    		clock-freq-min-max = <400000 200000000>;
>>>>
>>>> @@ -106,4 +127,24 @@ board specific portions as listed below.
>>>>
>>>>    		bus-width = <8>;
>>>>    		cap-mmc-highspeed;
>>>>    		cap-sd-highspeed;
>>>>
>>>> +		supports-idmac;
>>>>
>>>>    	};
>>>>
>>>> +
>>>> +[board specific generic DMA request binding]
>>>> +
>>>> +	dwmmc0@12200000 {
>>>> +		clock-frequency = <400000000>;
>>>> +		clock-freq-min-max = <400000 200000000>;
>>>> +		num-slots = <1>;
>>>> +		broken-cd;
>>>> +		fifo-depth = <0x80>;
>>>> +		card-detect-delay = <200>;
>>>> +		vmmc-supply = <&buck8>;
>>>> +		bus-width = <8>;
>>>> +		cap-mmc-highspeed;
>>>> +		cap-sd-highspeed;
>>>> +		supports-edmac;
>>>> +		dmas = <&pdma 12>;
>>>> +		dma-names = "rx-tx";
>>>> +	};
>>>> +
>
>
>


-- 
Shawn Lin

Re: [RFC PATCH v3 1/5] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

在 2015/8/5 16:49, Heiko Stübner 写道:
> Am Mittwoch, 5. August 2015, 16:17:28 schrieb Shawn Lin:
>> DesignWare MMC Controller can supports two types of DMA
>> mode: external dma and internal dma. We get a RK312x platform
>> integrated dw_mmc and ARM pl330 dma controller. This patch add
>> edmac ops to support these platforms. I've tested it on RK312x
>> platform with edmac mode and RK3288 platform with idmac mode.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>>
>> ---
> [...]
>
>> diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
>> index 5be9767..6c1c7ea 100644
>> --- a/include/linux/mmc/dw_mmc.h
>> +++ b/include/linux/mmc/dw_mmc.h
>> @@ -16,6 +16,7 @@
>>
>>   #include <linux/scatterlist.h>
>>   #include <linux/mmc/core.h>
>> +#include <linux/dmaengine.h>
>>
>>   #define MAX_MCI_SLOTS	2
>>
>> @@ -40,6 +41,17 @@ enum {
>>
>>   struct mmc_data;
>>
>> +enum {
>> +	TRANS_MODE_PIO = 0,
>> +	TRANS_MODE_IDMAC,
>> +	TRANS_MODE_EDMAC
>> +};
>> +
>> +struct dw_mci_dma_slave {
>> +	struct dma_chan *ch;
>> +	enum dma_transfer_direction direction;
>> +};
>> +
>>   /**
>>    * struct dw_mci - MMC controller state shared between all slots
>>    * @lock: Spinlock protecting the queue and associated data.
>> @@ -147,17 +159,23 @@ struct dw_mci {
>>
>>   	/* DMA interface members*/
>>   	int			use_dma;
>> +	int			trans_mode;
> you're introducing this new trans_mode, but we have "use_dma" already.
>
> So you could just define
>
> enum {
> 	TRANS_DMA_PIO = 0,
> 	TRANS_DMA_IDMAC,
> 	TRANS_DMA_EDMAC
> };
>
> and fill use_dma appropriately. "0" is meaning PIO already, which I also did fix
> up some days ago in "[PATCH] mmc: dw_mmc: fix pio mode when internal dmac is
> enabled" [0].
    I  agree.  "trans_mode" is redundant here since it does the same 
work as "use_dma" to some degree.
    Thanks.
>
> Heiko
>
> [0] https://lkml.org/lkml/2015/8/3/407
>
>
>


-- 
Shawn Lin

Re: [RFC PATCH v3 5/5] ARM: dts: add supports-idmac property

[Shawn Lin]

在 2015/8/5 16:52, Alexey Brodkin 写道:
> Hi Shawn,
>
> On Wed, 2015-08-05 at 16:18 +0800, Shawn Lin wrote:
>> DesignWare MMC Controller's transfer mode should be decided
>> at runtime instead of compile-time. Add "supports-idmac" for
>> all platforms that use internal dma mode to enable this feature
>> at runtime.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>> ---
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>   arch/arm/boot/dts/exynos3250-monk.dts              | 1 +
>>   arch/arm/boot/dts/exynos3250-rinato.dts            | 1 +
>>   arch/arm/boot/dts/exynos4412-odroid-common.dtsi    | 1 +
>>   arch/arm/boot/dts/exynos4412-origen.dts            | 1 +
>>   arch/arm/boot/dts/exynos4412-trats2.dts            | 1 +
>>   arch/arm/boot/dts/exynos4x12.dtsi                  | 1 +
>>   arch/arm/boot/dts/exynos5250-arndale.dts           | 2 ++
>>   arch/arm/boot/dts/exynos5250-smdk5250.dts          | 2 ++
>>   arch/arm/boot/dts/exynos5250-snow.dts              | 3 +++
>>   arch/arm/boot/dts/exynos5250-spring.dts            | 2 ++
>>   arch/arm/boot/dts/exynos5260-xyref5260.dts         | 2 ++
>>   arch/arm/boot/dts/exynos5410-smdk5410.dts          | 2 ++
>>   arch/arm/boot/dts/exynos5420-arndale-octa.dts      | 2 ++
>>   arch/arm/boot/dts/exynos5420-peach-pit.dts         | 3 +++
>>   arch/arm/boot/dts/exynos5420-smdk5420.dts          | 2 ++
>>   arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 2 ++
>>   arch/arm/boot/dts/exynos5800-peach-pi.dts          | 3 +++
>>   arch/arm/boot/dts/hisi-x5hd2.dtsi                  | 2 ++
>>   arch/arm/boot/dts/rk3288-evb.dtsi                  | 2 ++
>>   arch/arm/boot/dts/rk3288-firefly.dtsi              | 3 +++
>>   arch/arm/boot/dts/rk3288-popmetal.dts              | 2 ++
>>   arch/arm64/boot/dts/exynos/exynos7-espresso.dts    | 2 ++
>>   22 files changed, 42 insertions(+)
> I'm wondering if you're going to care about other platforms
> that use DW MMC?
>
> Just grep for "snps,dw-mshc", "altr,socfpga-dw-mshc",
> "img,pistachio-dw-mshc" and you'll see more dt* files to
> be updated.
   Thanks,  Alexey.
   Yes,  I missed some ARC dt*  files just as Vineet told me. It will be 
fixed in v4.
   Btw, I cannot find "img,pistachio-dw-mshc" in 4.2.0-rc3. And no more 
"dw-mshc" or "dwmmc"
   is found.

> -Alexey
>
>


-- 
Shawn Lin

Re: [RFC PATCH v3 0/5]

[Krzysztof Kozlowski]

On 05.08.2015 17:16, Shawn Lin wrote:
> Synopsys DesignWare mobile storage host controller supports three
> types of transfer mode: pio, internal dma and external dma. However,
> dw_mmc can only supports pio and internal dma now. Thus some platforms
> using dw-mshc integrated with generic dma can't work in dma mode. So we
> submit this patch to achieve it.
> 
> And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
> (commit:f95f3850) for the first version of dw_mmc and never be touched from
> then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
> we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
> time. Nowadays, device-tree helps us to support a variety of boards with one
> kernel. That's why we need to remove it and decide the transfer mode at runtime.
> 
> This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
> to make the running.
> 
> Patch does the following things:
> - remove CONFIG_MMC_DW_IDMAC config option
> - add bindings for idmac and edmac used by synopsys-dw-mshc
>   at runtime
> - add edmac support for synopsys-dw-mshc
> 
> Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc
> 
> 
> Changes in v3:
> - choose transfer mode at runtime
> - remove all CONFIG_MMC_DW_IDMAC config option
> - add supports-idmac property for some platforms
> 
> Changes in v2:
> - Fix typo of dev_info msg
> - remove unused dmach from declaration of dw_mci_dma_slave
> 
> Shawn Lin (5):
>   mmc: dw_mmc: Add external dma interface support
>   Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
>   arm: configs: remove CONFIG_MMC_DW_IDMAC
>   mips: configs: remove CONFIG_MMC_DW_IDMAC
>   ARM: dts: add supports-idmac property

Please fix the title of cover letter.

You CC-ed a lot of people. Probably the whole output of git_maintainers
which is not necessary. This means that your patches did not reach some
of the mailing lists because of too many recipients. I received your
patchset but I can't find it on any of the lists I subscribe.

Please CC only REAL maintainers, not committers.

Additionally if DTS changes do not have to be introduced atomically
please split it per sub-architecture. Of course that applies only in
case of bisectable patches. And the patchset should preserve
bisectability and backward compatibility (mentioned earlier).

Best regards,
Krzysztof


> 
>  .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |  41 +++
>  arch/arc/configs/axs101_defconfig                  |   1 -
>  arch/arc/configs/axs103_defconfig                  |   1 -
>  arch/arc/configs/axs103_smp_defconfig              |   1 -
>  arch/arm/boot/dts/exynos3250-monk.dts              |   1 +
>  arch/arm/boot/dts/exynos3250-rinato.dts            |   1 +
>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   1 +
>  arch/arm/boot/dts/exynos4412-origen.dts            |   1 +
>  arch/arm/boot/dts/exynos4412-trats2.dts            |   1 +
>  arch/arm/boot/dts/exynos4x12.dtsi                  |   1 +
>  arch/arm/boot/dts/exynos5250-arndale.dts           |   2 +
>  arch/arm/boot/dts/exynos5250-smdk5250.dts          |   2 +
>  arch/arm/boot/dts/exynos5250-snow.dts              |   3 +
>  arch/arm/boot/dts/exynos5250-spring.dts            |   2 +
>  arch/arm/boot/dts/exynos5260-xyref5260.dts         |   2 +
>  arch/arm/boot/dts/exynos5410-smdk5410.dts          |   2 +
>  arch/arm/boot/dts/exynos5420-arndale-octa.dts      |   2 +
>  arch/arm/boot/dts/exynos5420-peach-pit.dts         |   3 +
>  arch/arm/boot/dts/exynos5420-smdk5420.dts          |   2 +
>  arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi |   2 +
>  arch/arm/boot/dts/exynos5800-peach-pi.dts          |   3 +
>  arch/arm/boot/dts/hisi-x5hd2.dtsi                  |   2 +
>  arch/arm/boot/dts/rk3288-evb.dtsi                  |   2 +
>  arch/arm/boot/dts/rk3288-firefly.dtsi              |   3 +
>  arch/arm/boot/dts/rk3288-popmetal.dts              |   2 +
>  arch/arm/configs/exynos_defconfig                  |   1 -
>  arch/arm/configs/hisi_defconfig                    |   1 -
>  arch/arm/configs/lpc18xx_defconfig                 |   1 -
>  arch/arm/configs/multi_v7_defconfig                |   1 -
>  arch/arm/configs/zx_defconfig                      |   1 -
>  arch/arm64/boot/dts/exynos/exynos7-espresso.dts    |   2 +
>  arch/mips/configs/pistachio_defconfig              |   1 -
>  drivers/mmc/host/Kconfig                           |  11 +-
>  drivers/mmc/host/dw_mmc-pltfm.c                    |   2 +
>  drivers/mmc/host/dw_mmc.c                          | 277 +++++++++++++++++----
>  include/linux/mmc/dw_mmc.h                         |  28 ++-
>  36 files changed, 338 insertions(+), 72 deletions(-)
> 

Re: [RFC PATCH v3 0/5]

[Shawn Lin]

On 2015/8/6 7:45, Krzysztof Kozlowski wrote:
> On 05.08.2015 17:16, Shawn Lin wrote:
>> Synopsys DesignWare mobile storage host controller supports three
>> types of transfer mode: pio, internal dma and external dma. However,
>> dw_mmc can only supports pio and internal dma now. Thus some platforms
>> using dw-mshc integrated with generic dma can't work in dma mode. So we
>> submit this patch to achieve it.
>>
>> And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
>> (commit:f95f3850) for the first version of dw_mmc and never be touched from
>> then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
>> we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
>> time. Nowadays, device-tree helps us to support a variety of boards with one
>> kernel. That's why we need to remove it and decide the transfer mode at runtime.
>>
>> This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
>> to make the running.
>>
>> Patch does the following things:
>> - remove CONFIG_MMC_DW_IDMAC config option
>> - add bindings for idmac and edmac used by synopsys-dw-mshc
>>    at runtime
>> - add edmac support for synopsys-dw-mshc
>>
>> Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc
>>
>>
>> Changes in v3:
>> - choose transfer mode at runtime
>> - remove all CONFIG_MMC_DW_IDMAC config option
>> - add supports-idmac property for some platforms
>>
>> Changes in v2:
>> - Fix typo of dev_info msg
>> - remove unused dmach from declaration of dw_mci_dma_slave
>>
>> Shawn Lin (5):
>>    mmc: dw_mmc: Add external dma interface support
>>    Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
>>    arm: configs: remove CONFIG_MMC_DW_IDMAC
>>    mips: configs: remove CONFIG_MMC_DW_IDMAC
>>    ARM: dts: add supports-idmac property
> Please fix the title of cover letter.
>
> You CC-ed a lot of people. Probably the whole output of git_maintainers
> which is not necessary. This means that your patches did not reach some
> of the mailing lists because of too many recipients. I received your
> patchset but I can't find it on any of the lists I subscribe.
>
> Please CC only REAL maintainers, not committers.

Right, not the whole output of "cc" by patchman automatically should be 
involved
in the  iteration of this patch. I will omit them from this loop  in v4.

>
> Additionally if DTS changes do not have to be introduced atomically
> please split it per sub-architecture. Of course that applies only in
> case of bisectable patches. And the patchset should preserve
> bisectability and backward compatibility (mentioned earlier).

okay, it will be split for each sub-architecture.
Thanks, Krzysztof. It's helpful.
> Best regards,
> Krzysztof
>
>
>>   .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |  41 +++
>>   arch/arc/configs/axs101_defconfig                  |   1 -
>>   arch/arc/configs/axs103_defconfig                  |   1 -
>>   arch/arc/configs/axs103_smp_defconfig              |   1 -
>>   arch/arm/boot/dts/exynos3250-monk.dts              |   1 +
>>   arch/arm/boot/dts/exynos3250-rinato.dts            |   1 +
>>   arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   1 +
>>   arch/arm/boot/dts/exynos4412-origen.dts            |   1 +
>>   arch/arm/boot/dts/exynos4412-trats2.dts            |   1 +
>>   arch/arm/boot/dts/exynos4x12.dtsi                  |   1 +
>>   arch/arm/boot/dts/exynos5250-arndale.dts           |   2 +
>>   arch/arm/boot/dts/exynos5250-smdk5250.dts          |   2 +
>>   arch/arm/boot/dts/exynos5250-snow.dts              |   3 +
>>   arch/arm/boot/dts/exynos5250-spring.dts            |   2 +
>>   arch/arm/boot/dts/exynos5260-xyref5260.dts         |   2 +
>>   arch/arm/boot/dts/exynos5410-smdk5410.dts          |   2 +
>>   arch/arm/boot/dts/exynos5420-arndale-octa.dts      |   2 +
>>   arch/arm/boot/dts/exynos5420-peach-pit.dts         |   3 +
>>   arch/arm/boot/dts/exynos5420-smdk5420.dts          |   2 +
>>   arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi |   2 +
>>   arch/arm/boot/dts/exynos5800-peach-pi.dts          |   3 +
>>   arch/arm/boot/dts/hisi-x5hd2.dtsi                  |   2 +
>>   arch/arm/boot/dts/rk3288-evb.dtsi                  |   2 +
>>   arch/arm/boot/dts/rk3288-firefly.dtsi              |   3 +
>>   arch/arm/boot/dts/rk3288-popmetal.dts              |   2 +
>>   arch/arm/configs/exynos_defconfig                  |   1 -
>>   arch/arm/configs/hisi_defconfig                    |   1 -
>>   arch/arm/configs/lpc18xx_defconfig                 |   1 -
>>   arch/arm/configs/multi_v7_defconfig                |   1 -
>>   arch/arm/configs/zx_defconfig                      |   1 -
>>   arch/arm64/boot/dts/exynos/exynos7-espresso.dts    |   2 +
>>   arch/mips/configs/pistachio_defconfig              |   1 -
>>   drivers/mmc/host/Kconfig                           |  11 +-
>>   drivers/mmc/host/dw_mmc-pltfm.c                    |   2 +
>>   drivers/mmc/host/dw_mmc.c                          | 277 +++++++++++++++++----
>>   include/linux/mmc/dw_mmc.h                         |  28 ++-
>>   36 files changed, 338 insertions(+), 72 deletions(-)
>>
>
>
>


-- 
Shawn Lin

Re: [RFC PATCH v3 0/5]

[Jaehoon Chung]

Hi,

On 08/06/2015 09:45 AM, Shawn Lin wrote:
> On 2015/8/6 7:45, Krzysztof Kozlowski wrote:
>> On 05.08.2015 17:16, Shawn Lin wrote:
>>> Synopsys DesignWare mobile storage host controller supports three
>>> types of transfer mode: pio, internal dma and external dma. However,
>>> dw_mmc can only supports pio and internal dma now. Thus some platforms
>>> using dw-mshc integrated with generic dma can't work in dma mode. So we
>>> submit this patch to achieve it.
>>>
>>> And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton
>>> (commit:f95f3850) for the first version of dw_mmc and never be touched from
>>> then. At that time dt-bindings hadn't been introduced into dw_mmc yet means
>>> we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile
>>> time. Nowadays, device-tree helps us to support a variety of boards with one
>>> kernel. That's why we need to remove it and decide the transfer mode at runtime.
>>>
>>> This RFC patch needs lots of ACKs. I know it's hard, but it does need someone
>>> to make the running.
>>>
>>> Patch does the following things:
>>> - remove CONFIG_MMC_DW_IDMAC config option
>>> - add bindings for idmac and edmac used by synopsys-dw-mshc
>>>    at runtime
>>> - add edmac support for synopsys-dw-mshc
>>>
>>> Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc
>>>
>>>
>>> Changes in v3:
>>> - choose transfer mode at runtime
>>> - remove all CONFIG_MMC_DW_IDMAC config option
>>> - add supports-idmac property for some platforms
>>>
>>> Changes in v2:
>>> - Fix typo of dev_info msg
>>> - remove unused dmach from declaration of dw_mci_dma_slave
>>>
>>> Shawn Lin (5):
>>>    mmc: dw_mmc: Add external dma interface support
>>>    Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
>>>    arm: configs: remove CONFIG_MMC_DW_IDMAC
>>>    mips: configs: remove CONFIG_MMC_DW_IDMAC
>>>    ARM: dts: add supports-idmac property
>> Please fix the title of cover letter.
>>
>> You CC-ed a lot of people. Probably the whole output of git_maintainers
>> which is not necessary. This means that your patches did not reach some
>> of the mailing lists because of too many recipients. I received your
>> patchset but I can't find it on any of the lists I subscribe.
>>
>> Please CC only REAL maintainers, not committers.
> 
> Right, not the whole output of "cc" by patchman automatically should be involved
> in the  iteration of this patch. I will omit them from this loop  in v4.

As Krzysztof mentioned, I can't read these patchset at mailing list.
I will check these after resend..It's helpful to me for checking patches.

Best Regards,
Jaehoon Chung

> 
>>
>> Additionally if DTS changes do not have to be introduced atomically
>> please split it per sub-architecture. Of course that applies only in
>> case of bisectable patches. And the patchset should preserve
>> bisectability and backward compatibility (mentioned earlier).
> 
> okay, it will be split for each sub-architecture.
> Thanks, Krzysztof. It's helpful.
>> Best regards,
>> Krzysztof
>>
>>
>>>   .../devicetree/bindings/mmc/synopsys-dw-mshc.txt   |  41 +++
>>>   arch/arc/configs/axs101_defconfig                  |   1 -
>>>   arch/arc/configs/axs103_defconfig                  |   1 -
>>>   arch/arc/configs/axs103_smp_defconfig              |   1 -
>>>   arch/arm/boot/dts/exynos3250-monk.dts              |   1 +
>>>   arch/arm/boot/dts/exynos3250-rinato.dts            |   1 +
>>>   arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   1 +
>>>   arch/arm/boot/dts/exynos4412-origen.dts            |   1 +
>>>   arch/arm/boot/dts/exynos4412-trats2.dts            |   1 +
>>>   arch/arm/boot/dts/exynos4x12.dtsi                  |   1 +
>>>   arch/arm/boot/dts/exynos5250-arndale.dts           |   2 +
>>>   arch/arm/boot/dts/exynos5250-smdk5250.dts          |   2 +
>>>   arch/arm/boot/dts/exynos5250-snow.dts              |   3 +
>>>   arch/arm/boot/dts/exynos5250-spring.dts            |   2 +
>>>   arch/arm/boot/dts/exynos5260-xyref5260.dts         |   2 +
>>>   arch/arm/boot/dts/exynos5410-smdk5410.dts          |   2 +
>>>   arch/arm/boot/dts/exynos5420-arndale-octa.dts      |   2 +
>>>   arch/arm/boot/dts/exynos5420-peach-pit.dts         |   3 +
>>>   arch/arm/boot/dts/exynos5420-smdk5420.dts          |   2 +
>>>   arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi |   2 +
>>>   arch/arm/boot/dts/exynos5800-peach-pi.dts          |   3 +
>>>   arch/arm/boot/dts/hisi-x5hd2.dtsi                  |   2 +
>>>   arch/arm/boot/dts/rk3288-evb.dtsi                  |   2 +
>>>   arch/arm/boot/dts/rk3288-firefly.dtsi              |   3 +
>>>   arch/arm/boot/dts/rk3288-popmetal.dts              |   2 +
>>>   arch/arm/configs/exynos_defconfig                  |   1 -
>>>   arch/arm/configs/hisi_defconfig                    |   1 -
>>>   arch/arm/configs/lpc18xx_defconfig                 |   1 -
>>>   arch/arm/configs/multi_v7_defconfig                |   1 -
>>>   arch/arm/configs/zx_defconfig                      |   1 -
>>>   arch/arm64/boot/dts/exynos/exynos7-espresso.dts    |   2 +
>>>   arch/mips/configs/pistachio_defconfig              |   1 -
>>>   drivers/mmc/host/Kconfig                           |  11 +-
>>>   drivers/mmc/host/dw_mmc-pltfm.c                    |   2 +
>>>   drivers/mmc/host/dw_mmc.c                          | 277 +++++++++++++++++----
>>>   include/linux/mmc/dw_mmc.h                         |  28 ++-
>>>   36 files changed, 338 insertions(+), 72 deletions(-)
>>>
>>
>>
>>
> 
> 

Re: [RFC PATCH v3 2/5] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Doug Anderson]

Shawn,

On Wed, Aug 5, 2015 at 1:17 AM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> synopsys-dw-mshc supports three types of transfer mode. We add bindings
> and description for how to use them at runtime. Without idmac and edmac
> property, pio is the default transfer mode. Make sure that Idmac and emdac
> should not be used simultaneously.

Can't you just read the HCON register?

[17:16]: DMA_INTERFACE
 00: none
 01: DW_DMA
 10: GENERIC_DMA
 11: NON-DW-DMA

Re: [RFC PATCH v3 2/5] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Jaehoon Chung]

On 08/06/2015 11:16 AM, Doug Anderson wrote:
> Shawn,
> 
> On Wed, Aug 5, 2015 at 1:17 AM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>> synopsys-dw-mshc supports three types of transfer mode. We add bindings
>> and description for how to use them at runtime. Without idmac and edmac
>> property, pio is the default transfer mode. Make sure that Idmac and emdac
>> should not be used simultaneously.
> 
> Can't you just read the HCON register?
> 
> [17:16]: DMA_INTERFACE
>  00: none
>  01: DW_DMA
>  10: GENERIC_DMA
>  11: NON-DW-DMA

If read it and get the exactly information. I think we can use that information.

Best Regards,
Jaehoon Chung

> 

Re: [RFC PATCH v3 1/5] mmc: dw_mmc: Add external dma interface support

[Jaehoon Chung]

Hi, Shawn.

On 08/05/2015 05:17 PM, Shawn Lin wrote:
> DesignWare MMC Controller can supports two types of DMA
> mode: external dma and internal dma. We get a RK312x platform
> integrated dw_mmc and ARM pl330 dma controller. This patch add
> edmac ops to support these platforms. I've tested it on RK312x
> platform with edmac mode and RK3288 platform with idmac mode.

RK312X doesn't support the idamc? Just wondering...

> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> 
> ---
> 
> Changes in v3:
> - choose transfer mode at runtime
> - remove all CONFIG_MMC_DW_IDMAC config option
> - add supports-idmac property for some platforms
> 
> Changes in v2:
> - Fix typo of dev_info msg
> - remove unused dmach from declaration of dw_mci_dma_slave
> 
>  drivers/mmc/host/Kconfig        |  11 +-
>  drivers/mmc/host/dw_mmc-pltfm.c |   2 +
>  drivers/mmc/host/dw_mmc.c       | 277 +++++++++++++++++++++++++++++++++-------
>  include/linux/mmc/dw_mmc.h      |  28 +++-
>  4 files changed, 255 insertions(+), 63 deletions(-)
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 6a0f9c7..a86c0eb 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -607,15 +607,7 @@ config MMC_DW
>  	help
>  	  This selects support for the Synopsys DesignWare Mobile Storage IP
>  	  block, this provides host support for SD and MMC interfaces, in both
> -	  PIO and external DMA modes.
> -
> -config MMC_DW_IDMAC
> -	bool "Internal DMAC interface"
> -	depends on MMC_DW
> -	help
> -	  This selects support for the internal DMAC block within the Synopsys
> -	  Designware Mobile Storage IP block. This disables the external DMA
> -	  interface.
> +	  PIO, internal DMA mode and external DMA modes.
>  
>  config MMC_DW_PLTFM
>  	tristate "Synopsys Designware MCI Support as platform device"
> @@ -644,7 +636,6 @@ config MMC_DW_K3
>  	tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
>  	depends on MMC_DW
>  	select MMC_DW_PLTFM
> -	select MMC_DW_IDMAC
>  	help
>  	  This selects support for Hisilicon K3 SoC specific extensions to the
>  	  Synopsys DesignWare Memory Card Interface driver. Select this option
> diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
> index ec6dbcd..7e1d13b 100644
> --- a/drivers/mmc/host/dw_mmc-pltfm.c
> +++ b/drivers/mmc/host/dw_mmc-pltfm.c
> @@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
>  	host->pdata = pdev->dev.platform_data;
>  
>  	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	/* Get registers' physical base address */
> +	host->phy_regs = (void *)(regs->start);
>  	host->regs = devm_ioremap_resource(&pdev->dev, regs);
>  	if (IS_ERR(host->regs))
>  		return PTR_ERR(host->regs);
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 40e9d8e..9341879 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -56,7 +56,7 @@
>  #define DW_MCI_FREQ_MAX	200000000	/* unit: HZ */
>  #define DW_MCI_FREQ_MIN	400000		/* unit: HZ */
>  
> -#ifdef CONFIG_MMC_DW_IDMAC
> +
>  #define IDMAC_INT_CLR		(SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
>  				 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
>  				 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
> @@ -99,7 +99,6 @@ struct idmac_desc {
>  
>  	__le32		des3;	/* buffer 2 physical address */
>  };
> -#endif /* CONFIG_MMC_DW_IDMAC */
>  
>  static bool dw_mci_reset(struct dw_mci *host);
>  static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
> @@ -403,7 +402,6 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
>  		return DMA_FROM_DEVICE;
>  }
>  
> -#ifdef CONFIG_MMC_DW_IDMAC
>  static void dw_mci_dma_cleanup(struct dw_mci *host)
>  {
>  	struct mmc_data *data = host->data;
> @@ -441,8 +439,9 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
>  	mci_writel(host, BMOD, temp);
>  }
>  
> -static void dw_mci_idmac_complete_dma(struct dw_mci *host)
> +static void dw_mci_idmac_complete_dma(void *arg)
>  {
> +	struct dw_mci *host = arg;
>  	struct mmc_data *data = host->data;
>  
>  	dev_vdbg(host->dev, "DMA complete\n");
> @@ -527,7 +526,7 @@ static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
>  	wmb();
>  }
>  
> -static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
> +static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>  {
>  	u32 temp;
>  
> @@ -551,6 +550,8 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>  
>  	/* Start it running */
>  	mci_writel(host, PLDMND, 1);
> +
> +	return 0;

void -> int? What do you want to do at here?

>  }
>  
>  static int dw_mci_idmac_init(struct dw_mci *host)
> @@ -632,7 +633,142 @@ static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
>  	.complete = dw_mci_idmac_complete_dma,
>  	.cleanup = dw_mci_dma_cleanup,
>  };
> -#endif /* CONFIG_MMC_DW_IDMAC */
> +
> +static void dw_mci_edmac_cleanup(struct dw_mci *host)
> +{
> +	struct mmc_data *data = host->data;
> +
> +	if (data && (!data->host_cookie))
> +		dma_unmap_sg(host->dev, data->sg,
> +			     data->sg_len, dw_mci_get_dma_dir(data));
> +}
> +

Can it reuse the dw_mci_dma_cleanup()?

> +static void dw_mci_edmac_stop_dma(struct dw_mci *host)
> +{
> +	dmaengine_terminate_all(host->dms->ch);
> +}
> +
> +static void dw_mci_edmac_complete_dma(void *arg)
> +{
> +	struct dw_mci *host = arg;
> +	struct mmc_data *data = host->data;
> +
> +	dev_vdbg(host->dev, "DMA complete\n");
> +
> +	if (data && data->flags & MMC_DATA_READ)
> +		/* Invalidate cache after read */
> +		dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc), data->sg,
> +				    data->sg_len, DMA_FROM_DEVICE);
> +
> +	host->dma_ops->cleanup(host);
> +
> +	/*
> +	* If the card was removed, data will be NULL. No point in trying to
> +	* send the stop command or waiting for NBUSY in this case.
> +	*/
> +	if (data) {
> +		set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
> +		tasklet_schedule(&host->tasklet);
> +	}
> +}

Ditto.

we can reduce the code lines..

> +
> +static int dw_mci_edmac_start_dma(struct dw_mci *host,
> +					    unsigned int sg_len)
> +{
> +	struct dma_slave_config cfg;
> +	struct dma_async_tx_descriptor *desc = NULL;
> +	struct scatterlist *sgl = host->data->sg;
> +	const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
> +	u32 sg_elems = host->data->sg_len;

doesn't check whether data is present or not?

> +	u32 fifoth_val;
> +	u32 fifo_offset = host->fifo_reg - host->regs;
> +	int ret = 0;
> +
> +	/* Set external dma config: burst size, burst width */
> +	cfg.dst_addr = (dma_addr_t)(host->phy_regs + fifo_offset);
> +	cfg.src_addr = cfg.dst_addr;
> +	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +
> +	/* Match burst msize with external dma config */
> +	fifoth_val = mci_readl(host, FIFOTH);
> +	cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
> +	cfg.src_maxburst = cfg.dst_maxburst;
> +
> +	if (host->data->flags & MMC_DATA_WRITE)
> +		cfg.direction = DMA_MEM_TO_DEV;
> +	else /* MMC_DATA_READ */
> +		cfg.direction = DMA_DEV_TO_MEM;
> +
> +	ret = dmaengine_slave_config(host->dms->ch, &cfg);
> +	if (ret) {
> +		dev_err(host->dev, "Failed to config edmac.\n");
> +		return -EBUSY;
> +	}
> +
> +	desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
> +				       sg_len, cfg.direction,
> +				       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
> +	if (!desc) {
> +		dev_err(host->dev, "Can't prepare slave sg.\n");
> +		return -EBUSY;
> +	}
> +
> +	/* Set dw_mci_edmac_complete_dma as callback */
> +	desc->callback = dw_mci_edmac_complete_dma;
> +	desc->callback_param = (void *)host;
> +	dmaengine_submit(desc);
> +
> +	/* Flush cache before write */
> +	if (host->data->flags & MMC_DATA_WRITE)
> +		dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
> +				       sg_elems, DMA_TO_DEVICE);
> +
> +	dma_async_issue_pending(host->dms->ch);
> +
> +	return 0;
> +}
> +
> +static int dw_mci_edmac_init(struct dw_mci *host)
> +{
> +	/* Request external dma channel */
> +	host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
> +	if (!host->dms)
> +		return -ENOMEM;
> +
> +	host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
> +	if (!host->dms->ch) {
> +		dev_err(host->dev,
> +			"Failed to get external DMA channel %d\n",
> +			host->dms->ch->chan_id);
> +		kfree(host->dms);
> +		host->dms = NULL;
> +		return -ENXIO;
> +	}
> +
> +	return 0;
> +}
> +
> +static void dw_mci_edmac_exit(struct dw_mci *host)
> +{
> +	if (host->dms) {
> +		if (host->dms->ch) {
> +			dma_release_channel(host->dms->ch);
> +			host->dms->ch = NULL;
> +		}
> +		kfree(host->dms);
> +		host->dms = NULL;
> +	}
> +}
> +
> +static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
> +	.init = dw_mci_edmac_init,
> +	.exit = dw_mci_edmac_exit,
> +	.start = dw_mci_edmac_start_dma,
> +	.stop = dw_mci_edmac_stop_dma,
> +	.complete = dw_mci_edmac_complete_dma,
> +	.cleanup = dw_mci_edmac_cleanup,
> +};
>  
>  static int dw_mci_pre_dma_transfer(struct dw_mci *host,
>  				   struct mmc_data *data,
> @@ -712,7 +848,6 @@ static void dw_mci_post_req(struct mmc_host *mmc,
>  
>  static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
>  {
> -#ifdef CONFIG_MMC_DW_IDMAC
>  	unsigned int blksz = data->blksz;
>  	const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
>  	u32 fifo_width = 1 << host->data_shift;
> @@ -720,6 +855,9 @@ static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
>  	u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
>  	int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
>  
> +	if (host->trans_mode == TRANS_MODE_PIO)
> +		return;
> +

"trans_mode" refer to Heiko's comment.

Best Regards,
Jaehoon Chung

>  	tx_wmark = (host->fifo_depth) / 2;
>  	tx_wmark_invers = host->fifo_depth - tx_wmark;
>  
> @@ -748,7 +886,6 @@ static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
>  done:
>  	fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
>  	mci_writel(host, FIFOTH, fifoth_val);
> -#endif
>  }
>  
>  static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
> @@ -835,7 +972,11 @@ static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
>  	mci_writel(host, INTMASK, temp);
>  	spin_unlock_irqrestore(&host->irq_lock, irqflags);
>  
> -	host->dma_ops->start(host, sg_len);
> +	if (host->dma_ops->start(host, sg_len)) {
> +		/* We can't do DMA */
> +		dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
> +		return -ENODEV;
> +	}
>  
>  	return 0;
>  }
> @@ -2256,26 +2397,30 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
>  
>  	}
>  
> -#ifdef CONFIG_MMC_DW_IDMAC
> -	/* Handle DMA interrupts */
> -	if (host->dma_64bit_address == 1) {
> -		pending = mci_readl(host, IDSTS64);
> -		if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
> -			mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
> -							SDMMC_IDMAC_INT_RI);
> -			mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
> -			host->dma_ops->complete(host);
> -		}
> -	} else {
> -		pending = mci_readl(host, IDSTS);
> -		if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
> -			mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
> -							SDMMC_IDMAC_INT_RI);
> -			mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
> -			host->dma_ops->complete(host);
> +	if ((host->trans_mode == TRANS_MODE_IDMAC) && host->use_dma) {
> +		/* Handle DMA interrupts */
> +		if (host->dma_64bit_address == 1) {
> +			pending = mci_readl(host, IDSTS64);
> +			if (pending & (SDMMC_IDMAC_INT_TI |
> +				       SDMMC_IDMAC_INT_RI)) {
> +				mci_writel(host, IDSTS64,
> +					   SDMMC_IDMAC_INT_TI |
> +					   SDMMC_IDMAC_INT_RI);
> +				mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
> +				host->dma_ops->complete((void *)host);
> +			}
> +		} else {
> +			pending = mci_readl(host, IDSTS);
> +			if (pending & (SDMMC_IDMAC_INT_TI |
> +				       SDMMC_IDMAC_INT_RI)) {
> +				mci_writel(host, IDSTS,
> +					   SDMMC_IDMAC_INT_TI |
> +					   SDMMC_IDMAC_INT_RI);
> +				mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
> +				host->dma_ops->complete((void *)host);
> +			}
>  		}
>  	}
> -#endif
>  
>  	return IRQ_HANDLED;
>  }
> @@ -2391,19 +2536,29 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
>  		mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
>  	} else {
>  		/* Useful defaults if platform data is unset. */
> -#ifdef CONFIG_MMC_DW_IDMAC
> -		mmc->max_segs = host->ring_size;
> -		mmc->max_blk_size = 65536;
> -		mmc->max_seg_size = 0x1000;
> -		mmc->max_req_size = mmc->max_seg_size * host->ring_size;
> -		mmc->max_blk_count = mmc->max_req_size / 512;
> -#else
> -		mmc->max_segs = 64;
> -		mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
> -		mmc->max_blk_count = 512;
> -		mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
> -		mmc->max_seg_size = mmc->max_req_size;
> -#endif /* CONFIG_MMC_DW_IDMAC */
> +		if (host->trans_mode == TRANS_MODE_IDMAC && host->use_dma) {
> +			mmc->max_segs = host->ring_size;
> +			mmc->max_blk_size = 65536;
> +			mmc->max_seg_size = 0x1000;
> +			mmc->max_req_size = mmc->max_seg_size * host->ring_size;
> +			mmc->max_blk_count = mmc->max_req_size / 512;
> +		} else if (host->trans_mode == TRANS_MODE_EDMAC &&
> +			   host->use_dma) {
> +			mmc->max_segs = 64;
> +			mmc->max_blk_size = 65536;
> +			mmc->max_blk_count = 65535;
> +			mmc->max_req_size =
> +					mmc->max_blk_size * mmc->max_blk_count;
> +			mmc->max_seg_size = mmc->max_req_size;
> +		} else {
> +			/* TRANS_MODE_PIO */
> +			mmc->max_segs = 64;
> +			mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
> +			mmc->max_blk_count = 512;
> +			mmc->max_req_size =
> +					mmc->max_blk_size * mmc->max_blk_count;
> +			mmc->max_seg_size = mmc->max_req_size;
> +		}
>  	}
>  
>  	if (dw_mci_get_cd(mmc))
> @@ -2437,6 +2592,11 @@ static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
>  static void dw_mci_init_dma(struct dw_mci *host)
>  {
>  	int addr_config;
> +
> +	/* Check tansfer mode */
> +	if (host->trans_mode == TRANS_MODE_PIO)
> +		goto no_dma;
> +
>  	/* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
>  	addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
>  
> @@ -2462,10 +2622,14 @@ static void dw_mci_init_dma(struct dw_mci *host)
>  	}
>  
>  	/* Determine which DMA interface to use */
> -#ifdef CONFIG_MMC_DW_IDMAC
> -	host->dma_ops = &dw_mci_idmac_ops;
> -	dev_info(host->dev, "Using internal DMA controller.\n");
> -#endif
> +	if (host->trans_mode == TRANS_MODE_IDMAC) {
> +		host->dma_ops = &dw_mci_idmac_ops;
> +		dev_info(host->dev, "Using internal DMA controller.\n");
> +	} else {
> +		/* TRANS_MODE_EDMAC */
> +		host->dma_ops = &dw_mci_edmac_ops;
> +		dev_info(host->dev, "Using external DMA controller.\n");
> +	}
>  
>  	if (!host->dma_ops)
>  		goto no_dma;
> @@ -2570,10 +2734,9 @@ static bool dw_mci_reset(struct dw_mci *host)
>  		}
>  	}
>  
> -#if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
> -	/* It is also recommended that we reset and reprogram idmac */
> -	dw_mci_idmac_reset(host);
> -#endif
> +	if (host->trans_mode == TRANS_MODE_IDMAC)
> +		/* It is also recommended that we reset and reprogram idmac */
> +		dw_mci_idmac_reset(host);
>  
>  	ret = true;
>  
> @@ -2653,6 +2816,21 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
>  	if (of_find_property(np, "supports-highspeed", NULL))
>  		pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
>  
> +	if (of_find_property(np, "supports-idmac", NULL)) {
> +		host->trans_mode = TRANS_MODE_IDMAC;
> +		if (of_find_property(np, "supports-edmac", NULL)) {
> +			dev_err(dev, "can't configure idmac & edmac simultaneously\n");
> +			/* Force pio mode */
> +			host->trans_mode = TRANS_MODE_PIO;
> +		}
> +
> +	} else if (of_find_property(np, "supports-edmac", NULL)) {
> +		host->trans_mode = TRANS_MODE_EDMAC;
> +	} else {
> +		/* Default use pio */
> +		host->trans_mode = TRANS_MODE_PIO;
> +	}
> +
>  	return pdata;
>  }
>  
> @@ -2958,6 +3136,9 @@ EXPORT_SYMBOL(dw_mci_remove);
>   */
>  int dw_mci_suspend(struct dw_mci *host)
>  {
> +	if (host->use_dma && host->dma_ops->exit)
> +		host->dma_ops->exit(host);
> +
>  	return 0;
>  }
>  EXPORT_SYMBOL(dw_mci_suspend);
> diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
> index 5be9767..6c1c7ea 100644
> --- a/include/linux/mmc/dw_mmc.h
> +++ b/include/linux/mmc/dw_mmc.h
> @@ -16,6 +16,7 @@
>  
>  #include <linux/scatterlist.h>
>  #include <linux/mmc/core.h>
> +#include <linux/dmaengine.h>
>  
>  #define MAX_MCI_SLOTS	2
>  
> @@ -40,6 +41,17 @@ enum {
>  
>  struct mmc_data;
>  
> +enum {
> +	TRANS_MODE_PIO = 0,
> +	TRANS_MODE_IDMAC,
> +	TRANS_MODE_EDMAC
> +};
> +
> +struct dw_mci_dma_slave {
> +	struct dma_chan *ch;
> +	enum dma_transfer_direction direction;
> +};
> +
>  /**
>   * struct dw_mci - MMC controller state shared between all slots
>   * @lock: Spinlock protecting the queue and associated data.
> @@ -147,17 +159,23 @@ struct dw_mci {
>  
>  	/* DMA interface members*/
>  	int			use_dma;
> +	int			trans_mode;
>  	int			using_dma;
>  	int			dma_64bit_address;
>  
>  	dma_addr_t		sg_dma;
>  	void			*sg_cpu;
>  	const struct dw_mci_dma_ops	*dma_ops;
> -#ifdef CONFIG_MMC_DW_IDMAC
> +	/* For idmac */
>  	unsigned int		ring_size;
> -#else
> +
> +	/* For edmac */
> +	struct dw_mci_dma_slave *dms;
> +	/* Registers's physical base address */
> +	void                    *phy_regs;
> +
>  	struct dw_mci_dma_data	*dma_data;
> -#endif
> +
>  	u32			cmd_status;
>  	u32			data_status;
>  	u32			stop_cmdr;
> @@ -210,8 +228,8 @@ struct dw_mci {
>  struct dw_mci_dma_ops {
>  	/* DMA Ops */
>  	int (*init)(struct dw_mci *host);
> -	void (*start)(struct dw_mci *host, unsigned int sg_len);
> -	void (*complete)(struct dw_mci *host);
> +	int (*start)(struct dw_mci *host, unsigned int sg_len);
> +	void (*complete)(void *host);
>  	void (*stop)(struct dw_mci *host);
>  	void (*cleanup)(struct dw_mci *host);
>  	void (*exit)(struct dw_mci *host);
> 

Re: [RFC PATCH v3 2/5] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac

[Shawn Lin]

在 2015/8/6 10:20, Jaehoon Chung 写道:
> On 08/06/2015 11:16 AM, Doug Anderson wrote:
>> Shawn,
>>
>> On Wed, Aug 5, 2015 at 1:17 AM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>>> synopsys-dw-mshc supports three types of transfer mode. We add bindings
>>> and description for how to use them at runtime. Without idmac and edmac
>>> property, pio is the default transfer mode. Make sure that Idmac and emdac
>>> should not be used simultaneously.
>> Can't you just read the HCON register?
>>
>> [17:16]: DMA_INTERFACE
>>   00: none
>>   01: DW_DMA
>>   10: GENERIC_DMA
>>   11: NON-DW-DMA
> If read it and get the exactly information. I think we can use that information.

  It's helpful really, but the description is ambiguous. ：(
  So I make a big big mistake when I read it for the firest time .
  I was just wondering the "mismatch" value from HCON and my databook.

Here I get details from our ASIC team guy :

// Name:         DMA_INTERFACE
// Default:      None
// Values:       None (0), DW-DMA (1), Generic-DMA (2), NON-DW-DMA (3)
// Enabled:      INTERNAL_DMAC==0
//
// Configures the type for DMA interface. In addition to AMBA host 
interface,
//  the data FIFO can be accesses by the optional DMA interface. The DMA 
type
//  could be either DW-DMA, which provides hand shake signals to 
DW_ahb_dmac
//  controller, or a generic DMA interface which provides a simpler
//  request/acknowledgement protocol and dedicated DMA data-bus, or
//  no DMA interface.
`define DMA_INTERFACE 1

   if we use idmac, DMA_INTERFACE should be "0", and we get 2b'00 from 
HCON[17:16]
   if we use edmac, DMA_INTERFACE should be "1", "2" and we get 2b'01 ,2b'10
   from HCON[17:16] respectively .
   But if only support PIO mode,   DMA_INTERFACE should be "3", and we 
get 2b'11 from
   HCON[17:16].

   So, "none" means IDMAC, "DW_DMA"/"GENERIC_DMA" refer to two types of 
external dma and "NON-DW-DMA" means pio from databook . It's a little 
difficult to understand it.

  This makes my work easy!

  Thanks, Doug and Jeahoon.

> Best Regards,
> Jaehoon Chung
>
>
>
>


-- 
Shawn Lin

Re: [RFC PATCH v3 1/5] mmc: dw_mmc: Add external dma interface support

[Shawn Lin]

在 2015/8/6 10:27, Jaehoon Chung 写道:
> Hi, Shawn.
>
> On 08/05/2015 05:17 PM, Shawn Lin wrote:
>> DesignWare MMC Controller can supports two types of DMA
>> mode: external dma and internal dma. We get a RK312x platform
>> integrated dw_mmc and ARM pl330 dma controller. This patch add
>> edmac ops to support these platforms. I've tested it on RK312x
>> platform with edmac mode and RK3288 platform with idmac mode.
> RK312X doesn't support the idamc? Just wondering...

   It does. And we have lots of platforms cannot support idmac...

>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>>
>> ---
>>
>> Changes in v3:
>> - choose transfer mode at runtime
>> - remove all CONFIG_MMC_DW_IDMAC config option
>> - add supports-idmac property for some platforms
>>
>> Changes in v2:
>> - Fix typo of dev_info msg
>> - remove unused dmach from declaration of dw_mci_dma_slave
>>
>>   drivers/mmc/host/Kconfig        |  11 +-
>>   drivers/mmc/host/dw_mmc-pltfm.c |   2 +
>>   drivers/mmc/host/dw_mmc.c       | 277 +++++++++++++++++++++++++++++++++-------
>>   include/linux/mmc/dw_mmc.h      |  28 +++-
>>   4 files changed, 255 insertions(+), 63 deletions(-)
>>
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index 6a0f9c7..a86c0eb 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -607,15 +607,7 @@ config MMC_DW
>>   	help
>>   	  This selects support for the Synopsys DesignWare Mobile Storage IP
>>   	  block, this provides host support for SD and MMC interfaces, in both
>> -	  PIO and external DMA modes.
>> -
>> -config MMC_DW_IDMAC
>> -	bool "Internal DMAC interface"
>> -	depends on MMC_DW
>> -	help
>> -	  This selects support for the internal DMAC block within the Synopsys
>> -	  Designware Mobile Storage IP block. This disables the external DMA
>> -	  interface.
>> +	  PIO, internal DMA mode and external DMA modes.
>>   
>>   config MMC_DW_PLTFM
>>   	tristate "Synopsys Designware MCI Support as platform device"
>> @@ -644,7 +636,6 @@ config MMC_DW_K3
>>   	tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
>>   	depends on MMC_DW
>>   	select MMC_DW_PLTFM
>> -	select MMC_DW_IDMAC
>>   	help
>>   	  This selects support for Hisilicon K3 SoC specific extensions to the
>>   	  Synopsys DesignWare Memory Card Interface driver. Select this option
>> diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
>> index ec6dbcd..7e1d13b 100644
>> --- a/drivers/mmc/host/dw_mmc-pltfm.c
>> +++ b/drivers/mmc/host/dw_mmc-pltfm.c
>> @@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
>>   	host->pdata = pdev->dev.platform_data;
>>   
>>   	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	/* Get registers' physical base address */
>> +	host->phy_regs = (void *)(regs->start);
>>   	host->regs = devm_ioremap_resource(&pdev->dev, regs);
>>   	if (IS_ERR(host->regs))
>>   		return PTR_ERR(host->regs);
>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>> index 40e9d8e..9341879 100644
>> --- a/drivers/mmc/host/dw_mmc.c
>> +++ b/drivers/mmc/host/dw_mmc.c
>> @@ -56,7 +56,7 @@
>>   #define DW_MCI_FREQ_MAX	200000000	/* unit: HZ */
>>   #define DW_MCI_FREQ_MIN	400000		/* unit: HZ */
>>   
>> -#ifdef CONFIG_MMC_DW_IDMAC
>> +
>>   #define IDMAC_INT_CLR		(SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
>>   				 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
>>   				 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
>> @@ -99,7 +99,6 @@ struct idmac_desc {
>>   
>>   	__le32		des3;	/* buffer 2 physical address */
>>   };
>> -#endif /* CONFIG_MMC_DW_IDMAC */
>>   
>>   static bool dw_mci_reset(struct dw_mci *host);
>>   static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
>> @@ -403,7 +402,6 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
>>   		return DMA_FROM_DEVICE;
>>   }
>>   
>> -#ifdef CONFIG_MMC_DW_IDMAC
>>   static void dw_mci_dma_cleanup(struct dw_mci *host)
>>   {
>>   	struct mmc_data *data = host->data;
>> @@ -441,8 +439,9 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
>>   	mci_writel(host, BMOD, temp);
>>   }
>>   
>> -static void dw_mci_idmac_complete_dma(struct dw_mci *host)
>> +static void dw_mci_idmac_complete_dma(void *arg)
>>   {
>> +	struct dw_mci *host = arg;
>>   	struct mmc_data *data = host->data;
>>   
>>   	dev_vdbg(host->dev, "DMA complete\n");
>> @@ -527,7 +526,7 @@ static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
>>   	wmb();
>>   }
>>   
>> -static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>> +static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>>   {
>>   	u32 temp;
>>   
>> @@ -551,6 +550,8 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
>>   
>>   	/* Start it running */
>>   	mci_writel(host, PLDMND, 1);
>> +
>> +	return 0;
> void -> int? What do you want to do at here?
    I just want to check wether  dma_ops->start () fail or not. If it 
does fail, use pio to submit this mrq.
    It's meaningless  for idma but edmac may not be started for some reasons
    (dmaengine_slave_config or dmaengine_prep_slave_sg may return 
unsuccessful state)

>
>>   }
>>   
>>   static int dw_mci_idmac_init(struct dw_mci *host)
>> @@ -632,7 +633,142 @@ static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
>>   	.complete = dw_mci_idmac_complete_dma,
>>   	.cleanup = dw_mci_dma_cleanup,
>>   };
>> -#endif /* CONFIG_MMC_DW_IDMAC */
>> +
>> +static void dw_mci_edmac_cleanup(struct dw_mci *host)
>> +{
>> +	struct mmc_data *data = host->data;
>> +
>> +	if (data && (!data->host_cookie))
>> +		dma_unmap_sg(host->dev, data->sg,
>> +			     data->sg_len, dw_mci_get_dma_dir(data));
>> +}
>> +
> Can it reuse the dw_mci_dma_cleanup()?
   yes, I will.

>> +static void dw_mci_edmac_stop_dma(struct dw_mci *host)
>> +{
>> +	dmaengine_terminate_all(host->dms->ch);
>> +}
>> +
>> +static void dw_mci_edmac_complete_dma(void *arg)
>> +{
>> +	struct dw_mci *host = arg;
>> +	struct mmc_data *data = host->data;
>> +
>> +	dev_vdbg(host->dev, "DMA complete\n");
>> +
>> +	if (data && data->flags & MMC_DATA_READ)
>> +		/* Invalidate cache after read */
>> +		dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc), data->sg,
>> +				    data->sg_len, DMA_FROM_DEVICE);
>> +
>> +	host->dma_ops->cleanup(host);
>> +
>> +	/*
>> +	* If the card was removed, data will be NULL. No point in trying to
>> +	* send the stop command or waiting for NBUSY in this case.
>> +	*/
>> +	if (data) {
>> +		set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
>> +		tasklet_schedule(&host->tasklet);
>> +	}
>> +}
> Ditto.
>
> we can reduce the code lines..
   yes,  I will rename dw_mci_idmac_complete_dma to 
dw_mci_dmac_complete_dma,
   and reuse it for idmac & edmac. BTW,  dma_sync_sg_for_cpu will be 
added for edmac only.
   Fine? ：)
>
>> +
>> +static int dw_mci_edmac_start_dma(struct dw_mci *host,
>> +					    unsigned int sg_len)
>> +{
>> +	struct dma_slave_config cfg;
>> +	struct dma_async_tx_descriptor *desc = NULL;
>> +	struct scatterlist *sgl = host->data->sg;
>> +	const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
>> +	u32 sg_elems = host->data->sg_len;
> doesn't check whether data is present or not?
   I don't think so.
   dw_mci_submit_data will check it. It doesn't care dma mode, and will 
call dma_ops->start() only.
  That means idmac_start and edmac_start are safe.
>> +	u32 fifoth_val;
>> +	u32 fifo_offset = host->fifo_reg - host->regs;
>> +	int ret = 0;
>> +
>> +	/* Set external dma config: burst size, burst width */
>> +	cfg.dst_addr = (dma_addr_t)(host->phy_regs + fifo_offset);
>> +	cfg.src_addr = cfg.dst_addr;
>> +	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
>> +	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
>> +
>> +	/* Match burst msize with external dma config */
>> +	fifoth_val = mci_readl(host, FIFOTH);
>> +	cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
>> +	cfg.src_maxburst = cfg.dst_maxburst;
>> +
>> +	if (host->data->flags & MMC_DATA_WRITE)
>> +		cfg.direction = DMA_MEM_TO_DEV;
>> +	else /* MMC_DATA_READ */
>> +		cfg.direction = DMA_DEV_TO_MEM;
>> +
>> +	ret = dmaengine_slave_config(host->dms->ch, &cfg);
>> +	if (ret) {
>> +		dev_err(host->dev, "Failed to config edmac.\n");
>> +		return -EBUSY;
>> +	}
>> +
>> +	desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
>> +				       sg_len, cfg.direction,
>> +				       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
>> +	if (!desc) {
>> +		dev_err(host->dev, "Can't prepare slave sg.\n");
>> +		return -EBUSY;
>> +	}
>> +
>> +	/* Set dw_mci_edmac_complete_dma as callback */
>> +	desc->callback = dw_mci_edmac_complete_dma;
>> +	desc->callback_param = (void *)host;
>> +	dmaengine_submit(desc);
>> +
>> +	/* Flush cache before write */
>> +	if (host->data->flags & MMC_DATA_WRITE)
>> +		dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
>> +				       sg_elems, DMA_TO_DEVICE);
>> +
>> +	dma_async_issue_pending(host->dms->ch);
>> +
>> +	return 0;
>> +}
>> +
>> +static int dw_mci_edmac_init(struct dw_mci *host)
>> +{
>> +	/* Request external dma channel */
>> +	host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
>> +	if (!host->dms)
>> +		return -ENOMEM;
>> +
>> +	host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
>> +	if (!host->dms->ch) {
>> +		dev_err(host->dev,
>> +			"Failed to get external DMA channel %d\n",
>> +			host->dms->ch->chan_id);
>> +		kfree(host->dms);
>> +		host->dms = NULL;
>> +		return -ENXIO;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static void dw_mci_edmac_exit(struct dw_mci *host)
>> +{
>> +	if (host->dms) {
>> +		if (host->dms->ch) {
>> +			dma_release_channel(host->dms->ch);
>> +			host->dms->ch = NULL;
>> +		}
>> +		kfree(host->dms);
>> +		host->dms = NULL;
>> +	}
>> +}
>> +
>> +static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
>> +	.init = dw_mci_edmac_init,
>> +	.exit = dw_mci_edmac_exit,
>> +	.start = dw_mci_edmac_start_dma,
>> +	.stop = dw_mci_edmac_stop_dma,
>> +	.complete = dw_mci_edmac_complete_dma,
>> +	.cleanup = dw_mci_edmac_cleanup,
>> +};
>>   
>>   static int dw_mci_pre_dma_transfer(struct dw_mci *host,
>>   				   struct mmc_data *data,
>> @@ -712,7 +848,6 @@ static void dw_mci_post_req(struct mmc_host *mmc,
>>   
>>   static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
>>   {
>> -#ifdef CONFIG_MMC_DW_IDMAC
>>   	unsigned int blksz = data->blksz;
>>   	const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
>>   	u32 fifo_width = 1 << host->data_shift;
>> @@ -720,6 +855,9 @@ static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
>>   	u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
>>   	int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
>>   
>> +	if (host->trans_mode == TRANS_MODE_PIO)
>> +		return;
>> +
> "trans_mode" refer to Heiko's comment.

  Got it.
>
> Best Regards,
> Jaehoon Chung
>
>>   	tx_wmark = (host->fifo_depth) / 2;
>>   	tx_wmark_invers = host->fifo_depth - tx_wmark;
>>   
>> @@ -748,7 +886,6 @@ static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
>>   done:
>>   	fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
>>   	mci_writel(host, FIFOTH, fifoth_val);
>> -#endif
>>   }
>>   
>>   static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
>> @@ -835,7 +972,11 @@ static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
>>   	mci_writel(host, INTMASK, temp);
>>   	spin_unlock_irqrestore(&host->irq_lock, irqflags);
>>   
>> -	host->dma_ops->start(host, sg_len);
>> +	if (host->dma_ops->start(host, sg_len)) {
>> +		/* We can't do DMA */
>> +		dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
>> +		return -ENODEV;
>> +	}
>>   
>>   	return 0;
>>   }
>> @@ -2256,26 +2397,30 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
>>   
>>   	}
>>   
>> -#ifdef CONFIG_MMC_DW_IDMAC
>> -	/* Handle DMA interrupts */
>> -	if (host->dma_64bit_address == 1) {
>> -		pending = mci_readl(host, IDSTS64);
>> -		if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
>> -			mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
>> -							SDMMC_IDMAC_INT_RI);
>> -			mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
>> -			host->dma_ops->complete(host);
>> -		}
>> -	} else {
>> -		pending = mci_readl(host, IDSTS);
>> -		if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
>> -			mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
>> -							SDMMC_IDMAC_INT_RI);
>> -			mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
>> -			host->dma_ops->complete(host);
>> +	if ((host->trans_mode == TRANS_MODE_IDMAC) && host->use_dma) {
>> +		/* Handle DMA interrupts */
>> +		if (host->dma_64bit_address == 1) {
>> +			pending = mci_readl(host, IDSTS64);
>> +			if (pending & (SDMMC_IDMAC_INT_TI |
>> +				       SDMMC_IDMAC_INT_RI)) {
>> +				mci_writel(host, IDSTS64,
>> +					   SDMMC_IDMAC_INT_TI |
>> +					   SDMMC_IDMAC_INT_RI);
>> +				mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
>> +				host->dma_ops->complete((void *)host);
>> +			}
>> +		} else {
>> +			pending = mci_readl(host, IDSTS);
>> +			if (pending & (SDMMC_IDMAC_INT_TI |
>> +				       SDMMC_IDMAC_INT_RI)) {
>> +				mci_writel(host, IDSTS,
>> +					   SDMMC_IDMAC_INT_TI |
>> +					   SDMMC_IDMAC_INT_RI);
>> +				mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
>> +				host->dma_ops->complete((void *)host);
>> +			}
>>   		}
>>   	}
>> -#endif
>>   
>>   	return IRQ_HANDLED;
>>   }
>> @@ -2391,19 +2536,29 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
>>   		mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
>>   	} else {
>>   		/* Useful defaults if platform data is unset. */
>> -#ifdef CONFIG_MMC_DW_IDMAC
>> -		mmc->max_segs = host->ring_size;
>> -		mmc->max_blk_size = 65536;
>> -		mmc->max_seg_size = 0x1000;
>> -		mmc->max_req_size = mmc->max_seg_size * host->ring_size;
>> -		mmc->max_blk_count = mmc->max_req_size / 512;
>> -#else
>> -		mmc->max_segs = 64;
>> -		mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
>> -		mmc->max_blk_count = 512;
>> -		mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
>> -		mmc->max_seg_size = mmc->max_req_size;
>> -#endif /* CONFIG_MMC_DW_IDMAC */
>> +		if (host->trans_mode == TRANS_MODE_IDMAC && host->use_dma) {
>> +			mmc->max_segs = host->ring_size;
>> +			mmc->max_blk_size = 65536;
>> +			mmc->max_seg_size = 0x1000;
>> +			mmc->max_req_size = mmc->max_seg_size * host->ring_size;
>> +			mmc->max_blk_count = mmc->max_req_size / 512;
>> +		} else if (host->trans_mode == TRANS_MODE_EDMAC &&
>> +			   host->use_dma) {
>> +			mmc->max_segs = 64;
>> +			mmc->max_blk_size = 65536;
>> +			mmc->max_blk_count = 65535;
>> +			mmc->max_req_size =
>> +					mmc->max_blk_size * mmc->max_blk_count;
>> +			mmc->max_seg_size = mmc->max_req_size;
>> +		} else {
>> +			/* TRANS_MODE_PIO */
>> +			mmc->max_segs = 64;
>> +			mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
>> +			mmc->max_blk_count = 512;
>> +			mmc->max_req_size =
>> +					mmc->max_blk_size * mmc->max_blk_count;
>> +			mmc->max_seg_size = mmc->max_req_size;
>> +		}
>>   	}
>>   
>>   	if (dw_mci_get_cd(mmc))
>> @@ -2437,6 +2592,11 @@ static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
>>   static void dw_mci_init_dma(struct dw_mci *host)
>>   {
>>   	int addr_config;
>> +
>> +	/* Check tansfer mode */
>> +	if (host->trans_mode == TRANS_MODE_PIO)
>> +		goto no_dma;
>> +
>>   	/* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
>>   	addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
>>   
>> @@ -2462,10 +2622,14 @@ static void dw_mci_init_dma(struct dw_mci *host)
>>   	}
>>   
>>   	/* Determine which DMA interface to use */
>> -#ifdef CONFIG_MMC_DW_IDMAC
>> -	host->dma_ops = &dw_mci_idmac_ops;
>> -	dev_info(host->dev, "Using internal DMA controller.\n");
>> -#endif
>> +	if (host->trans_mode == TRANS_MODE_IDMAC) {
>> +		host->dma_ops = &dw_mci_idmac_ops;
>> +		dev_info(host->dev, "Using internal DMA controller.\n");
>> +	} else {
>> +		/* TRANS_MODE_EDMAC */
>> +		host->dma_ops = &dw_mci_edmac_ops;
>> +		dev_info(host->dev, "Using external DMA controller.\n");
>> +	}
>>   
>>   	if (!host->dma_ops)
>>   		goto no_dma;
>> @@ -2570,10 +2734,9 @@ static bool dw_mci_reset(struct dw_mci *host)
>>   		}
>>   	}
>>   
>> -#if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
>> -	/* It is also recommended that we reset and reprogram idmac */
>> -	dw_mci_idmac_reset(host);
>> -#endif
>> +	if (host->trans_mode == TRANS_MODE_IDMAC)
>> +		/* It is also recommended that we reset and reprogram idmac */
>> +		dw_mci_idmac_reset(host);
>>   
>>   	ret = true;
>>   
>> @@ -2653,6 +2816,21 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
>>   	if (of_find_property(np, "supports-highspeed", NULL))
>>   		pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
>>   
>> +	if (of_find_property(np, "supports-idmac", NULL)) {
>> +		host->trans_mode = TRANS_MODE_IDMAC;
>> +		if (of_find_property(np, "supports-edmac", NULL)) {
>> +			dev_err(dev, "can't configure idmac & edmac simultaneously\n");
>> +			/* Force pio mode */
>> +			host->trans_mode = TRANS_MODE_PIO;
>> +		}
>> +
>> +	} else if (of_find_property(np, "supports-edmac", NULL)) {
>> +		host->trans_mode = TRANS_MODE_EDMAC;
>> +	} else {
>> +		/* Default use pio */
>> +		host->trans_mode = TRANS_MODE_PIO;
>> +	}
>> +
>>   	return pdata;
>>   }
>>   
>> @@ -2958,6 +3136,9 @@ EXPORT_SYMBOL(dw_mci_remove);
>>    */
>>   int dw_mci_suspend(struct dw_mci *host)
>>   {
>> +	if (host->use_dma && host->dma_ops->exit)
>> +		host->dma_ops->exit(host);
>> +
>>   	return 0;
>>   }
>>   EXPORT_SYMBOL(dw_mci_suspend);
>> diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
>> index 5be9767..6c1c7ea 100644
>> --- a/include/linux/mmc/dw_mmc.h
>> +++ b/include/linux/mmc/dw_mmc.h
>> @@ -16,6 +16,7 @@
>>   
>>   #include <linux/scatterlist.h>
>>   #include <linux/mmc/core.h>
>> +#include <linux/dmaengine.h>
>>   
>>   #define MAX_MCI_SLOTS	2
>>   
>> @@ -40,6 +41,17 @@ enum {
>>   
>>   struct mmc_data;
>>   
>> +enum {
>> +	TRANS_MODE_PIO = 0,
>> +	TRANS_MODE_IDMAC,
>> +	TRANS_MODE_EDMAC
>> +};
>> +
>> +struct dw_mci_dma_slave {
>> +	struct dma_chan *ch;
>> +	enum dma_transfer_direction direction;
>> +};
>> +
>>   /**
>>    * struct dw_mci - MMC controller state shared between all slots
>>    * @lock: Spinlock protecting the queue and associated data.
>> @@ -147,17 +159,23 @@ struct dw_mci {
>>   
>>   	/* DMA interface members*/
>>   	int			use_dma;
>> +	int			trans_mode;
>>   	int			using_dma;
>>   	int			dma_64bit_address;
>>   
>>   	dma_addr_t		sg_dma;
>>   	void			*sg_cpu;
>>   	const struct dw_mci_dma_ops	*dma_ops;
>> -#ifdef CONFIG_MMC_DW_IDMAC
>> +	/* For idmac */
>>   	unsigned int		ring_size;
>> -#else
>> +
>> +	/* For edmac */
>> +	struct dw_mci_dma_slave *dms;
>> +	/* Registers's physical base address */
>> +	void                    *phy_regs;
>> +
>>   	struct dw_mci_dma_data	*dma_data;
>> -#endif
>> +
>>   	u32			cmd_status;
>>   	u32			data_status;
>>   	u32			stop_cmdr;
>> @@ -210,8 +228,8 @@ struct dw_mci {
>>   struct dw_mci_dma_ops {
>>   	/* DMA Ops */
>>   	int (*init)(struct dw_mci *host);
>> -	void (*start)(struct dw_mci *host, unsigned int sg_len);
>> -	void (*complete)(struct dw_mci *host);
>> +	int (*start)(struct dw_mci *host, unsigned int sg_len);
>> +	void (*complete)(void *host);
>>   	void (*stop)(struct dw_mci *host);
>>   	void (*cleanup)(struct dw_mci *host);
>>   	void (*exit)(struct dw_mci *host);
>>
>
>
>


-- 
Shawn Lin