From: James Liao <jamesjj.liao@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Mike Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Heiko Stubner <heiko@sntech.de>
Cc: srv_heupstream@mediatek.com, Daniel Kurtz <djkurtz@chromium.org>,
Ricky Liang <jcliang@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
James Liao <jamesjj.liao@mediatek.com>
Subject: [PATCH v7 3/9] clk: mediatek: Add __initdata and __init for data and functions
Date: Mon, 10 Aug 2015 17:50:22 +0800 [thread overview]
Message-ID: <1439200228-318-4-git-send-email-jamesjj.liao@mediatek.com> (raw)
In-Reply-To: <1439200228-318-1-git-send-email-jamesjj.liao@mediatek.com>
Add __init for clock registration functions, and add __initdata for
mtk_gate_regs initial structures.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
drivers/clk/mediatek/clk-gate.c | 2 +-
drivers/clk/mediatek/clk-mt8173.c | 6 +++---
drivers/clk/mediatek/clk-mtk.c | 13 +++++++------
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 5702036..576bdb7 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -97,7 +97,7 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
.disable = mtk_cg_disable_inv,
};
-struct clk *mtk_clk_register_gate(
+struct clk * __init mtk_clk_register_gate(
const char *name,
const char *parent_name,
struct regmap *regmap,
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 13aa432..361fe32 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -586,7 +586,7 @@ static const struct mtk_composite top_muxes[] __initconst = {
MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
};
-static const struct mtk_gate_regs infra_cg_regs = {
+static const struct mtk_gate_regs infra_cg_regs __initconst = {
.set_ofs = 0x0040,
.clr_ofs = 0x0044,
.sta_ofs = 0x0048,
@@ -615,13 +615,13 @@ static const struct mtk_gate infra_clks[] __initconst = {
GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
};
-static const struct mtk_gate_regs peri0_cg_regs = {
+static const struct mtk_gate_regs peri0_cg_regs __initconst = {
.set_ofs = 0x0008,
.clr_ofs = 0x0010,
.sta_ofs = 0x0018,
};
-static const struct mtk_gate_regs peri1_cg_regs = {
+static const struct mtk_gate_regs peri1_cg_regs __initconst = {
.set_ofs = 0x000c,
.clr_ofs = 0x0014,
.sta_ofs = 0x001c,
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 18444ae..268b6ff 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -24,7 +24,7 @@
#include "clk-mtk.h"
#include "clk-gate.h"
-struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
+struct clk_onecell_data * __init mtk_alloc_clk_data(unsigned int clk_num)
{
int i;
struct clk_onecell_data *clk_data;
@@ -49,8 +49,8 @@ err_out:
return NULL;
}
-void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
- struct clk_onecell_data *clk_data)
+void __init mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
+ int num, struct clk_onecell_data *clk_data)
{
int i;
struct clk *clk;
@@ -72,7 +72,8 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
}
}
-int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
+int __init mtk_clk_register_gates(struct device_node *node,
+ const struct mtk_gate *clks,
int num, struct clk_onecell_data *clk_data)
{
int i;
@@ -111,7 +112,7 @@ int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks
return 0;
}
-struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
+struct clk * __init mtk_clk_register_composite(const struct mtk_composite *mc,
void __iomem *base, spinlock_t *lock)
{
struct clk *clk;
@@ -196,7 +197,7 @@ err_out:
return ERR_PTR(ret);
}
-void mtk_clk_register_composites(const struct mtk_composite *mcs,
+void __init mtk_clk_register_composites(const struct mtk_composite *mcs,
int num, void __iomem *base, spinlock_t *lock,
struct clk_onecell_data *clk_data)
{
--
1.8.1.1.dirty
next prev parent reply other threads:[~2015-08-10 9:50 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-10 9:50 [PATCH v7 0/9] Fixes and new clocks support for Mediatek MT8173 James Liao
[not found] ` <1439200228-318-1-git-send-email-jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2015-08-10 9:50 ` [PATCH v7 1/9] clk: mediatek: Removed unused dpi_ck clock from MT8173 James Liao
2015-08-10 9:50 ` [PATCH v7 2/9] clk: mediatek: Remove unused code " James Liao
2015-08-10 9:50 ` James Liao [this message]
2015-08-10 9:50 ` [PATCH v7 4/9] clk: mediatek: Add fixed clocks support for Mediatek SoC James Liao
2015-08-10 9:50 ` [PATCH v7 5/9] clk: mediatek: Fix rate and dependency of MT8173 clocks James Liao
2015-08-10 9:50 ` [PATCH v7 6/9] dt-bindings: ARM: Mediatek: Document devicetree bindings for clock controllers James Liao
2015-08-10 9:50 ` [PATCH v7 7/9] clk: mediatek: Add subsystem clocks of MT8173 James Liao
2015-08-10 9:50 ` [PATCH v7 8/9] clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS James Liao
2015-08-10 9:50 ` [PATCH v7 9/9] arm64: dts: mt8173: Add subsystem clock controller device nodes James Liao
2015-10-14 13:26 ` Matthias Brugger
2015-08-11 4:43 ` [PATCH v7 0/9] Fixes and new clocks support for Mediatek MT8173 Daniel Kurtz
[not found] ` <CAGS+omCya_0djzoVGhJchmaTtzo2z+JdnJHDjLipNMsZKV=MLQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-08-14 4:01 ` Daniel Kurtz
[not found] ` <CAGS+omAj=BZXYXChJwC2Heq+2KVEV2EoRrhiQhtXZRHGaZ9tEw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-08-19 14:50 ` Sascha Hauer
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