* [PATCH 0/2] ST PLL fixes for 4.3
@ 2015-08-19 8:48 Gabriel Fernandez
2015-08-19 8:48 ` [PATCH 1/2] dt-bindings: Fix tipo in st,clkgen-pll documentation Gabriel Fernandez
2015-08-19 8:48 ` [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Gabriel Fernandez
0 siblings, 2 replies; 6+ messages in thread
From: Gabriel Fernandez @ 2015-08-19 8:48 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Russell King, Michael Turquette, Stephen Boyd, Gabriel Fernandez,
Peter Griffin, Pankaj Dev, Olivier Bideau, Geert Uytterhoeven,
Fabian Frederick
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, linux-clk
Should be apply with
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")
to avoid broken compatibility.
Gabriel Fernandez (2):
dt-bindings: Fix tipo in st,clkgen-pll documentation
drivers: clk: st: Rename st_pll3200c32_407_c0_x into
st_pll3200c32_cx_x
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
drivers/clk/st/clkgen-fsyn.c | 8 ++++----
drivers/clk/st/clkgen-pll.c | 12 ++++++------
3 files changed, 12 insertions(+), 12 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/2] dt-bindings: Fix tipo in st,clkgen-pll documentation 2015-08-19 8:48 [PATCH 0/2] ST PLL fixes for 4.3 Gabriel Fernandez @ 2015-08-19 8:48 ` Gabriel Fernandez 2015-08-19 8:48 ` [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Gabriel Fernandez 1 sibling, 0 replies; 6+ messages in thread From: Gabriel Fernandez @ 2015-08-19 8:48 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Michael Turquette, Stephen Boyd, Gabriel Fernandez, Peter Griffin, Pankaj Dev, Olivier Bideau, Geert Uytterhoeven, Fabian Frederick Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, linux-clk replace "sst,plls-c32-cx_x" by "st,plls-c32-cx_x" Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index d8b168e..e2c6db0 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -21,8 +21,8 @@ Required properties: "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32" "st,stih407-plls-c32-a0", "st,clkgen-plls-c32" "st,stih407-plls-c32-a9", "st,clkgen-plls-c32" - "sst,plls-c32-cx_0", "st,clkgen-plls-c32" - "sst,plls-c32-cx_1", "st,clkgen-plls-c32" + "st,plls-c32-cx_0", "st,clkgen-plls-c32" + "st,plls-c32-cx_1", "st,clkgen-plls-c32" "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32" "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32" -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x 2015-08-19 8:48 [PATCH 0/2] ST PLL fixes for 4.3 Gabriel Fernandez 2015-08-19 8:48 ` [PATCH 1/2] dt-bindings: Fix tipo in st,clkgen-pll documentation Gabriel Fernandez @ 2015-08-19 8:48 ` Gabriel Fernandez 1 sibling, 0 replies; 6+ messages in thread From: Gabriel Fernandez @ 2015-08-19 8:48 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Michael Turquette, Stephen Boyd, Gabriel Fernandez, Peter Griffin, Pankaj Dev, Olivier Bideau, Geert Uytterhoeven, Fabian Frederick Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, linux-clk Use a generic name for this kind of PLL Correction in dts files are already done here: commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x") Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- drivers/clk/st/clkgen-fsyn.c | 8 ++++---- drivers/clk/st/clkgen-pll.c | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c index 83ccf14..576cd03 100644 --- a/drivers/clk/st/clkgen-fsyn.c +++ b/drivers/clk/st/clkgen-fsyn.c @@ -307,7 +307,7 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = { .get_rate = clk_fs660c32_dig_get_rate, }; -static const struct clkgen_quadfs_data st_fs660c32_C_407 = { +static const struct clkgen_quadfs_data st_fs660c32_C = { .nrst_present = true, .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0), CLKGEN_FIELD(0x2f0, 0x1, 1), @@ -350,7 +350,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = { .get_rate = clk_fs660c32_dig_get_rate, }; -static const struct clkgen_quadfs_data st_fs660c32_D_407 = { +static const struct clkgen_quadfs_data st_fs660c32_D = { .nrst_present = true, .nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0), CLKGEN_FIELD(0x2a0, 0x1, 1), @@ -1077,11 +1077,11 @@ static const struct of_device_id quadfs_of_match[] = { }, { .compatible = "st,stih407-quadfs660-C", - .data = &st_fs660c32_C_407 + .data = &st_fs660c32_C }, { .compatible = "st,stih407-quadfs660-D", - .data = &st_fs660c32_D_407 + .data = &st_fs660c32_D }, {} }; diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c index 47a38a9..b2a332c 100644 --- a/drivers/clk/st/clkgen-pll.c +++ b/drivers/clk/st/clkgen-pll.c @@ -193,7 +193,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = { .ops = &stm_pll3200c32_ops, }; -static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = { +static const struct clkgen_pll_data st_pll3200c32_cx_0 = { /* 407 C0 PLL0 */ .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8), .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24), @@ -205,7 +205,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = { .ops = &stm_pll3200c32_ops, }; -static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = { +static const struct clkgen_pll_data st_pll3200c32_cx_1 = { /* 407 C0 PLL1 */ .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8), .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24), @@ -624,12 +624,12 @@ static const struct of_device_id c32_pll_of_match[] = { .data = &st_pll3200c32_407_a0, }, { - .compatible = "st,stih407-plls-c32-c0_0", - .data = &st_pll3200c32_407_c0_0, + .compatible = "st,plls-c32-cx_0", + .data = &st_pll3200c32_cx_0, }, { - .compatible = "st,stih407-plls-c32-c0_1", - .data = &st_pll3200c32_407_c0_1, + .compatible = "st,plls-c32-cx_1", + .data = &st_pll3200c32_cx_1, }, { .compatible = "st,stih407-plls-c32-a9", -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2
@ 2015-09-16 7:42 Gabriel Fernandez
2015-09-16 7:42 ` [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Gabriel Fernandez
0 siblings, 1 reply; 6+ messages in thread
From: Gabriel Fernandez @ 2015-09-16 7:42 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Russell King, Michael Turquette, Stephen Boyd, Gabriel Fernandez,
Peter Griffin, Pankaj Dev, Olivier Bideau, Geert Uytterhoeven,
Fabian Frederick
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, linux-clk
This patch set fixes a kernel crash :
[ 2.433152] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.2.0-rc7-next-20150821 #134
[ 2.440713] Hardware name: STiH415/416 SoC with Flattened Device Tree
[ 2.447173] [<c00183ac>] (unwind_backtrace) from [<c0013cac>] (show_stack+0x10/0x14)
[ 2.454914] [<c0013cac>] (show_stack) from [<c0284f80>] (dump_stack+0x8c/0x9c)
[ 2.462145] [<c0284f80>] (dump_stack) from [<c0283a54>] (Ldiv0+0x8/0x10)
[ 2.468845] [<c0283a54>] (Ldiv0) from [<c0690e90>] (flexgen_round_rate+0x54/0x68)
[ 2.476327] [<c0690e90>] (flexgen_round_rate) from [<c06791f4>] (clk_calc_new_rates+0x1bc/0x22c)
[ 2.485109] [<c06791f4>] (clk_calc_new_rates) from [<c0679804>] (clk_core_set_rate_nolock+0x44/0xac)
[ 2.494235] [<c0679804>] (clk_core_set_rate_nolock) from [<c0679890>] (clk_set_rate+0x24/0x34)
[ 2.502845] [<c0679890>] (clk_set_rate) from [<c064f848>] (st_mmcss_cconfig+0x5c/0xfc)
[ 2.510763] [<c064f848>] (st_mmcss_cconfig) from [<c064fab0>] (sdhci_st_probe+0xec/0x1fc)
[ 2.518946] [<c064fab0>] (sdhci_st_probe) from [<c04334c8>] (platform_drv_probe+0x44/0xa4)
[ 2.527209] [<c04334c8>] (platform_drv_probe) from [<c0431bf4>] (driver_probe_device+0x204/0x2f0)
[ 2.536077] [<c0431bf4>] (driver_probe_device) from [<c0431d6c>] (__driver_attach+0x8c/0x90)
[ 2.544510] [<c0431d6c>] (__driver_attach) from [<c0430098>] (bus_for_each_dev+0x68/0x9c)
[ 2.552682] [<c0430098>] (bus_for_each_dev) from [<c0431320>] (bus_add_driver+0x19c/0x214)
[ 2.560941] [<c0431320>] (bus_add_driver) from [<c0432574>] (driver_register+0x78/0xf8)
[ 2.568941] [<c0432574>] (driver_register) from [<c000ab90>] (do_one_initcall+0x8c/0x1d4)
[ 2.577115] [<c000ab90>] (do_one_initcall) from [<c0b98ddc>] (kernel_init_freeable+0x158/0x1f8)
[ 2.585818] [<c0b98ddc>] (kernel_init_freeable) from [<c07b9350>] (kernel_init+0x8/0xe8)
[ 2.593905] [<c07b9350>] (kernel_init) from [<c00108a8>] (ret_from_fork+0x14/0x2c)
[ 2.601467] Division by zero in kernel.
This kernel crash is due to a broken compatibility with this commit:
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")
Gabriel Fernandez (2):
dt-bindings: Fix tipo in st,clkgen-pll documentation
drivers: clk: st: Rename st_pll3200c32_407_c0_x into
st_pll3200c32_cx_x
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
drivers/clk/st/clkgen-fsyn.c | 8 ++++----
drivers/clk/st/clkgen-pll.c | 12 ++++++------
3 files changed, 12 insertions(+), 12 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x 2015-09-16 7:42 [RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2 Gabriel Fernandez @ 2015-09-16 7:42 ` Gabriel Fernandez 2015-09-17 18:51 ` Stephen Boyd 0 siblings, 1 reply; 6+ messages in thread From: Gabriel Fernandez @ 2015-09-16 7:42 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Michael Turquette, Stephen Boyd, Gabriel Fernandez, Peter Griffin, Pankaj Dev, Olivier Bideau, Geert Uytterhoeven, Fabian Frederick Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, linux-clk Use a generic name for this kind of PLL Correction in dts files are already done here: commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x") Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- drivers/clk/st/clkgen-fsyn.c | 8 ++++---- drivers/clk/st/clkgen-pll.c | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c index 83ccf14..576cd03 100644 --- a/drivers/clk/st/clkgen-fsyn.c +++ b/drivers/clk/st/clkgen-fsyn.c @@ -307,7 +307,7 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = { .get_rate = clk_fs660c32_dig_get_rate, }; -static const struct clkgen_quadfs_data st_fs660c32_C_407 = { +static const struct clkgen_quadfs_data st_fs660c32_C = { .nrst_present = true, .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0), CLKGEN_FIELD(0x2f0, 0x1, 1), @@ -350,7 +350,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = { .get_rate = clk_fs660c32_dig_get_rate, }; -static const struct clkgen_quadfs_data st_fs660c32_D_407 = { +static const struct clkgen_quadfs_data st_fs660c32_D = { .nrst_present = true, .nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0), CLKGEN_FIELD(0x2a0, 0x1, 1), @@ -1077,11 +1077,11 @@ static const struct of_device_id quadfs_of_match[] = { }, { .compatible = "st,stih407-quadfs660-C", - .data = &st_fs660c32_C_407 + .data = &st_fs660c32_C }, { .compatible = "st,stih407-quadfs660-D", - .data = &st_fs660c32_D_407 + .data = &st_fs660c32_D }, {} }; diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c index 47a38a9..b2a332c 100644 --- a/drivers/clk/st/clkgen-pll.c +++ b/drivers/clk/st/clkgen-pll.c @@ -193,7 +193,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = { .ops = &stm_pll3200c32_ops, }; -static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = { +static const struct clkgen_pll_data st_pll3200c32_cx_0 = { /* 407 C0 PLL0 */ .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8), .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24), @@ -205,7 +205,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = { .ops = &stm_pll3200c32_ops, }; -static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = { +static const struct clkgen_pll_data st_pll3200c32_cx_1 = { /* 407 C0 PLL1 */ .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8), .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24), @@ -624,12 +624,12 @@ static const struct of_device_id c32_pll_of_match[] = { .data = &st_pll3200c32_407_a0, }, { - .compatible = "st,stih407-plls-c32-c0_0", - .data = &st_pll3200c32_407_c0_0, + .compatible = "st,plls-c32-cx_0", + .data = &st_pll3200c32_cx_0, }, { - .compatible = "st,stih407-plls-c32-c0_1", - .data = &st_pll3200c32_407_c0_1, + .compatible = "st,plls-c32-cx_1", + .data = &st_pll3200c32_cx_1, }, { .compatible = "st,stih407-plls-c32-a9", -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x 2015-09-16 7:42 ` [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Gabriel Fernandez @ 2015-09-17 18:51 ` Stephen Boyd 2015-09-18 7:31 ` Maxime Coquelin 0 siblings, 1 reply; 6+ messages in thread From: Stephen Boyd @ 2015-09-17 18:51 UTC (permalink / raw) To: Gabriel Fernandez Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Michael Turquette, Peter Griffin, Pankaj Dev, Olivier Bideau, Geert Uytterhoeven, Fabian Frederick, devicetree, linux-kernel, linux-arm-kernel, kernel, linux-clk On 09/16, Gabriel Fernandez wrote: > Use a generic name for this kind of PLL > > Correction in dts files are already done here: > commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x") > > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> > --- Applied to clk-fixes -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x 2015-09-17 18:51 ` Stephen Boyd @ 2015-09-18 7:31 ` Maxime Coquelin 0 siblings, 0 replies; 6+ messages in thread From: Maxime Coquelin @ 2015-09-18 7:31 UTC (permalink / raw) To: Stephen Boyd, Gabriel Fernandez Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Patrice Chotard, Russell King, Michael Turquette, Peter Griffin, Pankaj Dev, Olivier Bideau, Geert Uytterhoeven, Fabian Frederick, devicetree, linux-kernel, linux-arm-kernel, kernel, linux-clk On 09/17/2015 08:51 PM, Stephen Boyd wrote: > On 09/16, Gabriel Fernandez wrote: >> Use a generic name for this kind of PLL >> >> Correction in dts files are already done here: >> commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x") >> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> >> --- > Applied to clk-fixes > Thanks Stephen ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-09-18 7:31 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-08-19 8:48 [PATCH 0/2] ST PLL fixes for 4.3 Gabriel Fernandez 2015-08-19 8:48 ` [PATCH 1/2] dt-bindings: Fix tipo in st,clkgen-pll documentation Gabriel Fernandez 2015-08-19 8:48 ` [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Gabriel Fernandez -- strict thread matches above, loose matches on Subject: below -- 2015-09-16 7:42 [RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2 Gabriel Fernandez 2015-09-16 7:42 ` [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Gabriel Fernandez 2015-09-17 18:51 ` Stephen Boyd 2015-09-18 7:31 ` Maxime Coquelin
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).