From: Gabriel Fernandez <gabriel.fernandez@linaro.org>
To: Maxime Coquelin <maxime.coquelin@st.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Gabriel Fernandez <gabriel.fernandez@linaro.org>
Cc: Peter Griffin <peter.griffin@linaro.org>,
Pankaj Dev <pankaj.dev@st.com>,
Olivier Bideau <olivier.bideau@st.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Fabian Frederick <fabf@skynet.be>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Srinivas Kandagatla <srinivas.kandagatla@gmail.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kernel@stlinux.com,
linux-clk@vger.kernel.org
Subject: [PATCH v3 4/4] ARM: STi: DT: Add support for stih418 A9 pll
Date: Mon, 5 Oct 2015 10:06:33 +0200 [thread overview]
Message-ID: <1444032393-13433-5-git-send-email-gabriel.fernandez@linaro.org> (raw)
In-Reply-To: <1444032393-13433-1-git-send-email-gabriel.fernandez@linaro.org>
Add support for new PLL-type for stih418 A9-PLL.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
arch/arm/boot/dts/stih418-clock.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 148e177..ae6d997 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -44,7 +44,7 @@
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
+ compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
--
1.9.1
prev parent reply other threads:[~2015-10-05 8:06 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-05 8:06 [PATCH v3 0/4] ST PLL improvement Gabriel Fernandez
2015-10-05 8:06 ` [PATCH v3 1/4] drivers: clk: st: Support for enable/disable in Clockgen PLLs Gabriel Fernandez
2015-10-05 8:06 ` [PATCH v3 2/4] drivers: clk: st: PLL rate change implementation for DVFS Gabriel Fernandez
2015-10-06 18:06 ` Stephen Boyd
[not found] ` <20151006180617.GE12338-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2015-10-07 7:47 ` Gabriel Fernandez
[not found] ` <1444032393-13433-1-git-send-email-gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2015-10-05 8:06 ` [PATCH v3 3/4] drivers: clk: st: Correct the pll-type for A9 for stih418 Gabriel Fernandez
2015-10-05 8:06 ` Gabriel Fernandez [this message]
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