[PATCH 2/6] clk: sunxi: Add H3 clocks support

[PATCH 2/6] clk: sunxi: Add H3 clocks support

[Jens Kuske]

The H3 clock control unit is similar to the those of other sun8i family
members like the A23.

The AHB1 gates got split up into AHB1 and AHB2, with AHB2 clock source
being muxable between AHB1 and PLL6/2, but still sharing gate registers.
The documentation isn't totally clear about which devices belong to
AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner
kernel source code.

Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  7 ++++
 drivers/clk/sunxi/clk-sunxi.c                     | 46 ++++++++++++++++++++++-
 2 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 4fa11af..4eeb893 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -14,6 +14,8 @@ Required properties:
 	"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
 	"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
 	"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
+	"allwinner,sun8i-h3-pll6-clk" - for the PLL6 clock on H3
+	"allwinner,sun8i-h3-pll8-clk" - for the PLL8 clock on H3
 	"allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
 	"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
 	"allwinner,sun4i-a10-axi-clk" - for the AXI clock
@@ -28,8 +30,11 @@ Required properties:
 	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
 	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
 	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
+	"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
 	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
 	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
+	"allwinner,sun8i-h3-ahb1-gates-clk" - for the AHB1 gates on H3
+	"allwinner,sun8i-h3-ahb2-gates-clk" - for the AHB2 gates on H3
 	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
 	"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
 	"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
@@ -52,8 +57,10 @@ Required properties:
 	"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
 	"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
 	"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
+	"allwinner,sun8i-h3-apb1-gates-clk" - for the APB1 gates on H3
 	"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
 	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
+	"allwinner,sun8i-h3-apb2-gates-clk" - for the APB2 gates on H3
 	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
 	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
 	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 7e1e2bd..152a1f7 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -727,6 +727,12 @@ static const struct factors_data sun5i_a13_ahb_data __initconst = {
 	.getter = sun5i_a13_get_ahb_factors,
 };
 
+static const struct factors_data sun8i_h3_pll8_data __initconst = {
+	.enable = 31,
+	.table = &sun6i_a31_pll6_config,
+	.getter = sun6i_a31_get_pll6_factors,
+};
+
 static const struct factors_data sun4i_apb1_data __initconst = {
 	.mux = 24,
 	.muxmask = BIT(1) | BIT(0),
@@ -777,6 +783,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
 	.shift = 12,
 };
 
+static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
+	.shift = 0,
+};
+
 static void __init sunxi_mux_clk_setup(struct device_node *node,
 				       struct mux_data *data)
 {
@@ -892,7 +902,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
  * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
  */
 
-#define SUNXI_GATES_MAX_SIZE	64
+#define SUNXI_GATES_MAX_SIZE	160
 
 struct gates_data {
 	DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
@@ -926,6 +936,10 @@ static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
 	.mask = {0x25386742, 0x2505111},
 };
 
+static const struct gates_data sun8i_h3_ahb1_gates_data __initconst = {
+	.mask = {0x1fbc6760, 0x00701b39, 0x00000000, 0x00000000, 0x00000081},
+};
+
 static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
 	.mask = {0xF5F12B},
 };
@@ -938,6 +952,10 @@ static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
 	.mask = {0x9B7},
 };
 
+static const struct gates_data sun8i_h3_ahb2_gates_data __initconst = {
+	.mask = {0xe0020000},
+};
+
 static const struct gates_data sun4i_apb0_gates_data __initconst = {
 	.mask = {0x4EF},
 };
@@ -978,6 +996,10 @@ static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
 	.mask = {0x3021},
 };
 
+static const struct gates_data sun8i_h3_apb1_gates_data __initconst = {
+	.mask = {0x7123},
+};
+
 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
 	.mask = {0x3F000F},
 };
@@ -994,6 +1016,10 @@ static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
 	.mask = {0x1F0007},
 };
 
+static const struct gates_data sun8i_h3_apb2_gates_data __initconst = {
+	.mask = {0x1F0007},
+};
+
 static void __init sunxi_gates_clk_setup(struct device_node *node,
 					 struct gates_data *data)
 {
@@ -1106,6 +1132,16 @@ static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
 	}
 };
 
+static const struct divs_data sun8i_h3_pll6_divs_data __initconst = {
+	.factors = &sun6i_a31_pll6_data,
+	.ndivs = 3,
+	.div = {
+		{ .fixed = 2 }, /* normal output, pll6 */
+		{ .self = 1 }, /* base factor clock, pll6 x2 */
+		{ .fixed = 4 }, /* divided output, pll6 /2 */
+	}
+};
+
 /**
  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
  *
@@ -1252,6 +1288,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
 	{.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
 	{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
 	{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
+	{.compatible = "allwinner,sun8i-h3-pll8-clk", .data = &sun8i_h3_pll8_data,},
 	{}
 };
 
@@ -1269,6 +1306,7 @@ static const struct of_device_id clk_divs_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
 	{.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
 	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
+	{.compatible = "allwinner,sun8i-h3-pll6-clk", .data = &sun8i_h3_pll6_divs_data,},
 	{}
 };
 
@@ -1276,6 +1314,7 @@ static const struct of_device_id clk_divs_match[] __initconst = {
 static const struct of_device_id clk_mux_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
 	{.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
+	{.compatible = "allwinner,sun8i-h3-ahb2-clk", .data = &sun8i_h3_ahb2_mux_data,},
 	{}
 };
 
@@ -1288,9 +1327,11 @@ static const struct of_device_id clk_gates_match[] __initconst = {
 	{.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
 	{.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
 	{.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
+	{.compatible = "allwinner,sun8i-h3-ahb1-gates-clk", .data = &sun8i_h3_ahb1_gates_data,},
 	{.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
 	{.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
 	{.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
+	{.compatible = "allwinner,sun8i-h3-ahb2-gates-clk", .data = &sun8i_h3_ahb2_gates_data,},
 	{.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
 	{.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
 	{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
@@ -1302,9 +1343,11 @@ static const struct of_device_id clk_gates_match[] __initconst = {
 	{.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
 	{.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
 	{.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
+	{.compatible = "allwinner,sun8i-h3-apb1-gates-clk", .data = &sun8i_h3_apb1_gates_data,},
 	{.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
 	{.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
 	{.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
+	{.compatible = "allwinner,sun8i-h3-apb2-gates-clk", .data = &sun8i_h3_apb2_gates_data,},
 	{}
 };
 
@@ -1389,6 +1432,7 @@ static void __init sun6i_init_clocks(struct device_node *node)
 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
 CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
+CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);
 
 static void __init sun9i_init_clocks(struct device_node *node)
 {
-- 
2.3.7

Re: [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Chen-Yu Tsai]

Hi,

On Wed, May 6, 2015 at 5:31 PM, Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> The H3 clock control unit is similar to the those of other sun8i family
> members like the A23.
>
> The AHB1 gates got split up into AHB1 and AHB2, with AHB2 clock source
> being muxable between AHB1 and PLL6/2, but still sharing gate registers.
> The documentation isn't totally clear about which devices belong to
> AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner
> kernel source code.
>
> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  7 ++++
>  drivers/clk/sunxi/clk-sunxi.c                     | 46 ++++++++++++++++++++++-
>  2 files changed, 52 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 4fa11af..4eeb893 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -14,6 +14,8 @@ Required properties:
>         "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
>         "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
>         "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
> +       "allwinner,sun8i-h3-pll6-clk" - for the PLL6 clock on H3
> +       "allwinner,sun8i-h3-pll8-clk" - for the PLL8 clock on H3
>         "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
>         "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
>         "allwinner,sun4i-a10-axi-clk" - for the AXI clock
> @@ -28,8 +30,11 @@ Required properties:
>         "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
>         "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
>         "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
> +       "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
>         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>         "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
> +       "allwinner,sun8i-h3-ahb1-gates-clk" - for the AHB1 gates on H3
> +       "allwinner,sun8i-h3-ahb2-gates-clk" - for the AHB2 gates on H3
>         "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
>         "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
>         "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
> @@ -52,8 +57,10 @@ Required properties:
>         "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
>         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
>         "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
> +       "allwinner,sun8i-h3-apb1-gates-clk" - for the APB1 gates on H3
>         "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
>         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
> +       "allwinner,sun8i-h3-apb2-gates-clk" - for the APB2 gates on H3
>         "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
>         "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
>         "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 7e1e2bd..152a1f7 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -727,6 +727,12 @@ static const struct factors_data sun5i_a13_ahb_data __initconst = {
>         .getter = sun5i_a13_get_ahb_factors,
>  };
>
> +static const struct factors_data sun8i_h3_pll8_data __initconst = {
> +       .enable = 31,
> +       .table = &sun6i_a31_pll6_config,
> +       .getter = sun6i_a31_get_pll6_factors,
> +};
> +

If it's fully compatible with sun6i-a31-pll6, please just use it.

On second thought, maybe it's not working because of the .name field?
If so, you're missing one here.

>  static const struct factors_data sun4i_apb1_data __initconst = {
>         .mux = 24,
>         .muxmask = BIT(1) | BIT(0),
> @@ -777,6 +783,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
>         .shift = 12,
>  };
>
> +static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
> +       .shift = 0,
> +};
> +
>  static void __init sunxi_mux_clk_setup(struct device_node *node,
>                                        struct mux_data *data)
>  {
> @@ -892,7 +902,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
>   * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
>   */
>
> -#define SUNXI_GATES_MAX_SIZE   64
> +#define SUNXI_GATES_MAX_SIZE   160
>
>  struct gates_data {
>         DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> @@ -926,6 +936,10 @@ static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
>         .mask = {0x25386742, 0x2505111},
>  };
>
> +static const struct gates_data sun8i_h3_ahb1_gates_data __initconst = {
> +       .mask = {0x1fbc6760, 0x00701b39, 0x00000000, 0x00000000, 0x00000081},
> +};
> +

Wow, what's with the hardware design... :|

>  static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
>         .mask = {0xF5F12B},
>  };
> @@ -938,6 +952,10 @@ static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
>         .mask = {0x9B7},
>  };
>
> +static const struct gates_data sun8i_h3_ahb2_gates_data __initconst = {
> +       .mask = {0xe0020000},
> +};
> +
>  static const struct gates_data sun4i_apb0_gates_data __initconst = {
>         .mask = {0x4EF},
>  };
> @@ -978,6 +996,10 @@ static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
>         .mask = {0x3021},
>  };
>
> +static const struct gates_data sun8i_h3_apb1_gates_data __initconst = {
> +       .mask = {0x7123},
> +};
> +
>  static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
>         .mask = {0x3F000F},
>  };
> @@ -994,6 +1016,10 @@ static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
>         .mask = {0x1F0007},
>  };
>
> +static const struct gates_data sun8i_h3_apb2_gates_data __initconst = {
> +       .mask = {0x1F0007},
> +};
> +
>  static void __init sunxi_gates_clk_setup(struct device_node *node,
>                                          struct gates_data *data)
>  {
> @@ -1106,6 +1132,16 @@ static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
>         }
>  };
>
> +static const struct divs_data sun8i_h3_pll6_divs_data __initconst = {
> +       .factors = &sun6i_a31_pll6_data,
> +       .ndivs = 3,
> +       .div = {
> +               { .fixed = 2 }, /* normal output, pll6 */
> +               { .self = 1 }, /* base factor clock, pll6 x2 */
> +               { .fixed = 4 }, /* divided output, pll6 /2 */

Since you have the luxury of starting a new binding, maybe you could
put the ".self" clock first?

> +       }
> +};
> +
>  /**
>   * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
>   *
> @@ -1252,6 +1288,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
>         {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
>         {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
>         {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
> +       {.compatible = "allwinner,sun8i-h3-pll8-clk", .data = &sun8i_h3_pll8_data,},

Matching comment above, no need to add a new compatible for something that's
the same.

ChenYu

>         {}
>  };
>
> @@ -1269,6 +1306,7 @@ static const struct of_device_id clk_divs_match[] __initconst = {
>         {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
>         {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
>         {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
> +       {.compatible = "allwinner,sun8i-h3-pll6-clk", .data = &sun8i_h3_pll6_divs_data,},
>         {}
>  };
>
> @@ -1276,6 +1314,7 @@ static const struct of_device_id clk_divs_match[] __initconst = {
>  static const struct of_device_id clk_mux_match[] __initconst = {
>         {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
>         {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
> +       {.compatible = "allwinner,sun8i-h3-ahb2-clk", .data = &sun8i_h3_ahb2_mux_data,},
>         {}
>  };
>
> @@ -1288,9 +1327,11 @@ static const struct of_device_id clk_gates_match[] __initconst = {
>         {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
>         {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
>         {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
> +       {.compatible = "allwinner,sun8i-h3-ahb1-gates-clk", .data = &sun8i_h3_ahb1_gates_data,},
>         {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
>         {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
>         {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
> +       {.compatible = "allwinner,sun8i-h3-ahb2-gates-clk", .data = &sun8i_h3_ahb2_gates_data,},
>         {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
>         {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
>         {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
> @@ -1302,9 +1343,11 @@ static const struct of_device_id clk_gates_match[] __initconst = {
>         {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
>         {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
>         {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
> +       {.compatible = "allwinner,sun8i-h3-apb1-gates-clk", .data = &sun8i_h3_apb1_gates_data,},
>         {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
>         {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
>         {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
> +       {.compatible = "allwinner,sun8i-h3-apb2-gates-clk", .data = &sun8i_h3_apb2_gates_data,},
>         {}
>  };
>
> @@ -1389,6 +1432,7 @@ static void __init sun6i_init_clocks(struct device_node *node)
>  CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
>  CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
>  CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
> +CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);
>
>  static void __init sun9i_init_clocks(struct device_node *node)
>  {
> --
> 2.3.7
>

Re: [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Jens Kuske]

On 06/05/15 11:47, Chen-Yu Tsai wrote:
> Hi,
> 
> On Wed, May 6, 2015 at 5:31 PM, Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> The H3 clock control unit is similar to the those of other sun8i family
>> members like the A23.
>>
>> The AHB1 gates got split up into AHB1 and AHB2, with AHB2 clock source
>> being muxable between AHB1 and PLL6/2, but still sharing gate registers.
>> The documentation isn't totally clear about which devices belong to
>> AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner
>> kernel source code.
>>
>> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt |  7 ++++
>>  drivers/clk/sunxi/clk-sunxi.c                     | 46 ++++++++++++++++++++++-
>>  2 files changed, 52 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index 4fa11af..4eeb893 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -14,6 +14,8 @@ Required properties:
>>         "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
>>         "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
>>         "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
>> +       "allwinner,sun8i-h3-pll6-clk" - for the PLL6 clock on H3
>> +       "allwinner,sun8i-h3-pll8-clk" - for the PLL8 clock on H3
>>         "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
>>         "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
>>         "allwinner,sun4i-a10-axi-clk" - for the AXI clock
>> @@ -28,8 +30,11 @@ Required properties:
>>         "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
>>         "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
>>         "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
>> +       "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
>>         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>>         "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
>> +       "allwinner,sun8i-h3-ahb1-gates-clk" - for the AHB1 gates on H3
>> +       "allwinner,sun8i-h3-ahb2-gates-clk" - for the AHB2 gates on H3
>>         "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
>>         "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
>>         "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
>> @@ -52,8 +57,10 @@ Required properties:
>>         "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
>>         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
>>         "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
>> +       "allwinner,sun8i-h3-apb1-gates-clk" - for the APB1 gates on H3
>>         "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
>>         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
>> +       "allwinner,sun8i-h3-apb2-gates-clk" - for the APB2 gates on H3
>>         "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
>>         "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
>>         "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> index 7e1e2bd..152a1f7 100644
>> --- a/drivers/clk/sunxi/clk-sunxi.c
>> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> @@ -727,6 +727,12 @@ static const struct factors_data sun5i_a13_ahb_data __initconst = {
>>         .getter = sun5i_a13_get_ahb_factors,
>>  };
>>
>> +static const struct factors_data sun8i_h3_pll8_data __initconst = {
>> +       .enable = 31,
>> +       .table = &sun6i_a31_pll6_config,
>> +       .getter = sun6i_a31_get_pll6_factors,
>> +};
>> +
> 
> If it's fully compatible with sun6i-a31-pll6, please just use it.
> 
> On second thought, maybe it's not working because of the .name field?
> If so, you're missing one here.

It complained about the .name field.
But I notice now, the name was correct, it gives us a pll8 running twice
as fast as it should. pll8 doesn't have the x2 output.

So, self-NACK

> 
>>  static const struct factors_data sun4i_apb1_data __initconst = {
>>         .mux = 24,
>>         .muxmask = BIT(1) | BIT(0),
>> @@ -777,6 +783,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
>>         .shift = 12,
>>  };
>>
>> +static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
>> +       .shift = 0,
>> +};
>> +
>>  static void __init sunxi_mux_clk_setup(struct device_node *node,
>>                                        struct mux_data *data)
>>  {
>> @@ -892,7 +902,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
>>   * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
>>   */
>>
>> -#define SUNXI_GATES_MAX_SIZE   64
>> +#define SUNXI_GATES_MAX_SIZE   160
>>
>>  struct gates_data {
>>         DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
>> @@ -926,6 +936,10 @@ static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
>>         .mask = {0x25386742, 0x2505111},
>>  };
>>
>> +static const struct gates_data sun8i_h3_ahb1_gates_data __initconst = {
>> +       .mask = {0x1fbc6760, 0x00701b39, 0x00000000, 0x00000000, 0x00000081},
>> +};
>> +
> 
> Wow, what's with the hardware design... :|

Yeah, I don't like that too, but Allwinner's kernel source says EPHY is
on AHB1.
If anyone has a better idea how to implement this I'm happy to hear it.
Maybe we should simply add a ahb1_gates2 for the new register.

> 
>>  static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
>>         .mask = {0xF5F12B},
>>  };
>> @@ -938,6 +952,10 @@ static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
>>         .mask = {0x9B7},
>>  };
>>
>> +static const struct gates_data sun8i_h3_ahb2_gates_data __initconst = {
>> +       .mask = {0xe0020000},
>> +};
>> +
>>  static const struct gates_data sun4i_apb0_gates_data __initconst = {
>>         .mask = {0x4EF},
>>  };
>> @@ -978,6 +996,10 @@ static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
>>         .mask = {0x3021},
>>  };
>>
>> +static const struct gates_data sun8i_h3_apb1_gates_data __initconst = {
>> +       .mask = {0x7123},
>> +};
>> +
>>  static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
>>         .mask = {0x3F000F},
>>  };
>> @@ -994,6 +1016,10 @@ static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
>>         .mask = {0x1F0007},
>>  };
>>
>> +static const struct gates_data sun8i_h3_apb2_gates_data __initconst = {
>> +       .mask = {0x1F0007},
>> +};
>> +
>>  static void __init sunxi_gates_clk_setup(struct device_node *node,
>>                                          struct gates_data *data)
>>  {
>> @@ -1106,6 +1132,16 @@ static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
>>         }
>>  };
>>
>> +static const struct divs_data sun8i_h3_pll6_divs_data __initconst = {
>> +       .factors = &sun6i_a31_pll6_data,
>> +       .ndivs = 3,
>> +       .div = {
>> +               { .fixed = 2 }, /* normal output, pll6 */
>> +               { .self = 1 }, /* base factor clock, pll6 x2 */
>> +               { .fixed = 4 }, /* divided output, pll6 /2 */
> 
> Since you have the luxury of starting a new binding, maybe you could
> put the ".self" clock first?

I wanted to keep it compatible to the older SoCs, and it felt logical to
have the normal output at first position.

> 
>> +       }
>> +};
>> +
>>  /**
>>   * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
>>   *
>> @@ -1252,6 +1288,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
>>         {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
>>         {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
>>         {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
>> +       {.compatible = "allwinner,sun8i-h3-pll8-clk", .data = &sun8i_h3_pll8_data,},
> 
> Matching comment above, no need to add a new compatible for something that's
> the same.

PLL8 doesn't have a x2 output according to User Manual, but I did it
wrong anyway, see first comment.

This will need some more work I think.

Jens

Re: [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 5844 bytes --]

On Wed, May 06, 2015 at 11:31:29AM +0200, Jens Kuske wrote:
> The H3 clock control unit is similar to the those of other sun8i family
> members like the A23.
> 
> The AHB1 gates got split up into AHB1 and AHB2, with AHB2 clock source
> being muxable between AHB1 and PLL6/2, but still sharing gate registers.
> The documentation isn't totally clear about which devices belong to
> AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner
> kernel source code.
> 
> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  7 ++++
>  drivers/clk/sunxi/clk-sunxi.c                     | 46 ++++++++++++++++++++++-
>  2 files changed, 52 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 4fa11af..4eeb893 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -14,6 +14,8 @@ Required properties:
>  	"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
>  	"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
>  	"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
> +	"allwinner,sun8i-h3-pll6-clk" - for the PLL6 clock on H3
> +	"allwinner,sun8i-h3-pll8-clk" - for the PLL8 clock on H3
>  	"allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
>  	"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
>  	"allwinner,sun4i-a10-axi-clk" - for the AXI clock
> @@ -28,8 +30,11 @@ Required properties:
>  	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
>  	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
>  	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
> +	"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
>  	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>  	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
> +	"allwinner,sun8i-h3-ahb1-gates-clk" - for the AHB1 gates on H3
> +	"allwinner,sun8i-h3-ahb2-gates-clk" - for the AHB2 gates on H3
>  	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
>  	"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
>  	"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
> @@ -52,8 +57,10 @@ Required properties:
>  	"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
>  	"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
>  	"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
> +	"allwinner,sun8i-h3-apb1-gates-clk" - for the APB1 gates on H3
>  	"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
>  	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
> +	"allwinner,sun8i-h3-apb2-gates-clk" - for the APB2 gates on H3
>  	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
>  	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
>  	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 7e1e2bd..152a1f7 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -727,6 +727,12 @@ static const struct factors_data sun5i_a13_ahb_data __initconst = {
>  	.getter = sun5i_a13_get_ahb_factors,
>  };
>  
> +static const struct factors_data sun8i_h3_pll8_data __initconst = {
> +	.enable = 31,
> +	.table = &sun6i_a31_pll6_config,
> +	.getter = sun6i_a31_get_pll6_factors,
> +};

This looks like it's just another instance of the A31 pll6.

In such a case, we don't need to declare a new driver, just reuse the
same compatible.

>  static const struct factors_data sun4i_apb1_data __initconst = {
>  	.mux = 24,
>  	.muxmask = BIT(1) | BIT(0),
> @@ -777,6 +783,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
>  	.shift = 12,
>  };
>  
> +static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
> +	.shift = 0,
> +};
> +
>  static void __init sunxi_mux_clk_setup(struct device_node *node,
>  				       struct mux_data *data)
>  {
> @@ -892,7 +902,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
>   * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
>   */
>  
> -#define SUNXI_GATES_MAX_SIZE	64
> +#define SUNXI_GATES_MAX_SIZE	160
>  
>  struct gates_data {
>  	DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> @@ -926,6 +936,10 @@ static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
>  	.mask = {0x25386742, 0x2505111},
>  };
>  
> +static const struct gates_data sun8i_h3_ahb1_gates_data __initconst = {
> +	.mask = {0x1fbc6760, 0x00701b39, 0x00000000, 0x00000000, 0x00000081},
> +};
> +

Judging from the user manual, there's a few gates in those 0
registers, is this normal that you don't support them?

>  static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
>  	.mask = {0xF5F12B},
>  };
> @@ -938,6 +952,10 @@ static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
>  	.mask = {0x9B7},
>  };
>  
> +static const struct gates_data sun8i_h3_ahb2_gates_data __initconst = {
> +	.mask = {0xe0020000},
> +};
> +

I don't think we should split the ahb1 and ahb2 gates here. It really
looks like it's the same controller.

The way I'm seeing it would be to have a single clock driver that
would handle both your ahb1 and ahb2 gates.

It would take two parents, ahb1 and ahb2, obviously, and would take
register depending on the gate w'ere registering either the ahb1 or
the ahb2 parent.

It seems like there's only a handful of devices in ahb2 anyway, so
that wouldn't make a very long list of devices to declare as childs of
ahb2.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1151 bytes --]

On Wed, May 06, 2015 at 12:18:11PM +0200, Jens Kuske wrote:
> >>  /**
> >>   * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
> >>   *
> >> @@ -1252,6 +1288,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
> >>         {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
> >>         {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
> >>         {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
> >> +       {.compatible = "allwinner,sun8i-h3-pll8-clk", .data = &sun8i_h3_pll8_data,},
> > 
> > Matching comment above, no need to add a new compatible for something that's
> > the same.
> 
> PLL8 doesn't have a x2 output according to User Manual, but I did it
> wrong anyway, see first comment.

Don't worry too much about that output.

It's not really an output, it's a pre-multiplier on a single
child. We're discussing with Chen-Yu about refactoring this anyway, so
it will probably go away in a near future.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Jens Kuske]

Hi,

On 09/05/15 13:27, Maxime Ripard wrote:
> On Wed, May 06, 2015 at 11:31:29AM +0200, Jens Kuske wrote:
>> The H3 clock control unit is similar to the those of other sun8i family
>> members like the A23.
>>
>> The AHB1 gates got split up into AHB1 and AHB2, with AHB2 clock source
>> being muxable between AHB1 and PLL6/2, but still sharing gate registers.
>> The documentation isn't totally clear about which devices belong to
>> AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner
>> kernel source code.
>>
>> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt |  7 ++++
>>  drivers/clk/sunxi/clk-sunxi.c                     | 46 ++++++++++++++++++++++-
>>  2 files changed, 52 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index 4fa11af..4eeb893 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -14,6 +14,8 @@ Required properties:
>>  	"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
>>  	"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
>>  	"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
>> +	"allwinner,sun8i-h3-pll6-clk" - for the PLL6 clock on H3
>> +	"allwinner,sun8i-h3-pll8-clk" - for the PLL8 clock on H3
>>  	"allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
>>  	"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
>>  	"allwinner,sun4i-a10-axi-clk" - for the AXI clock
>> @@ -28,8 +30,11 @@ Required properties:
>>  	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
>>  	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
>>  	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
>> +	"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
>>  	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>>  	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
>> +	"allwinner,sun8i-h3-ahb1-gates-clk" - for the AHB1 gates on H3
>> +	"allwinner,sun8i-h3-ahb2-gates-clk" - for the AHB2 gates on H3
>>  	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
>>  	"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
>>  	"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
>> @@ -52,8 +57,10 @@ Required properties:
>>  	"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
>>  	"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
>>  	"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
>> +	"allwinner,sun8i-h3-apb1-gates-clk" - for the APB1 gates on H3
>>  	"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
>>  	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
>> +	"allwinner,sun8i-h3-apb2-gates-clk" - for the APB2 gates on H3
>>  	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
>>  	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
>>  	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> index 7e1e2bd..152a1f7 100644
>> --- a/drivers/clk/sunxi/clk-sunxi.c
>> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> @@ -727,6 +727,12 @@ static const struct factors_data sun5i_a13_ahb_data __initconst = {
>>  	.getter = sun5i_a13_get_ahb_factors,
>>  };
>>  
>> +static const struct factors_data sun8i_h3_pll8_data __initconst = {
>> +	.enable = 31,
>> +	.table = &sun6i_a31_pll6_config,
>> +	.getter = sun6i_a31_get_pll6_factors,
>> +};
> 
> This looks like it's just another instance of the A31 pll6.
> 
> In such a case, we don't need to declare a new driver, just reuse the
> same compatible.

If I reuse pll6 for pll8 I get errors because of the .name = "pll6x2"
field, already existing clock or something like that. (And pll8 doesn't
even have a x2 version)

> 
>>  static const struct factors_data sun4i_apb1_data __initconst = {
>>  	.mux = 24,
>>  	.muxmask = BIT(1) | BIT(0),
>> @@ -777,6 +783,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
>>  	.shift = 12,
>>  };
>>  
>> +static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
>> +	.shift = 0,
>> +};
>> +
>>  static void __init sunxi_mux_clk_setup(struct device_node *node,
>>  				       struct mux_data *data)
>>  {
>> @@ -892,7 +902,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
>>   * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
>>   */
>>  
>> -#define SUNXI_GATES_MAX_SIZE	64
>> +#define SUNXI_GATES_MAX_SIZE	160
>>  
>>  struct gates_data {
>>  	DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
>> @@ -926,6 +936,10 @@ static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
>>  	.mask = {0x25386742, 0x2505111},
>>  };
>>  
>> +static const struct gates_data sun8i_h3_ahb1_gates_data __initconst = {
>> +	.mask = {0x1fbc6760, 0x00701b39, 0x00000000, 0x00000000, 0x00000081},
>> +};
>> +
> 
> Judging from the user manual, there's a few gates in those 0
> registers, is this normal that you don't support them?

They are holes for apb1 and apb2. Which is actually pretty ugly.

> 
>>  static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
>>  	.mask = {0xF5F12B},
>>  };
>> @@ -938,6 +952,10 @@ static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
>>  	.mask = {0x9B7},
>>  };
>>  
>> +static const struct gates_data sun8i_h3_ahb2_gates_data __initconst = {
>> +	.mask = {0xe0020000},
>> +};
>> +
> 
> I don't think we should split the ahb1 and ahb2 gates here. It really
> looks like it's the same controller.
> 
> The way I'm seeing it would be to have a single clock driver that
> would handle both your ahb1 and ahb2 gates.
> 
> It would take two parents, ahb1 and ahb2, obviously, and would take
> register depending on the gate w'ere registering either the ahb1 or
> the ahb2 parent.
> 
> It seems like there's only a handful of devices in ahb2 anyway, so
> that wouldn't make a very long list of devices to declare as childs of
> ahb2.
> 

I have thought about adding a bus_gates driver for all ahb1, ahb2, apb1
and apb2 gates, as it is done in the user manual.

But it would need a pretty big parents array and result in big gate
numbers in devicetree, <&bus_gates 112> for uart0 for example.

Would this be ok?

Jens

Re: [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 7262 bytes --]

Hi,

On Sun, May 10, 2015 at 12:54:50PM +0200, Jens Kuske wrote:
> On 09/05/15 13:27, Maxime Ripard wrote:
> > On Wed, May 06, 2015 at 11:31:29AM +0200, Jens Kuske wrote:
> >> The H3 clock control unit is similar to the those of other sun8i family
> >> members like the A23.
> >>
> >> The AHB1 gates got split up into AHB1 and AHB2, with AHB2 clock source
> >> being muxable between AHB1 and PLL6/2, but still sharing gate registers.
> >> The documentation isn't totally clear about which devices belong to
> >> AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner
> >> kernel source code.
> >>
> >> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> >> ---
> >>  Documentation/devicetree/bindings/clock/sunxi.txt |  7 ++++
> >>  drivers/clk/sunxi/clk-sunxi.c                     | 46 ++++++++++++++++++++++-
> >>  2 files changed, 52 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> >> index 4fa11af..4eeb893 100644
> >> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> >> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> >> @@ -14,6 +14,8 @@ Required properties:
> >>  	"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
> >>  	"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
> >>  	"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
> >> +	"allwinner,sun8i-h3-pll6-clk" - for the PLL6 clock on H3
> >> +	"allwinner,sun8i-h3-pll8-clk" - for the PLL8 clock on H3
> >>  	"allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
> >>  	"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
> >>  	"allwinner,sun4i-a10-axi-clk" - for the AXI clock
> >> @@ -28,8 +30,11 @@ Required properties:
> >>  	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
> >>  	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
> >>  	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
> >> +	"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
> >>  	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
> >>  	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
> >> +	"allwinner,sun8i-h3-ahb1-gates-clk" - for the AHB1 gates on H3
> >> +	"allwinner,sun8i-h3-ahb2-gates-clk" - for the AHB2 gates on H3
> >>  	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
> >>  	"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
> >>  	"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
> >> @@ -52,8 +57,10 @@ Required properties:
> >>  	"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
> >>  	"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
> >>  	"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
> >> +	"allwinner,sun8i-h3-apb1-gates-clk" - for the APB1 gates on H3
> >>  	"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
> >>  	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
> >> +	"allwinner,sun8i-h3-apb2-gates-clk" - for the APB2 gates on H3
> >>  	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
> >>  	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
> >>  	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
> >> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> >> index 7e1e2bd..152a1f7 100644
> >> --- a/drivers/clk/sunxi/clk-sunxi.c
> >> +++ b/drivers/clk/sunxi/clk-sunxi.c
> >> @@ -727,6 +727,12 @@ static const struct factors_data sun5i_a13_ahb_data __initconst = {
> >>  	.getter = sun5i_a13_get_ahb_factors,
> >>  };
> >>  
> >> +static const struct factors_data sun8i_h3_pll8_data __initconst = {
> >> +	.enable = 31,
> >> +	.table = &sun6i_a31_pll6_config,
> >> +	.getter = sun6i_a31_get_pll6_factors,
> >> +};
> > 
> > This looks like it's just another instance of the A31 pll6.
> > 
> > In such a case, we don't need to declare a new driver, just reuse the
> > same compatible.
> 
> If I reuse pll6 for pll8 I get errors because of the .name = "pll6x2"
> field, already existing clock or something like that.

Damn. You're obviously right...

Could you add a TODO comment on top then? just so that we know that we
need to merge this clock with pll6?

> (And pll8 doesn't even have a x2 version)

Judging by the H3 datasheet, it does.

> >>  static const struct factors_data sun4i_apb1_data __initconst = {
> >>  	.mux = 24,
> >>  	.muxmask = BIT(1) | BIT(0),
> >> @@ -777,6 +783,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
> >>  	.shift = 12,
> >>  };
> >>  
> >> +static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
> >> +	.shift = 0,
> >> +};
> >> +
> >>  static void __init sunxi_mux_clk_setup(struct device_node *node,
> >>  				       struct mux_data *data)
> >>  {
> >> @@ -892,7 +902,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
> >>   * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
> >>   */
> >>  
> >> -#define SUNXI_GATES_MAX_SIZE	64
> >> +#define SUNXI_GATES_MAX_SIZE	160
> >>  
> >>  struct gates_data {
> >>  	DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> >> @@ -926,6 +936,10 @@ static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
> >>  	.mask = {0x25386742, 0x2505111},
> >>  };
> >>  
> >> +static const struct gates_data sun8i_h3_ahb1_gates_data __initconst = {
> >> +	.mask = {0x1fbc6760, 0x00701b39, 0x00000000, 0x00000000, 0x00000081},
> >> +};
> >> +
> > 
> > Judging from the user manual, there's a few gates in those 0
> > registers, is this normal that you don't support them?
> 
> They are holes for apb1 and apb2. Which is actually pretty ugly.

Ah, right.

So I guess it's completely related to the discussion below.

> >>  static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
> >>  	.mask = {0xF5F12B},
> >>  };
> >> @@ -938,6 +952,10 @@ static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
> >>  	.mask = {0x9B7},
> >>  };
> >>  
> >> +static const struct gates_data sun8i_h3_ahb2_gates_data __initconst = {
> >> +	.mask = {0xe0020000},
> >> +};
> >> +
> > 
> > I don't think we should split the ahb1 and ahb2 gates here. It really
> > looks like it's the same controller.
> > 
> > The way I'm seeing it would be to have a single clock driver that
> > would handle both your ahb1 and ahb2 gates.
> > 
> > It would take two parents, ahb1 and ahb2, obviously, and would take
> > register depending on the gate w'ere registering either the ahb1 or
> > the ahb2 parent.
> > 
> > It seems like there's only a handful of devices in ahb2 anyway, so
> > that wouldn't make a very long list of devices to declare as childs of
> > ahb2.
> > 
> 
> I have thought about adding a bus_gates driver for all ahb1, ahb2, apb1
> and apb2 gates, as it is done in the user manual.
> 
> But it would need a pretty big parents array and result in big gate
> numbers in devicetree, <&bus_gates 112> for uart0 for example.
> 
> Would this be ok?

I don't see anything wrong with that, as long as we have a clear
documentation stating where that number comes from.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Chen-Yu Tsai]

On Tue, May 12, 2015 at 10:44 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi,
>
> On Sun, May 10, 2015 at 12:54:50PM +0200, Jens Kuske wrote:
>> On 09/05/15 13:27, Maxime Ripard wrote:
>> > On Wed, May 06, 2015 at 11:31:29AM +0200, Jens Kuske wrote:
>> >> The H3 clock control unit is similar to the those of other sun8i family
>> >> members like the A23.
>> >>
>> >> The AHB1 gates got split up into AHB1 and AHB2, with AHB2 clock source
>> >> being muxable between AHB1 and PLL6/2, but still sharing gate registers.
>> >> The documentation isn't totally clear about which devices belong to
>> >> AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner
>> >> kernel source code.
>> >>
>> >> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> >> ---
>> >>  Documentation/devicetree/bindings/clock/sunxi.txt |  7 ++++
>> >>  drivers/clk/sunxi/clk-sunxi.c                     | 46 ++++++++++++++++++++++-
>> >>  2 files changed, 52 insertions(+), 1 deletion(-)
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> >> index 4fa11af..4eeb893 100644
>> >> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> >> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> >> @@ -14,6 +14,8 @@ Required properties:
>> >>    "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
>> >>    "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
>> >>    "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
>> >> +  "allwinner,sun8i-h3-pll6-clk" - for the PLL6 clock on H3
>> >> +  "allwinner,sun8i-h3-pll8-clk" - for the PLL8 clock on H3
>> >>    "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
>> >>    "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
>> >>    "allwinner,sun4i-a10-axi-clk" - for the AXI clock
>> >> @@ -28,8 +30,11 @@ Required properties:
>> >>    "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
>> >>    "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
>> >>    "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
>> >> +  "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
>> >>    "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>> >>    "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
>> >> +  "allwinner,sun8i-h3-ahb1-gates-clk" - for the AHB1 gates on H3
>> >> +  "allwinner,sun8i-h3-ahb2-gates-clk" - for the AHB2 gates on H3
>> >>    "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
>> >>    "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
>> >>    "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
>> >> @@ -52,8 +57,10 @@ Required properties:
>> >>    "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
>> >>    "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
>> >>    "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
>> >> +  "allwinner,sun8i-h3-apb1-gates-clk" - for the APB1 gates on H3
>> >>    "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
>> >>    "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
>> >> +  "allwinner,sun8i-h3-apb2-gates-clk" - for the APB2 gates on H3
>> >>    "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
>> >>    "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
>> >>    "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
>> >> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> >> index 7e1e2bd..152a1f7 100644
>> >> --- a/drivers/clk/sunxi/clk-sunxi.c
>> >> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> >> @@ -727,6 +727,12 @@ static const struct factors_data sun5i_a13_ahb_data __initconst = {
>> >>    .getter = sun5i_a13_get_ahb_factors,
>> >>  };
>> >>
>> >> +static const struct factors_data sun8i_h3_pll8_data __initconst = {
>> >> +  .enable = 31,
>> >> +  .table = &sun6i_a31_pll6_config,
>> >> +  .getter = sun6i_a31_get_pll6_factors,
>> >> +};
>> >
>> > This looks like it's just another instance of the A31 pll6.
>> >
>> > In such a case, we don't need to declare a new driver, just reuse the
>> > same compatible.
>>
>> If I reuse pll6 for pll8 I get errors because of the .name = "pll6x2"
>> field, already existing clock or something like that.
>
> Damn. You're obviously right...

I think I have a solution for this.

The current divs clock setup just passes the factors_data directly to
sunxi_factors_register(). What if it did a copy, read the _correct_
name from the DT (since it knows the index) and put it in the copy.

How does that sound?

> Could you add a TODO comment on top then? just so that we know that we
> need to merge this clock with pll6?
>
>> (And pll8 doesn't even have a x2 version)
>
> Judging by the H3 datasheet, it does.
>
>> >>  static const struct factors_data sun4i_apb1_data __initconst = {
>> >>    .mux = 24,
>> >>    .muxmask = BIT(1) | BIT(0),
>> >> @@ -777,6 +783,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
>> >>    .shift = 12,
>> >>  };
>> >>
>> >> +static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
>> >> +  .shift = 0,
>> >> +};
>> >> +
>> >>  static void __init sunxi_mux_clk_setup(struct device_node *node,
>> >>                                   struct mux_data *data)
>> >>  {
>> >> @@ -892,7 +902,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
>> >>   * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
>> >>   */
>> >>
>> >> -#define SUNXI_GATES_MAX_SIZE      64
>> >> +#define SUNXI_GATES_MAX_SIZE      160
>> >>
>> >>  struct gates_data {
>> >>    DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
>> >> @@ -926,6 +936,10 @@ static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
>> >>    .mask = {0x25386742, 0x2505111},
>> >>  };
>> >>
>> >> +static const struct gates_data sun8i_h3_ahb1_gates_data __initconst = {
>> >> +  .mask = {0x1fbc6760, 0x00701b39, 0x00000000, 0x00000000, 0x00000081},
>> >> +};
>> >> +
>> >
>> > Judging from the user manual, there's a few gates in those 0
>> > registers, is this normal that you don't support them?
>>
>> They are holes for apb1 and apb2. Which is actually pretty ugly.
>
> Ah, right.
>
> So I guess it's completely related to the discussion below.

If the holes are really big, I guess you could split ahb and apb?


ChenYu

>> >>  static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
>> >>    .mask = {0xF5F12B},
>> >>  };
>> >> @@ -938,6 +952,10 @@ static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
>> >>    .mask = {0x9B7},
>> >>  };
>> >>
>> >> +static const struct gates_data sun8i_h3_ahb2_gates_data __initconst = {
>> >> +  .mask = {0xe0020000},
>> >> +};
>> >> +
>> >
>> > I don't think we should split the ahb1 and ahb2 gates here. It really
>> > looks like it's the same controller.
>> >
>> > The way I'm seeing it would be to have a single clock driver that
>> > would handle both your ahb1 and ahb2 gates.
>> >
>> > It would take two parents, ahb1 and ahb2, obviously, and would take
>> > register depending on the gate w'ere registering either the ahb1 or
>> > the ahb2 parent.
>> >
>> > It seems like there's only a handful of devices in ahb2 anyway, so
>> > that wouldn't make a very long list of devices to declare as childs of
>> > ahb2.
>> >
>>
>> I have thought about adding a bus_gates driver for all ahb1, ahb2, apb1
>> and apb2 gates, as it is done in the user manual.
>>
>> But it would need a pretty big parents array and result in big gate
>> numbers in devicetree, <&bus_gates 112> for uart0 for example.
>>
>> Would this be ok?
>
> I don't see anything wrong with that, as long as we have a clear
> documentation stating where that number comes from.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
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Re: [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 7092 bytes --]

On Thu, May 14, 2015 at 01:14:25PM +0800, Chen-Yu Tsai wrote:
> On Tue, May 12, 2015 at 10:44 PM, Maxime Ripard
> <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> > Hi,
> >
> > On Sun, May 10, 2015 at 12:54:50PM +0200, Jens Kuske wrote:
> >> On 09/05/15 13:27, Maxime Ripard wrote:
> >> > On Wed, May 06, 2015 at 11:31:29AM +0200, Jens Kuske wrote:
> >> >> The H3 clock control unit is similar to the those of other sun8i family
> >> >> members like the A23.
> >> >>
> >> >> The AHB1 gates got split up into AHB1 and AHB2, with AHB2 clock source
> >> >> being muxable between AHB1 and PLL6/2, but still sharing gate registers.
> >> >> The documentation isn't totally clear about which devices belong to
> >> >> AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner
> >> >> kernel source code.
> >> >>
> >> >> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> >> >> ---
> >> >>  Documentation/devicetree/bindings/clock/sunxi.txt |  7 ++++
> >> >>  drivers/clk/sunxi/clk-sunxi.c                     | 46 ++++++++++++++++++++++-
> >> >>  2 files changed, 52 insertions(+), 1 deletion(-)
> >> >>
> >> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> >> >> index 4fa11af..4eeb893 100644
> >> >> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> >> >> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> >> >> @@ -14,6 +14,8 @@ Required properties:
> >> >>    "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
> >> >>    "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
> >> >>    "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
> >> >> +  "allwinner,sun8i-h3-pll6-clk" - for the PLL6 clock on H3
> >> >> +  "allwinner,sun8i-h3-pll8-clk" - for the PLL8 clock on H3
> >> >>    "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
> >> >>    "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
> >> >>    "allwinner,sun4i-a10-axi-clk" - for the AXI clock
> >> >> @@ -28,8 +30,11 @@ Required properties:
> >> >>    "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
> >> >>    "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
> >> >>    "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
> >> >> +  "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
> >> >>    "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
> >> >>    "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
> >> >> +  "allwinner,sun8i-h3-ahb1-gates-clk" - for the AHB1 gates on H3
> >> >> +  "allwinner,sun8i-h3-ahb2-gates-clk" - for the AHB2 gates on H3
> >> >>    "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
> >> >>    "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
> >> >>    "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
> >> >> @@ -52,8 +57,10 @@ Required properties:
> >> >>    "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
> >> >>    "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
> >> >>    "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
> >> >> +  "allwinner,sun8i-h3-apb1-gates-clk" - for the APB1 gates on H3
> >> >>    "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
> >> >>    "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
> >> >> +  "allwinner,sun8i-h3-apb2-gates-clk" - for the APB2 gates on H3
> >> >>    "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
> >> >>    "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
> >> >>    "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
> >> >> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> >> >> index 7e1e2bd..152a1f7 100644
> >> >> --- a/drivers/clk/sunxi/clk-sunxi.c
> >> >> +++ b/drivers/clk/sunxi/clk-sunxi.c
> >> >> @@ -727,6 +727,12 @@ static const struct factors_data sun5i_a13_ahb_data __initconst = {
> >> >>    .getter = sun5i_a13_get_ahb_factors,
> >> >>  };
> >> >>
> >> >> +static const struct factors_data sun8i_h3_pll8_data __initconst = {
> >> >> +  .enable = 31,
> >> >> +  .table = &sun6i_a31_pll6_config,
> >> >> +  .getter = sun6i_a31_get_pll6_factors,
> >> >> +};
> >> >
> >> > This looks like it's just another instance of the A31 pll6.
> >> >
> >> > In such a case, we don't need to declare a new driver, just reuse the
> >> > same compatible.
> >>
> >> If I reuse pll6 for pll8 I get errors because of the .name = "pll6x2"
> >> field, already existing clock or something like that.
> >
> > Damn. You're obviously right...
> 
> I think I have a solution for this.
> 
> The current divs clock setup just passes the factors_data directly to
> sunxi_factors_register(). What if it did a copy, read the _correct_
> name from the DT (since it knows the index) and put it in the copy.
> 
> How does that sound?

That sounds great, but what name would you take from the DT? The first
of clock-output-names? the last one? a random one?

> 
> > Could you add a TODO comment on top then? just so that we know that we
> > need to merge this clock with pll6?
> >
> >> (And pll8 doesn't even have a x2 version)
> >
> > Judging by the H3 datasheet, it does.
> >
> >> >>  static const struct factors_data sun4i_apb1_data __initconst = {
> >> >>    .mux = 24,
> >> >>    .muxmask = BIT(1) | BIT(0),
> >> >> @@ -777,6 +783,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
> >> >>    .shift = 12,
> >> >>  };
> >> >>
> >> >> +static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
> >> >> +  .shift = 0,
> >> >> +};
> >> >> +
> >> >>  static void __init sunxi_mux_clk_setup(struct device_node *node,
> >> >>                                   struct mux_data *data)
> >> >>  {
> >> >> @@ -892,7 +902,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
> >> >>   * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
> >> >>   */
> >> >>
> >> >> -#define SUNXI_GATES_MAX_SIZE      64
> >> >> +#define SUNXI_GATES_MAX_SIZE      160
> >> >>
> >> >>  struct gates_data {
> >> >>    DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> >> >> @@ -926,6 +936,10 @@ static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
> >> >>    .mask = {0x25386742, 0x2505111},
> >> >>  };
> >> >>
> >> >> +static const struct gates_data sun8i_h3_ahb1_gates_data __initconst = {
> >> >> +  .mask = {0x1fbc6760, 0x00701b39, 0x00000000, 0x00000000, 0x00000081},
> >> >> +};
> >> >> +
> >> >
> >> > Judging from the user manual, there's a few gates in those 0
> >> > registers, is this normal that you don't support them?
> >>
> >> They are holes for apb1 and apb2. Which is actually pretty ugly.
> >
> > Ah, right.
> >
> > So I guess it's completely related to the discussion below.
> 
> If the holes are really big, I guess you could split ahb and apb?

It's actually already split. The holes in the ahb1 registers are for
the apb clocks.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Jens Kuske]

Hi everyone,

This is v3 of my patch series introducing basic kernel support for Allwinner's
H3 SoC. It mainly adds basic clocks and pinctrl. It also adds interrupts,
timers, watchdog, RTC, dmaengine, MMC and UARTs, which are mostly compatible
to those in earlier SoCs like A23 and A31, and can simply be reused.

These patches are based on Maxime's sunxi/for-next branch from
git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git


Patch 1 improves the sunxi divs clock to read the name of the base factor clock
from devicetree instead of hardcoding it, which allows us to reuse sun6i-pll6
for our pll8.

Patch 2 adds support for the basic clocks.

Patch 3 adds the pin sets for the H3 main PIO.

Patch 4 adds a new compatible for the H3 reset controller

Patch 5 adds the DTSI for the H3.

Patch 6 adds a DTS for the Orange Pi Plus SBC, which these patches
were developed and tested with.


Changes since v2:
- add mbus clock
- add Maxime's suggestion to take the substring up to the first "_" as name
  for the divs base clock
- use A31 pll6 for H3 pll6
- use a clock similar to the new simple gates for H3 bus gates
- drop the pinctrl-as-module patch since pinctrl and gpio don't seem to be
  ready for removable drivers
- documentation and machine support are merged already
  
Changes since v1:
- Update sunxi README in Documentation
- Add the multiple parents gates and use them for bus-gates instead of
  ahb1, ahb2, apb1 and apb2 gates
- Merge the pll8 clock with sun6i pll6
- Merge the ahb12, apb1 and apb2 resets to bus-resets with own compatible
- Add sun6i_timer_init to sun8i machine
- Remove the single SoC names from machine definition, its sun8i family
- Make the pinctrl driver tristate and put its Kconfig entry in the right order
- Rename pinctrl "scr" to "sim" and clock "sim" to "scr" to match user manual
- Remove the address paragraph from GPL in dts and dtsi
- Some style cleanup and line wrapping in dtsi
- Add ARM architected timers
- dmaengine isn't included anymore, it is merged already

Best Regards,
Jens


Jens Kuske (6):
  clk: sunxi: Let divs clocks read the base factor clock name from
    devicetree
  clk: sunxi: Add H3 clocks support
  pinctrl: sunxi: Add H3 PIO controller support
  reset: sunxi: Add compatible for Allwinner H3 bus resets
  ARM: dts: sunxi: Add Allwinner H3 DTSI
  ARM: dts: sun8i: Add Orange Pi Plus support

 Documentation/devicetree/bindings/clock/sunxi.txt  |   2 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 .../bindings/reset/allwinner,sunxi-clock-reset.txt |   1 +
 arch/arm/boot/dts/Makefile                         |   3 +-
 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts       |  77 +++
 arch/arm/boot/dts/sun8i-h3.dtsi                    | 499 ++++++++++++++++++++
 drivers/clk/sunxi/Makefile                         |   1 +
 drivers/clk/sunxi/clk-bus-gates.c                  | 105 +++++
 drivers/clk/sunxi/clk-sunxi.c                      |  47 +-
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c           | 516 +++++++++++++++++++++
 drivers/reset/reset-sunxi.c                        |   1 +
 13 files changed, 1245 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
 create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi
 create mode 100644 drivers/clk/sunxi/clk-bus-gates.c
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c

-- 
2.6.1

[PATCH 1/6] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

[Jens Kuske]

Currently, the sunxi clock driver gets the name for the base factor clock
of divs clocks from the name field in factors_data. This prevents reusing
of the factor clock for clocks with same properties, but different name.

This commit makes the divs setup function try to get a name from
clock-output-names in the devicetree. It also removes the name field where
possible and merges the sun4i PLL5 and PLL6 clocks.

Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/clk/sunxi/clk-sunxi.c | 39 ++++++++++++++++++++++++++++-----------
 1 file changed, 28 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 9c79af0c..7c4aee0 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -704,21 +704,12 @@ static const struct factors_data sun4i_pll5_data __initconst = {
 	.enable = 31,
 	.table = &sun4i_pll5_config,
 	.getter = sun4i_get_pll5_factors,
-	.name = "pll5",
-};
-
-static const struct factors_data sun4i_pll6_data __initconst = {
-	.enable = 31,
-	.table = &sun4i_pll5_config,
-	.getter = sun4i_get_pll5_factors,
-	.name = "pll6",
 };
 
 static const struct factors_data sun6i_a31_pll6_data __initconst = {
 	.enable = 31,
 	.table = &sun6i_a31_pll6_config,
 	.getter = sun6i_a31_get_pll6_factors,
-	.name = "pll6x2",
 };
 
 static const struct factors_data sun5i_a13_ahb_data __initconst = {
@@ -902,6 +893,7 @@ struct gates_data {
 
 #define SUNXI_DIVS_MAX_QTY	4
 #define SUNXI_DIVISOR_WIDTH	2
+#define SUNXI_DIVS_BASE_NAME_MAX_LEN	8
 
 struct divs_data {
 	const struct factors_data *factors; /* data for the factor clock */
@@ -941,7 +933,7 @@ static const struct divs_data pll5_divs_data __initconst = {
 };
 
 static const struct divs_data pll6_divs_data __initconst = {
-	.factors = &sun4i_pll6_data,
+	.factors = &sun4i_pll5_data,
 	.ndivs = 4,
 	.div = {
 		{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
@@ -983,6 +975,8 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 	struct clk_gate *gate = NULL;
 	struct clk_fixed_factor *fix_factor;
 	struct clk_divider *divider;
+	struct factors_data factors = *data->factors;
+	char base_name[SUNXI_DIVS_BASE_NAME_MAX_LEN];
 	void __iomem *reg;
 	int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
 	int flags, clkflags;
@@ -991,8 +985,31 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 	if (data->ndivs)
 		ndivs = data->ndivs;
 
+	/* Try to find a name for base factor clock */
+	for (i = 0; i < ndivs; i++) {
+		if (data->div[i].self) {
+			of_property_read_string_index(node, "clock-output-names",
+						      i, &factors.name);
+			break;
+		}
+	}
+	/* If we don't have a .self clk use the first output-name up to '_' */
+	if (factors.name == NULL) {
+		of_property_read_string_index(node, "clock-output-names",
+						      0, &clk_name);
+
+		for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 &&
+						clk_name[i] != '_' &&
+						clk_name[i] != '\0'; i++) {
+			base_name[i] = clk_name[i];
+		}
+
+		base_name[i] = '\0';
+		factors.name = base_name;
+	}
+
 	/* Set up factor clock that we will be dividing */
-	pclk = sunxi_factors_clk_setup(node, data->factors);
+	pclk = sunxi_factors_clk_setup(node, &factors);
 	parent = __clk_get_name(pclk);
 
 	reg = of_iomap(node, 0);
-- 
2.6.1

[PATCH 2/6] clk: sunxi: Add H3 clocks support

[Jens Kuske]

The H3 clock control unit is similar to the those of other sun8i family
members like the A23.

It adds a new bus gates clock similar to the simple gates, but with a
different parent clock for each single gate.
Some of the gates use the new AHB2 clock as parent, whose clock source
is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
is mostly based on Allwinner kernel source code.

Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
 drivers/clk/sunxi/Makefile                        |   1 +
 drivers/clk/sunxi/clk-bus-gates.c                 | 105 ++++++++++++++++++++++
 drivers/clk/sunxi/clk-sunxi.c                     |  12 ++-
 4 files changed, 117 insertions(+), 3 deletions(-)
 create mode 100644 drivers/clk/sunxi/clk-bus-gates.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 8a47b77..d303dec 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -28,6 +28,7 @@ Required properties:
 	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
 	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
 	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
+	"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
 	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
 	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
 	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
@@ -55,6 +56,7 @@ Required properties:
 	"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
 	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
 	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+	"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
 	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
 	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
 	"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index f5a35b8..ecaff7f 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -5,6 +5,7 @@
 obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-hosc.o
 obj-y += clk-a20-gmac.o
+obj-y += clk-bus-gates.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
 obj-y += clk-sun8i-mbus.o
diff --git a/drivers/clk/sunxi/clk-bus-gates.c b/drivers/clk/sunxi/clk-bus-gates.c
new file mode 100644
index 0000000..5bba0b9
--- /dev/null
+++ b/drivers/clk/sunxi/clk-bus-gates.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * Based on clk-simple-gates.c, which is:
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+static DEFINE_SPINLOCK(gates_lock);
+
+static void __init sunxi_bus_gates_setup(struct device_node *node,
+					 const int protected[],
+					 int nprotected)
+{
+	struct clk_onecell_data *clk_data;
+	const char *clk_parent, *clk_name;
+	struct property *prop;
+	struct resource res;
+	void __iomem *clk_reg;
+	void __iomem *reg;
+	const __be32 *p;
+	int number, i = 0, j;
+	u8 clk_bit;
+	u32 index;
+
+	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+	if (IS_ERR(reg))
+		return;
+
+	clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+	if (!clk_data)
+		goto err_unmap;
+
+	number = of_property_count_u32_elems(node, "clock-indices");
+	of_property_read_u32_index(node, "clock-indices", number - 1, &number);
+
+	clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
+	if (!clk_data->clks)
+		goto err_free_data;
+
+	of_property_for_each_u32(node, "clock-indices", prop, p, index) {
+		of_property_read_string_index(node, "clock-output-names",
+					      i, &clk_name);
+
+		clk_parent = of_clk_get_parent_name(node, i);
+
+		clk_reg = reg + 4 * (index / 32);
+		clk_bit = index % 32;
+
+		clk_data->clks[index] = clk_register_gate(NULL, clk_name,
+							  clk_parent, 0,
+							  clk_reg,
+							  clk_bit,
+							  0, &gates_lock);
+		i++;
+
+		if (IS_ERR(clk_data->clks[index])) {
+			WARN_ON(true);
+			continue;
+		}
+
+		for (j = 0; j < nprotected; j++)
+			if (protected[j] == index)
+				clk_prepare_enable(clk_data->clks[index]);
+
+	}
+
+	clk_data->clk_num = number + 1;
+	of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+	return;
+
+err_free_data:
+	kfree(clk_data);
+err_unmap:
+	iounmap(reg);
+	of_address_to_resource(node, 0, &res);
+	release_mem_region(res.start, resource_size(&res));
+}
+
+static void __init sunxi_bus_gates_init(struct device_node *node)
+{
+	sunxi_bus_gates_setup(node, NULL, 0);
+}
+
+CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
+	       sunxi_bus_gates_init);
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 7c4aee0..6293c65 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -769,6 +769,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
 	.shift = 12,
 };
 
+static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
+	.shift = 0,
+};
+
 static void __init sunxi_mux_clk_setup(struct device_node *node,
 				       struct mux_data *data)
 {
@@ -945,10 +949,11 @@ static const struct divs_data pll6_divs_data __initconst = {
 
 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
 	.factors = &sun6i_a31_pll6_data,
-	.ndivs = 2,
+	.ndivs = 3,
 	.div = {
 		{ .fixed = 2 }, /* normal output */
 		{ .self = 1 }, /* base factor clock, 2x */
+		{ .fixed = 4 }, /* divided output, /2 */
 	}
 };
 
@@ -1000,9 +1005,8 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 
 		for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 &&
 						clk_name[i] != '_' &&
-						clk_name[i] != '\0'; i++) {
+						clk_name[i] != '\0'; i++)
 			base_name[i] = clk_name[i];
-		}
 
 		base_name[i] = '\0';
 		factors.name = base_name;
@@ -1147,6 +1151,7 @@ static const struct of_device_id clk_divs_match[] __initconst = {
 static const struct of_device_id clk_mux_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
 	{.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
+	{.compatible = "allwinner,sun8i-h3-ahb2-clk", .data = &sun8i_h3_ahb2_mux_data,},
 	{}
 };
 
@@ -1229,6 +1234,7 @@ CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
 CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
+CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);
 
 static void __init sun9i_init_clocks(struct device_node *node)
 {
-- 
2.6.1

Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Hans de Goede]

Hi Jens,

On 21-10-15 18:13, Jens Kuske wrote:
> Hi everyone,
>
> This is v3 of my patch series introducing basic kernel support for Allwinner's
> H3 SoC. It mainly adds basic clocks and pinctrl. It also adds interrupts,
> timers, watchdog, RTC, dmaengine, MMC and UARTs, which are mostly compatible
> to those in earlier SoCs like A23 and A31, and can simply be reused.
>
> These patches are based on Maxime's sunxi/for-next branch from
> git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git
>
>
> Patch 1 improves the sunxi divs clock to read the name of the base factor clock
> from devicetree instead of hardcoding it, which allows us to reuse sun6i-pll6
> for our pll8.
>
> Patch 2 adds support for the basic clocks.
>
> Patch 3 adds the pin sets for the H3 main PIO.
>
> Patch 4 adds a new compatible for the H3 reset controller
>
> Patch 5 adds the DTSI for the H3.
>
> Patch 6 adds a DTS for the Orange Pi Plus SBC, which these patches
> were developed and tested with.

Great to see that you've started working on this again. Last weekend I
ended up working on this too together with Reinder E.N. de Haan <reinder-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org>
(added to the Cc).

We took a slightly different approach for the gates clocks, see:

https://github.com/jwrdegoede/linux-sunxi/commits/sunxi-wip

And specifically:

https://github.com/jwrdegoede/linux-sunxi/commit/80a1afe319d5d1a0c426d42e75d37f0c64e8ea0b

Combined with:

https://github.com/jwrdegoede/linux-sunxi/commit/d508da5feb5048f6674d6b24b58ac9058fb9d877

This deals with the per gate parents the same way the rockchip
clock code does, and it seems to be quite a bit less code then your solution.

So now we've two solutions to chose from :) Since you seem to be back to
working on this I'll refrain from doing any further work, at least
without coordinating. Maxime, can you let us know which solution for the
gates clock parents is best, or tell us if you think both solutions are
no good :)

(I wanted to get in touch with you about the work done this weekend,
but your posting of this v3 has sorta pre-empted that).

Other then the slightly different solution for the gates, the code in my tree
is a straight forward port of your v2.

Thanks for your work on this!

Regards,

Hans


p.s.

I'm teaching a kernel driver course at my local hackerspace in the netherlands:

https://revspace.nl/KernelDriverProgrammingCourse2015

Which is where our work on this this weekend originated. The next planned
course day is November 1st and I expect Reinder to be working on the H3
again then. I think the plan was to tackle USB next. Reinder can you confirm
this ?  If you (Jens) want to work on USB before then, that is fine, but please
coordinate their is plenty to do, so no need for us to be doing (more) double
work.







>
>
> Changes since v2:
> - add mbus clock
> - add Maxime's suggestion to take the substring up to the first "_" as name
>    for the divs base clock
> - use A31 pll6 for H3 pll6
> - use a clock similar to the new simple gates for H3 bus gates
> - drop the pinctrl-as-module patch since pinctrl and gpio don't seem to be
>    ready for removable drivers
> - documentation and machine support are merged already
>
> Changes since v1:
> - Update sunxi README in Documentation
> - Add the multiple parents gates and use them for bus-gates instead of
>    ahb1, ahb2, apb1 and apb2 gates
> - Merge the pll8 clock with sun6i pll6
> - Merge the ahb12, apb1 and apb2 resets to bus-resets with own compatible
> - Add sun6i_timer_init to sun8i machine
> - Remove the single SoC names from machine definition, its sun8i family
> - Make the pinctrl driver tristate and put its Kconfig entry in the right order
> - Rename pinctrl "scr" to "sim" and clock "sim" to "scr" to match user manual
> - Remove the address paragraph from GPL in dts and dtsi
> - Some style cleanup and line wrapping in dtsi
> - Add ARM architected timers
> - dmaengine isn't included anymore, it is merged already
>
> Best Regards,
> Jens
>
>
> Jens Kuske (6):
>    clk: sunxi: Let divs clocks read the base factor clock name from
>      devicetree
>    clk: sunxi: Add H3 clocks support
>    pinctrl: sunxi: Add H3 PIO controller support
>    reset: sunxi: Add compatible for Allwinner H3 bus resets
>    ARM: dts: sunxi: Add Allwinner H3 DTSI
>    ARM: dts: sun8i: Add Orange Pi Plus support
>
>   Documentation/devicetree/bindings/clock/sunxi.txt  |   2 +
>   .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
>   .../bindings/reset/allwinner,sunxi-clock-reset.txt |   1 +
>   arch/arm/boot/dts/Makefile                         |   3 +-
>   arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts       |  77 +++
>   arch/arm/boot/dts/sun8i-h3.dtsi                    | 499 ++++++++++++++++++++
>   drivers/clk/sunxi/Makefile                         |   1 +
>   drivers/clk/sunxi/clk-bus-gates.c                  | 105 +++++
>   drivers/clk/sunxi/clk-sunxi.c                      |  47 +-
>   drivers/pinctrl/sunxi/Kconfig                      |   4 +
>   drivers/pinctrl/sunxi/Makefile                     |   1 +
>   drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c           | 516 +++++++++++++++++++++
>   drivers/reset/reset-sunxi.c                        |   1 +
>   13 files changed, 1245 insertions(+), 13 deletions(-)
>   create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
>   create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi
>   create mode 100644 drivers/clk/sunxi/clk-bus-gates.c
>   create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
>

Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Hans de Goede]

Hi,

On 21-10-15 18:13, Jens Kuske wrote:
> Hi everyone,
>
> This is v3 of my patch series introducing basic kernel support for Allwinner's
> H3 SoC. It mainly adds basic clocks and pinctrl. It also adds interrupts,
> timers, watchdog, RTC, dmaengine, MMC and UARTs, which are mostly compatible
> to those in earlier SoCs like A23 and A31, and can simply be reused.
>
> These patches are based on Maxime's sunxi/for-next branch from
> git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git

p.s.

For the next version you will want to base these on the sunxi-next branch of:

https://github.com/linux-sunxi/linux-sunxi.git

There is at least a conflict with the pio driver due to the addition of
the a83 pio driver which mripard/linux/sunxi/for-next does not have, where
as linux-sunxi/sunxi-next does have that merged in.

Regards,

Hans

Re: [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Julian Calaby]

Hi Jens,

On Thu, Oct 22, 2015 at 3:13 AM, Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> The H3 clock control unit is similar to the those of other sun8i family
> members like the A23.
>
> It adds a new bus gates clock similar to the simple gates, but with a
> different parent clock for each single gate.
> Some of the gates use the new AHB2 clock as parent, whose clock source
> is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
> about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
> is mostly based on Allwinner kernel source code.
>
> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
>  drivers/clk/sunxi/Makefile                        |   1 +
>  drivers/clk/sunxi/clk-bus-gates.c                 | 105 ++++++++++++++++++++++
>  drivers/clk/sunxi/clk-sunxi.c                     |  12 ++-
>  4 files changed, 117 insertions(+), 3 deletions(-)
>  create mode 100644 drivers/clk/sunxi/clk-bus-gates.c
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 7c4aee0..6293c65 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c

This hunk should be in patch 1:

> @@ -1000,9 +1005,8 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
>
>                 for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 &&
>                                                 clk_name[i] != '_' &&
> -                                               clk_name[i] != '\0'; i++) {
> +                                               clk_name[i] != '\0'; i++)
>                         base_name[i] = clk_name[i];
> -               }
>
>                 base_name[i] = '\0';
>                 factors.name = base_name;

Thanks,

-- 
Julian Calaby

Email: julian.calaby-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Profile: http://www.google.com/profiles/julian.calaby/

Re: [PATCH 2/6] clk: sunxi: Add H3 clocks support

[Jens Kuske]

On 22/10/15 02:15, Julian Calaby wrote:
> 
> This hunk should be in patch 1:

Indeed, Thanks.

Jens

> 
>> @@ -1000,9 +1005,8 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
>>
>>                 for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 &&
>>                                                 clk_name[i] != '_' &&
>> -                                               clk_name[i] != '\0'; i++) {
>> +                                               clk_name[i] != '\0'; i++)
>>                         base_name[i] = clk_name[i];
>> -               }
>>
>>                 base_name[i] = '\0';
>>                 factors.name = base_name;
> 
> Thanks,
> 

Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Jens Kuske]

Hi,

On 21/10/15 21:18, Hans de Goede wrote:
> 
> Great to see that you've started working on this again. Last weekend I
> ended up working on this too together with Reinder E.N. de Haan <reinder-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org>
> (added to the Cc).
> 
> We took a slightly different approach for the gates clocks, see:
> 
> https://github.com/jwrdegoede/linux-sunxi/commits/sunxi-wip
> 
> And specifically:
> 
> https://github.com/jwrdegoede/linux-sunxi/commit/80a1afe319d5d1a0c426d42e75d37f0c64e8ea0b
> 
> Combined with:
> 
> https://github.com/jwrdegoede/linux-sunxi/commit/d508da5feb5048f6674d6b24b58ac9058fb9d877
> 
> This deals with the per gate parents the same way the rockchip
> clock code does, and it seems to be quite a bit less code then your solution.
> 
> So now we've two solutions to chose from :) Since you seem to be back to
> working on this I'll refrain from doing any further work, at least
> without coordinating. Maxime, can you let us know which solution for the
> gates clock parents is best, or tell us if you think both solutions are
> no good :)

I'd actually prefer your solution. I duplicated the simple-gates code
when trying a different approach and never revisited that decision.

> 
> (I wanted to get in touch with you about the work done this weekend,
> but your posting of this v3 has sorta pre-empted that).
> 
> Other then the slightly different solution for the gates, the code in my tree
> is a straight forward port of your v2.
> 
> Thanks for your work on this!
> 
> Regards,
> 
> Hans
> 
> 
> p.s.
> 
> I'm teaching a kernel driver course at my local hackerspace in the netherlands:
> 
> https://revspace.nl/KernelDriverProgrammingCourse2015
> 
> Which is where our work on this this weekend originated. The next planned
> course day is November 1st and I expect Reinder to be working on the H3
> again then. I think the plan was to tackle USB next. Reinder can you confirm
> this ?  If you (Jens) want to work on USB before then, that is fine, but please
> coordinate their is plenty to do, so no need for us to be doing (more) double
> work.
> 

I don't plan to work on USB soon, my next step would have been Ethernet
and finishing the basic u-boot support. You know my u-boot H3 wip tree I
hope? Before we duplicate our work there too...
https://github.com/jemk/u-boot-sunxi/tree/sunxi/h3

Jens

Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Jean-Francois Moine]

On Wed, 21 Oct 2015 21:18:45 +0200
Hans de Goede <hdegoede@redhat.com> wrote:

> Great to see that you've started working on this again. Last weekend I
> ended up working on this too together with Reinder E.N. de Haan <reinder@mveas.com>
> (added to the Cc).
> 
> We took a slightly different approach for the gates clocks, see:
> 
> https://github.com/jwrdegoede/linux-sunxi/commits/sunxi-wip
> 
> And specifically:
> 
> https://github.com/jwrdegoede/linux-sunxi/commit/80a1afe319d5d1a0c426d42e75d37f0c64e8ea0b
> 
> Combined with:
> 
> https://github.com/jwrdegoede/linux-sunxi/commit/d508da5feb5048f6674d6b24b58ac9058fb9d877
> 
> This deals with the per gate parents the same way the rockchip
> clock code does, and it seems to be quite a bit less code then your solution.

Here is a simpler patch:

diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
index 6ce9118..8fecaeab 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -35,6 +35,7 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
 	void __iomem *reg;
 	const __be32 *p;
 	int number, i = 0, j;
+	bool parent_per_gate;
 	u8 clk_bit;
 	u32 index;
 
@@ -43,6 +44,7 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
 		return;
 
 	clk_parent = of_clk_get_parent_name(node, 0);
+	parent_per_gate = of_clk_get_parent_count(node) != 1;
 
 	clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
 	if (!clk_data)
@@ -58,6 +60,8 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
 	of_property_for_each_u32(node, "clock-indices", prop, p, index) {
 		of_property_read_string_index(node, "clock-output-names",
 					      i, &clk_name);
+		if (parent_per_gate)
+			clk_parent = of_clk_get_parent_name(node, i);
 
 		clk_reg = reg + 4 * (index / 32);
 		clk_bit = index % 32;


-- 
Ken ar c'hentañ	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

Re: Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Hans de Goede]

Hi,

On 22-10-15 09:49, Jens Kuske wrote:
> Hi,
>
> On 21/10/15 21:18, Hans de Goede wrote:
>>
>> Great to see that you've started working on this again. Last weekend I
>> ended up working on this too together with Reinder E.N. de Haan <reinder-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org>
>> (added to the Cc).
>>
>> We took a slightly different approach for the gates clocks, see:
>>
>> https://github.com/jwrdegoede/linux-sunxi/commits/sunxi-wip
>>
>> And specifically:
>>
>> https://github.com/jwrdegoede/linux-sunxi/commit/80a1afe319d5d1a0c426d42e75d37f0c64e8ea0b
>>
>> Combined with:
>>
>> https://github.com/jwrdegoede/linux-sunxi/commit/d508da5feb5048f6674d6b24b58ac9058fb9d877
>>
>> This deals with the per gate parents the same way the rockchip
>> clock code does, and it seems to be quite a bit less code then your solution.
>>
>> So now we've two solutions to chose from :) Since you seem to be back to
>> working on this I'll refrain from doing any further work, at least
>> without coordinating. Maxime, can you let us know which solution for the
>> gates clock parents is best, or tell us if you think both solutions are
>> no good :)
>
> I'd actually prefer your solution. I duplicated the simple-gates code
> when trying a different approach and never revisited that decision.

Ok, note then when you switch to my solution (or the improved version of it
or the improved version Jean-Francois Moine suggests) the dtsi now has a list
of clocks with one per gate, rather then clock indices. You can save yourself
some time by taking that list from the dtsi patch in my tree, rather then
building it yourself manually.

>> (I wanted to get in touch with you about the work done this weekend,
>> but your posting of this v3 has sorta pre-empted that).
>>
>> Other then the slightly different solution for the gates, the code in my tree
>> is a straight forward port of your v2.
>>
>> Thanks for your work on this!
>>
>> Regards,
>>
>> Hans
>>
>>
>> p.s.
>>
>> I'm teaching a kernel driver course at my local hackerspace in the netherlands:
>>
>> https://revspace.nl/KernelDriverProgrammingCourse2015
>>
>> Which is where our work on this this weekend originated. The next planned
>> course day is November 1st and I expect Reinder to be working on the H3
>> again then. I think the plan was to tackle USB next. Reinder can you confirm
>> this ?  If you (Jens) want to work on USB before then, that is fine, but please
>> coordinate their is plenty to do, so no need for us to be doing (more) double
>> work.
>>
>
> I don't plan to work on USB soon, my next step would have been Ethernet
> and finishing the basic u-boot support. You know my u-boot H3 wip tree I
> hope? Before we duplicate our work there too...
> https://github.com/jemk/u-boot-sunxi/tree/sunxi/h3

I was not aware of that work, at a first glance it looks good. Can you rebase
this on top of current u-boot/master (or v2015.10) and then submit it upstream ?

2 questions which come to mind immediately:

1) Where does the dram init logic come from, AFAIK Allwinner has not provided
any H3 dram init code ?

2) I see no pmic code in there. I know these boards do not use an axp pmic,
but according to my info at least the Orange Pi 2 (which I have) uses a
sy8106a pmic, it is not entirely clear to me yet if this one needs any
init though, I've mailed the Orange Pi people about this.

Regards,

Hans

Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Hans de Goede]

Hi,

On 22-10-15 09:58, Jean-Francois Moine wrote:
> On Wed, 21 Oct 2015 21:18:45 +0200
> Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
>
>> Great to see that you've started working on this again. Last weekend I
>> ended up working on this too together with Reinder E.N. de Haan <reinder-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org>
>> (added to the Cc).
>>
>> We took a slightly different approach for the gates clocks, see:
>>
>> https://github.com/jwrdegoede/linux-sunxi/commits/sunxi-wip
>>
>> And specifically:
>>
>> https://github.com/jwrdegoede/linux-sunxi/commit/80a1afe319d5d1a0c426d42e75d37f0c64e8ea0b
>>
>> Combined with:
>>
>> https://github.com/jwrdegoede/linux-sunxi/commit/d508da5feb5048f6674d6b24b58ac9058fb9d877
>>
>> This deals with the per gate parents the same way the rockchip
>> clock code does, and it seems to be quite a bit less code then your solution.
>
> Here is a simpler patch:
>
> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> index 6ce9118..8fecaeab 100644
> --- a/drivers/clk/sunxi/clk-simple-gates.c
> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> @@ -35,6 +35,7 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
>   	void __iomem *reg;
>   	const __be32 *p;
>   	int number, i = 0, j;
> +	bool parent_per_gate;
>   	u8 clk_bit;
>   	u32 index;
>
> @@ -43,6 +44,7 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
>   		return;
>
>   	clk_parent = of_clk_get_parent_name(node, 0);
> +	parent_per_gate = of_clk_get_parent_count(node) != 1;
>
>   	clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
>   	if (!clk_data)
> @@ -58,6 +60,8 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
>   	of_property_for_each_u32(node, "clock-indices", prop, p, index) {
>   		of_property_read_string_index(node, "clock-output-names",
>   					      i, &clk_name);
> +		if (parent_per_gate)
> +			clk_parent = of_clk_get_parent_name(node, i);
>
>   		clk_reg = reg + 4 * (index / 32);
>   		clk_bit = index % 32;
>
>

Yes good one, doing things that way indeed is better.

Regards,

Hans

Re: Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Peter Korsgaard]

>>>>> "Hans" == Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> writes:

Hi,

 > 2) I see no pmic code in there. I know these boards do not use an axp pmic,
 > but according to my info at least the Orange Pi 2 (which I have) uses a
 > sy8106a pmic, it is not entirely clear to me yet if this one needs any
 > init though, I've mailed the Orange Pi people about this.

Did you hear back from them? I haven't been able to find any datasheet
describing the i2c interface, but the orange pi pc schematics has a note
that Vout is defined by the Ru1 / Ru2 resistors, so it sounds like i2c
configuration isn't critical to get something running.

-- 
Bye, Peter Korsgaard

Re: Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

[Mihail Tommonen]

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I have a feeling that sy8106a could be related to Silergy other pmics. 
Maybe something custom made, with special voltage, i2c address etc.

http://lists.infradead.org/pipermail/linux-rockchip/2014-September/000249.html

-Miskab

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SY8106 datasheet.

[zhao_steven]

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Dear all,
     SY8106 datasheet. 

steven
 
From: Peter Korsgaard
Date: 2015-10-28 03:24
To: Hans de Goede
CC: Jens Kuske; Maxime Ripard; Chen-Yu Tsai; Linus Walleij; Rob Herring; Philipp Zabel; EmilioLópez; Vishnu Patekar; devicetree; linux-arm-kernel; linux-kernel; linux-sunxi; Reinder E.N. de Haan; zhao_steven
Subject: Re: [linux-sunxi] Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support
>>>>> "Hans" == Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> writes:
 
Hi,
 
> 2) I see no pmic code in there. I know these boards do not use an axp pmic,
> but according to my info at least the Orange Pi 2 (which I have) uses a
> sy8106a pmic, it is not entirely clear to me yet if this one needs any
> init though, I've mailed the Orange Pi people about this.
 
Did you hear back from them? I haven't been able to find any datasheet
describing the i2c interface, but the orange pi pc schematics has a note
that Vout is defined by the Ru1 / Ru2 resistors, so it sounds like i2c
configuration isn't critical to get something running.
 
-- 
Bye, Peter Korsgaard
 
 

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