[PATCH 0/7] Add basic SMP support for Amlogic Meson8b

[PATCH 0/7] Add basic SMP support for Amlogic Meson8b

[Carlo Caione]

From: Carlo Caione <carlo@endlessm.com>

This patchset adds SMP support for Amlogic Meson8b SoCs.

Patch 1 fix some paramater for L2 cache needed for SMP.
Patches 2-4 add a small reset controller used to reset the CPU cores at boot.
Patches 5-7 deal with the SMP code itself.

Carlo Caione (7):
  ARM: DTS: meson8b: Extend L2 cache controller node
  Documentation: bindings: Define CPU reset controller
  clk: meson8b: Add reset controller for CPU cores
  ARM: DTS: meson8b: Enable reset controller
  Documentation: bindings: Add SMP related documentation
  ARM: meson8b: Add SMP bringup code
  ARM: DTS: meson8b: Add SMP related nodes

 .../devicetree/bindings/arm/amlogic/pmu.txt        |  16 ++
 .../devicetree/bindings/arm/amlogic/smp-sram.txt   |  32 +++
 .../arm/cpu-enable-method/amlogic,meson8b-smp      |  53 +++++
 .../bindings/clock/amlogic,meson8b-clkc.txt        |   6 +-
 arch/arm/boot/dts/meson8b.dtsi                     |  32 +++
 arch/arm/mach-meson/Kconfig                        |   1 +
 arch/arm/mach-meson/Makefile                       |   1 +
 arch/arm/mach-meson/platsmp.c                      | 228 +++++++++++++++++++++
 drivers/clk/meson/clk-cpu.c                        |  60 +++++-
 drivers/clk/meson/clkc.c                           |   5 +-
 drivers/clk/meson/clkc.h                           |   6 +-
 drivers/clk/meson/meson8b-clkc.c                   |   4 +-
 include/dt-bindings/clock/meson8b-clkc.h           |   5 +
 13 files changed, 441 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
 create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp
 create mode 100644 arch/arm/mach-meson/platsmp.c

-- 
2.5.0

[PATCH 1/7] ARM: DTS: meson8b: Extend L2 cache controller node

[Carlo Caione]

From: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>

This patch extends the L2 cache controller node for Amlogic Meson8b
SoCs with some missing parameters.

Signed-off-by: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/meson8b.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 8bad557..745f0f9 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -93,6 +93,9 @@
 		L2: l2-cache-controller@c4200000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xc4200000 0x1000>;
+			arm,data-latency = <3 3 3>;
+			arm,tag-latency = <2 2 2>;
+			arm,filter-ranges = <0x100000 0xc0000000>;
 			cache-unified;
 			cache-level = <2>;
 		};
-- 
2.5.0

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 2/7] Documentation: bindings: Define CPU reset controller

[Carlo Caione]

From: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>

The clock controller on Amlogic Meson8b SoCs has been extended with a
reset controller used to reset the CPU cores. It is used during SMP
bringup.

With this patch we extend the clock controller documentation.

Signed-off-by: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
---
 Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
index 2b7b3fa..feeb4de 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
@@ -1,7 +1,8 @@
 * Amlogic Meson8b Clock and Reset Unit
 
 The Amlogic Meson8b clock controller generates and supplies clock to various
-controllers within the SoC.
+controllers within the SoC and also implements a reset controller for the CPU
+cores.
 
 Required Properties:
 
@@ -13,16 +14,19 @@ Required Properties:
 	   mapped region.
 
 - #clock-cells: should be 1.
+- #reset-cells: should be 1.
 
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
 used in device tree sources.
+Similar identifiers exist for the CPU core reset lines.
 
 Example: Clock controller node:
 
 	clkc: clock-controller@c1104000 {
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 		compatible = "amlogic,meson8b-clkc";
 		reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
 	};
-- 
2.5.0

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 3/7] clk: meson8b: Add reset controller for CPU cores

[Carlo Caione]

From: Carlo Caione <carlo@endlessm.com>

In the Amlogic Meson8b SoC we need to soft reset the CPU cores during
the boot to enable the SMP support. With this patch we extend the clock
controller adding a small reset controller in charge of resetting the
cores.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
---
 drivers/clk/meson/clk-cpu.c              | 60 +++++++++++++++++++++++++++++++-
 drivers/clk/meson/clkc.c                 |  5 +--
 drivers/clk/meson/clkc.h                 |  6 ++--
 drivers/clk/meson/meson8b-clkc.c         |  4 +--
 include/dt-bindings/clock/meson8b-clkc.h |  5 +++
 5 files changed, 73 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/meson/clk-cpu.c b/drivers/clk/meson/clk-cpu.c
index f7c30ea..8836fa9 100644
--- a/drivers/clk/meson/clk-cpu.c
+++ b/drivers/clk/meson/clk-cpu.c
@@ -37,9 +37,14 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
+#include <linux/reset.h>
+#include <linux/reset-controller.h>
 
 #define MESON_CPU_CLK_CNTL1		0x00
 #define MESON_CPU_CLK_CNTL		0x40
+#define MESON_CPU_CLK_CNTL_CPU		0x19c
+
+#define MESON_MAX_CPU_RST		4
 
 #define MESON_CPU_CLK_MUX1		BIT(7)
 #define MESON_CPU_CLK_MUX2		BIT(0)
@@ -51,6 +56,11 @@
 
 #include "clkc.h"
 
+struct meson_reset_cpu {
+	void __iomem			*reset_base;
+	struct reset_controller_dev	rcdev;
+};
+
 struct meson_clk_cpu {
 	struct notifier_block		clk_nb;
 	const struct clk_div_table	*div_table;
@@ -182,13 +192,50 @@ static const struct clk_ops meson_clk_cpu_ops = {
 	.set_rate	= meson_clk_cpu_set_rate,
 };
 
-struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf,
+static int meson_reset_cpu_assert(struct reset_controller_dev *rcdev,
+				  unsigned long id)
+{
+	u32 reg;
+	struct meson_reset_cpu *reset_cpu = container_of(rcdev,
+							 struct meson_reset_cpu,
+							 rcdev);
+
+	reg = readl(reset_cpu->reset_base);
+	reg |= BIT(id + 24);
+	writel(reg, reset_cpu->reset_base);
+
+	return 0;
+}
+
+static int meson_reset_cpu_deassert(struct reset_controller_dev *rcdev,
+				    unsigned long id)
+{
+	u32 reg;
+	struct meson_reset_cpu *reset_cpu = container_of(rcdev,
+							 struct meson_reset_cpu,
+							 rcdev);
+
+	reg = readl(reset_cpu->reset_base);
+	reg &= ~BIT(id + 24);
+	writel(reg, reset_cpu->reset_base);
+
+	return 0;
+}
+
+static struct reset_control_ops meson_cpu_reset_ops = {
+	.assert		= meson_reset_cpu_assert,
+	.deassert	= meson_reset_cpu_deassert,
+};
+
+struct clk *meson_clk_register_cpu(struct device_node *np,
+				   const struct clk_conf *clk_conf,
 				   void __iomem *reg_base,
 				   spinlock_t *lock)
 {
 	struct clk *clk;
 	struct clk *pclk;
 	struct meson_clk_cpu *clk_cpu;
+	struct meson_reset_cpu *reset_cpu;
 	struct clk_init_data init;
 	int ret;
 
@@ -231,6 +278,17 @@ struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf,
 		goto unregister_clk_nb;
 	}
 
+	reset_cpu = kzalloc(sizeof(*reset_cpu), GFP_KERNEL);
+	if (!reset_cpu)
+		goto out;
+
+	reset_cpu->reset_base = reg_base + MESON_CPU_CLK_CNTL_CPU;
+	reset_cpu->rcdev.nr_resets = MESON_MAX_CPU_RST;
+	reset_cpu->rcdev.ops = &meson_cpu_reset_ops;
+	reset_cpu->rcdev.of_node = np;
+	reset_controller_register(&reset_cpu->rcdev);
+
+out:
 	return clk;
 
 unregister_clk_nb:
diff --git a/drivers/clk/meson/clkc.c b/drivers/clk/meson/clkc.c
index c83ae13..df71e82 100644
--- a/drivers/clk/meson/clkc.c
+++ b/drivers/clk/meson/clkc.c
@@ -197,7 +197,8 @@ meson_clk_register_fixed_rate(const struct clk_conf *clk_conf,
 	return clk;
 }
 
-void __init meson_clk_register_clks(const struct clk_conf *clk_confs,
+void __init meson_clk_register_clks(struct device_node *np,
+				    const struct clk_conf *clk_confs,
 				    size_t nr_confs,
 				    void __iomem *clk_base)
 {
@@ -221,7 +222,7 @@ void __init meson_clk_register_clks(const struct clk_conf *clk_confs,
 							   clk_base);
 			break;
 		case CLK_CPU:
-			clk = meson_clk_register_cpu(clk_conf, clk_base,
+			clk = meson_clk_register_cpu(np, clk_conf, clk_base,
 						     &clk_lock);
 			break;
 		case CLK_PLL:
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 609ae92..648d41d 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -177,9 +177,11 @@ struct clk_conf {
 	}								\
 
 struct clk **meson_clk_init(struct device_node *np, unsigned long nr_clks);
-void meson_clk_register_clks(const struct clk_conf *clk_confs,
+void meson_clk_register_clks(struct device_node *np,
+			     const struct clk_conf *clk_confs,
 			     unsigned int nr_confs, void __iomem *clk_base);
-struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf,
+struct clk *meson_clk_register_cpu(struct device_node *np,
+				   const struct clk_conf *clk_conf,
 				   void __iomem *reg_base, spinlock_t *lock);
 struct clk *meson_clk_register_pll(const struct clk_conf *clk_conf,
 				   void __iomem *reg_base, spinlock_t *lock);
diff --git a/drivers/clk/meson/meson8b-clkc.c b/drivers/clk/meson/meson8b-clkc.c
index 61f6d55..98f1ebd 100644
--- a/drivers/clk/meson/meson8b-clkc.c
+++ b/drivers/clk/meson/meson8b-clkc.c
@@ -179,7 +179,7 @@ static void __init meson8b_clkc_init(struct device_node *np)
 		return;
 	}
 
-	meson_clk_register_clks(&meson8b_xtal_conf, 1, clk_base);
+	meson_clk_register_clks(np, &meson8b_xtal_conf, 1, clk_base);
 	iounmap(clk_base);
 
 	/*  Generic clocks and PLLs */
@@ -189,7 +189,7 @@ static void __init meson8b_clkc_init(struct device_node *np)
 		return;
 	}
 
-	meson_clk_register_clks(meson8b_clk_confs,
+	meson_clk_register_clks(np, meson8b_clk_confs,
 				ARRAY_SIZE(meson8b_clk_confs),
 				clk_base);
 }
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index bd2720d..bbdadca 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -5,6 +5,11 @@
 #ifndef __MESON8B_CLKC_H
 #define __MESON8B_CLKC_H
 
+#define RST_CORE0		0
+#define RST_CORE1		1
+#define RST_CORE2		2
+#define RST_CORE3		3
+
 #define CLKID_UNUSED		0
 #define CLKID_XTAL		1
 #define CLKID_PLL_FIXED		2
-- 
2.5.0

[PATCH 4/7] ARM: DTS: meson8b: Enable reset controller

[Carlo Caione]

From: Carlo Caione <carlo@endlessm.com>

Extend the CPU nodes to use the reset controller.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 745f0f9..977d55f 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -60,6 +60,7 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x200>;
+			resets = <&clkc RST_CORE0>;
 		};
 
 		cpu@201 {
@@ -67,6 +68,7 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x201>;
+			resets = <&clkc RST_CORE1>;
 		};
 
 		cpu@202 {
@@ -74,6 +76,7 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x202>;
+			resets = <&clkc RST_CORE2>;
 		};
 
 		cpu@203 {
@@ -81,6 +84,7 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x203>;
+			resets = <&clkc RST_CORE3>;
 		};
 	};
 
@@ -153,6 +157,7 @@
 		};
 
 		clkc: clock-controller@c1104000 {
+			#reset-cells = <1>;
 			#clock-cells = <1>;
 			compatible = "amlogic,meson8b-clkc";
 			reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
-- 
2.5.0

[PATCH 5/7] Documentation: bindings: Add SMP related documentation

[Carlo Caione]

From: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>

With this patch we add documentation for:

* power-management-unit: the PMU is used to bring up the cores during
  SMP operations
* sram: among other things the sram is used to store the first code
  executed by the core when it is powered up
* cpu-enable-method: the CPU enable method used by Amlogic Meson8b SoCs

Signed-off-by: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
---
 .../devicetree/bindings/arm/amlogic/pmu.txt        | 16 +++++++
 .../devicetree/bindings/arm/amlogic/smp-sram.txt   | 32 +++++++++++++
 .../arm/cpu-enable-method/amlogic,meson8b-smp      | 53 ++++++++++++++++++++++
 3 files changed, 101 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
 create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp

diff --git a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt
new file mode 100644
index 0000000..7b9b2da
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt
@@ -0,0 +1,16 @@
+Amlogic power-management-unit:
+-------------------------------
+
+The pmu is used to turn off and on different power domains of the SoCs
+This includes the power to the CPU cores.
+
+Required node properties:
+- compatible value : = "amlogic,meson8b-pmu";
+- reg : physical base address and the size of the registers window
+
+Example:
+
+	pmu@c81000e4 {
+		compatible = "amlogic,meson8b-pmu", "syscon";
+		reg = <0xc81000e0 0x18>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
new file mode 100644
index 0000000..455ca20
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
@@ -0,0 +1,32 @@
+Amlogic SRAM for smp bringup:
+------------------------------
+
+Amlogic's smp-capable SoCs use part of the sram for the bringup of the cores.
+Once the core gets powered up it executes the code that is residing at a
+specific location.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Required sub-node properties:
+- compatible : should be "amlogic,meson8b-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+	sram: sram@d9000000 {
+		compatible = "mmio-sram";
+		reg = <0xd9000000 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xd9000000 0x20000>;
+
+		smp-sram@1ff80 {
+			compatible = "amlogic,meson8b-smp-sram";
+			reg = <0x1ff80 0x8>;
+		};
+	};
+
+
diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp
new file mode 100644
index 0000000..95ee458b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp
@@ -0,0 +1,53 @@
+=========================================================
+Secondary CPU enable-method "amlogic,meson8b-smp" binding
+=========================================================
+
+This document describes the "amlogic,meson8b-smp" method for enabling secondary
+CPUs. To apply to all CPUs, a single "amlogic,meson8b-smp" enable method should
+be defined in the "cpus" node.
+
+Enable method name:	"amlogic,meson8b-smp"
+Compatible machines:	"amlogic,meson8b"
+Compatible CPUs:	"arm,cortex-a5"
+Related properties:	(none)
+
+Example:
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "amlogic,meson8b-smp";
+
+		cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a5";
+			next-level-cache = <&L2>;
+			reg = <0x200>;
+			resets = <&clkc RST_CORE0>;
+		};
+
+		cpu@201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a5";
+			next-level-cache = <&L2>;
+			reg = <0x201>;
+			resets = <&clkc RST_CORE1>;
+		};
+
+		cpu@202 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a5";
+			next-level-cache = <&L2>;
+			reg = <0x202>;
+			resets = <&clkc RST_CORE2>;
+		};
+
+		cpu@203 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a5";
+			next-level-cache = <&L2>;
+			reg = <0x203>;
+			resets = <&clkc RST_CORE3>;
+		};
+	};
+
-- 
2.5.0

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 6/7] ARM: meson8b: Add SMP bringup code

[Carlo Caione]

From: Carlo Caione <carlo@endlessm.com>

This adds the necessary SMP-operations and startup code to use the
additional cores on the Amlogic Meson8b SoCs.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
---
 arch/arm/mach-meson/Kconfig   |   1 +
 arch/arm/mach-meson/Makefile  |   1 +
 arch/arm/mach-meson/platsmp.c | 228 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 230 insertions(+)
 create mode 100644 arch/arm/mach-meson/platsmp.c

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 5d56f86..e171744 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -6,6 +6,7 @@ menuconfig ARCH_MESON
 	select CACHE_L2X0
 	select PINCTRL
 	select PINCTRL_MESON
+	select HAVE_ARM_SCU if SMP
 
 if ARCH_MESON
 
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index 9d7380e..bc26c85 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_MESON) += meson.o
+obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c
new file mode 100644
index 0000000..37c9102
--- /dev/null
+++ b/arch/arm/mach-meson/platsmp.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (C) 2015 Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/smp.h>
+#include <linux/mfd/syscon.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+
+#define MESON_CPU_CTRL_REG			(0x00)
+#define MESON_CPU_CTRL_ADDR_REG(c)		(0x04 + ((c - 1) << 2))
+
+#define MESON_CPU_AO_RTI_PWR_A9_CNTL0		(0x00)
+#define MESON_CPU_AO_RTI_PWR_A9_CNTL1		(0x04)
+#define MESON_CPU_AO_RTI_PWR_A9_MEM_PD0		(0x14)
+
+#define MESON_CPU_PWR_A9_CNTL0_M(c)		(0x03 << ((c * 2) + 16))
+#define MESON_CPU_PWR_A9_CNTL1_M(c)		(0x03 << ((c + 1) << 1))
+#define MESON_CPU_PWR_A9_MEM_PD0_M(c)		(0x0f << (32 - (c * 4)))
+#define MESON_CPU_PWR_A9_CNTL1_ST(c)		(0x01 << (c + 16))
+
+static void __iomem *sram_base;
+static void __iomem *scu_base;
+static struct regmap *pmu;
+
+static void __init meson8b_smp_prepare_cpus(unsigned int max_cpus)
+{
+	static struct device_node *node;
+
+	/* SMP SRAM */
+	node = of_find_compatible_node(NULL, NULL, "amlogic,meson8b-smp-sram");
+	if (!node) {
+		pr_err("Missing SRAM node\n");
+		return;
+	}
+
+	sram_base = of_iomap(node, 0);
+	if (!sram_base) {
+		pr_err("Couldn't map SRAM registers\n");
+		return;
+	}
+
+	/* PMU */
+	pmu = syscon_regmap_lookup_by_compatible("amlogic,meson8b-pmu");
+	if (IS_ERR(pmu)) {
+		pr_err("Couldn't map PMU registors\n");
+		return;
+	}
+
+	/* SCU */
+	node = of_find_compatible_node(NULL, NULL, "arm,cortex-a5-scu");
+	if (!node) {
+		pr_err("Missing SCU node\n");
+		return;
+	}
+
+	scu_base = of_iomap(node, 0);
+	if (!scu_base) {
+		pr_err("Couln't map SCU registers\n");
+		return;
+	}
+
+	scu_enable(scu_base);
+}
+
+static struct reset_control *meson_get_core_reset(int cpu)
+{
+	struct device_node *np;
+
+	np = of_get_cpu_node(cpu, 0);
+
+	return of_reset_control_get(np, NULL);
+}
+
+static int meson8b_set_cpu_power_ctrl(unsigned int cpu, bool is_power_on)
+{
+	struct reset_control *rstc = meson_get_core_reset(cpu);
+	int ret;
+	u32 val;
+
+	if (is_power_on) {
+
+		/* CPU power UP */
+		ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
+					 MESON_CPU_PWR_A9_CNTL0_M(cpu), 0);
+		if (ret < 0) {
+			pr_err("Couldn't power up the CPU\n");
+			return ret;
+		}
+
+		udelay(5);
+
+		/* Reset enable */
+		reset_control_assert(rstc);
+
+		/* Memory power UP */
+		ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
+					 MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0);
+		if (ret < 0) {
+			pr_err("Couldn't power up the memory\n");
+			return ret;
+		}
+
+		/* Wake up CPU */
+		ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
+					 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
+		if (ret < 0) {
+			pr_err("Couldn't wake up the CPU\n");
+			return ret;
+		}
+
+		udelay(10);
+
+		val = 0;
+		while (!(val & MESON_CPU_PWR_A9_CNTL1_ST(cpu))) {
+			ret = regmap_read(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, &val);
+			if (ret < 0) {
+				pr_err("CPU wake up failed\n");
+				return ret;
+			}
+		}
+
+		/* Isolation disable */
+		ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
+					 BIT(cpu), 0);
+		if (ret < 0) {
+			pr_err("Error when disabling isolation\n");
+			return ret;
+		}
+
+		/* Reset disable */
+		reset_control_deassert(rstc);
+
+	} else {
+
+		/* CPU power DOWN */
+		ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
+					 MESON_CPU_PWR_A9_CNTL0_M(cpu), 0x3);
+		if (ret < 0) {
+			pr_err("Couldn't power down the CPU\n");
+			return ret;
+		}
+
+		/* Isolation enable */
+		ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
+					 BIT(cpu), 0x3);
+		if (ret < 0) {
+			pr_err("Error when enabling isolation\n");
+			return ret;
+		}
+
+		udelay(10);
+
+		/* Sleep status */
+		ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
+					 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
+		if (ret < 0) {
+			pr_err("Couldn't change sleep status\n");
+			return ret;
+		}
+
+		/* Memory power DOWN */
+		ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
+					 MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0xf);
+		if (ret < 0) {
+			pr_err("Couldn't power down the memory\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int meson8b_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+	int ret;
+	u32 reg;
+
+	ret = meson8b_set_cpu_power_ctrl(cpu, 1);
+	if (ret < 0)
+		return ret;
+
+	timeout = jiffies + (10 * HZ);
+	while (readl(sram_base + MESON_CPU_CTRL_ADDR_REG(cpu)))
+		if (!time_before(jiffies, timeout))
+			return -EPERM;
+
+	udelay(100);
+	writel(virt_to_phys(secondary_startup), sram_base + MESON_CPU_CTRL_ADDR_REG(cpu));
+
+	reg = readl(sram_base + MESON_CPU_CTRL_REG);
+	reg |= (BIT(cpu) | BIT(0));
+	writel(reg, sram_base + MESON_CPU_CTRL_REG);
+
+	return 0;
+}
+
+static void meson8b_smp_secondary_init(unsigned int cpu)
+{
+	scu_power_mode(scu_base, SCU_PM_NORMAL);
+}
+
+static struct smp_operations meson8b_smp_ops __initdata = {
+	.smp_prepare_cpus	= meson8b_smp_prepare_cpus,
+	.smp_boot_secondary	= meson8b_smp_boot_secondary,
+	.smp_secondary_init	= meson8b_smp_secondary_init,
+};
+
+CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops);
-- 
2.5.0

[PATCH 7/7] ARM: DTS: meson8b: Add SMP related nodes

[Carlo Caione]

From: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>

Add nodes for: SCU, PMU and SRAM. Set also the enable-method for SMP
bringup.

Signed-off-by: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/meson8b.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 977d55f..0477a81 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -51,9 +51,20 @@
 / {
 	interrupt-parent = <&gic>;
 
+	scu@c4300000 {
+		compatible = "arm,cortex-a5-scu";
+		reg = <0xc4300000 0x100>;
+	};
+
+	pmu@c81000e4 {
+		compatible = "amlogic,meson8b-pmu", "syscon";
+		reg = <0xc81000e0 0x18>;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "amlogic,meson8b-smp";
 
 		cpu@200 {
 			device_type = "cpu";
@@ -88,6 +99,19 @@
 		};
 	};
 
+	sram: sram@d9000000 {
+		compatible = "mmio-sram";
+		reg = <0xd9000000 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xd9000000 0x20000>;
+
+		smp-sram@1ff80 {
+			compatible = "amlogic,meson8b-smp-sram";
+			reg = <0x1ff80 0x8>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
-- 
2.5.0

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 5/7] Documentation: bindings: Add SMP related documentation

[Rob Herring]

On Tue, Nov 17, 2015 at 03:56:40PM +0100, Carlo Caione wrote:
> From: Carlo Caione <carlo@endlessm.com>

Please give some indication in the subject what platform this change is 
for:

dt-bindings: amlogic: ...

> 
> With this patch we add documentation for:
> 
> * power-management-unit: the PMU is used to bring up the cores during
>   SMP operations
> * sram: among other things the sram is used to store the first code
>   executed by the core when it is powered up
> * cpu-enable-method: the CPU enable method used by Amlogic Meson8b SoCs
> 
> Signed-off-by: Carlo Caione <carlo@endlessm.com>
> ---
>  .../devicetree/bindings/arm/amlogic/pmu.txt        | 16 +++++++
>  .../devicetree/bindings/arm/amlogic/smp-sram.txt   | 32 +++++++++++++
>  .../arm/cpu-enable-method/amlogic,meson8b-smp      | 53 ++++++++++++++++++++++


> diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp
> new file mode 100644
> index 0000000..95ee458b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/amlogic,meson8b-smp
> @@ -0,0 +1,53 @@
> +=========================================================
> +Secondary CPU enable-method "amlogic,meson8b-smp" binding
> +=========================================================
> +
> +This document describes the "amlogic,meson8b-smp" method for enabling secondary
> +CPUs. To apply to all CPUs, a single "amlogic,meson8b-smp" enable method should
> +be defined in the "cpus" node.
> +
> +Enable method name:	"amlogic,meson8b-smp"

Just add this to Documentation/devicetree/bindings/arm/cpus.txt and 
remove this file.

> +Compatible machines:	"amlogic,meson8b"
> +Compatible CPUs:	"arm,cortex-a5"
> +Related properties:	(none)
> +
> +Example:
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		enable-method = "amlogic,meson8b-smp";
> +
> +		cpu@200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a5";
> +			next-level-cache = <&L2>;
> +			reg = <0x200>;
> +			resets = <&clkc RST_CORE0>;
> +		};
> +
> +		cpu@201 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a5";
> +			next-level-cache = <&L2>;
> +			reg = <0x201>;
> +			resets = <&clkc RST_CORE1>;
> +		};
> +
> +		cpu@202 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a5";
> +			next-level-cache = <&L2>;
> +			reg = <0x202>;
> +			resets = <&clkc RST_CORE2>;
> +		};
> +
> +		cpu@203 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a5";
> +			next-level-cache = <&L2>;
> +			reg = <0x203>;
> +			resets = <&clkc RST_CORE3>;
> +		};
> +	};
> +
> -- 
> 2.5.0
> 

Re: [PATCH 2/7] Documentation: bindings: Define CPU reset controller

[Rob Herring]

On Tue, Nov 17, 2015 at 03:56:37PM +0100, Carlo Caione wrote:
> From: Carlo Caione <carlo@endlessm.com>

Same here, a more specific subject please.

Otherwise, looks fine.

> 
> The clock controller on Amlogic Meson8b SoCs has been extended with a
> reset controller used to reset the CPU cores. It is used during SMP
> bringup.
> 
> With this patch we extend the clock controller documentation.
> 
> Signed-off-by: Carlo Caione <carlo@endlessm.com>
> ---
>  Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> index 2b7b3fa..feeb4de 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> @@ -1,7 +1,8 @@
>  * Amlogic Meson8b Clock and Reset Unit
>  
>  The Amlogic Meson8b clock controller generates and supplies clock to various
> -controllers within the SoC.
> +controllers within the SoC and also implements a reset controller for the CPU
> +cores.
>  
>  Required Properties:
>  
> @@ -13,16 +14,19 @@ Required Properties:
>  	   mapped region.
>  
>  - #clock-cells: should be 1.
> +- #reset-cells: should be 1.
>  
>  Each clock is assigned an identifier and client nodes can use this identifier
>  to specify the clock which they consume. All available clocks are defined as
>  preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
>  used in device tree sources.
> +Similar identifiers exist for the CPU core reset lines.
>  
>  Example: Clock controller node:
>  
>  	clkc: clock-controller@c1104000 {
>  		#clock-cells = <1>;
> +		#reset-cells = <1>;
>  		compatible = "amlogic,meson8b-clkc";
>  		reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
>  	};
> -- 
> 2.5.0
>