From mboxrd@z Thu Jan 1 00:00:00 1970 From: Geert Uytterhoeven Subject: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support Date: Thu, 19 Nov 2015 19:38:41 +0100 Message-ID: <1447958344-836-3-git-send-email-geert+renesas@glider.be> References: <1447958344-836-1-git-send-email-geert+renesas@glider.be> Return-path: In-Reply-To: <1447958344-836-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Greg Kroah-Hartman , Simon Horman , Magnus Damm , Yoshinori Sato , Laurent Pinchart Cc: linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sh-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Geert Uytterhoeven , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org Amend the DT bindings to include the optional clock sources for the Baud Rate Generator for External Clock (BRG), as found on some SCIF variants and on HSCIF. Signed-off-by: Geert Uytterhoeven Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 8efc9b6f35637fbb..ae907e39b11c2a5a 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -46,6 +46,12 @@ Required properties: On (H)SCI(F) and some SCIFA, an additional clock may be specified: - "hsck" for the optional external clock input (on HSCIF), - "sck" for the optional external clock input (on other variants). + On UARTs equipped with a Baud Rate Generator for External Clock (BRG) + (some SCIF and HSCIF), additional clocks may be specified: + - "int_clk" for the optional internal clock source for the frequency + divider (typically the (AXI or SHwy) bus clock), + - "scif_clk" for the optional external clock source for the frequency + divider (SCIF_CLK). Note: Each enabled SCIx UART should have an alias correctly numbered in the "aliases" node. -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html