From: Jisheng Zhang <jszhang@marvell.com>
To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
catalin.marinas@arm.com, will.deacon@arm.com,
mturquette@baylibre.com, sboyd@codeaurora.org,
sebastian.hesselbarth@gmail.com,
antoine.tenart@free-electrons.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
Jisheng Zhang <jszhang@marvell.com>
Subject: [PATCH v2 0/6] Add Marvell berlin4ct clk support
Date: Fri, 20 Nov 2015 16:42:26 +0800 [thread overview]
Message-ID: <1448008952-1787-1-git-send-email-jszhang@marvell.com> (raw)
Add berlin4ct clk driver. The berlin4ct SoC contains:
two kinds of PLL: normal PLL and AVPLL. The normal PLL support is done.
The AVPLL support is in TODO list.
two kinds of clk: normal clk and gate clk. The normal clk supports changing
divider, selecting clock source, disabling/enabling etc. The gate clk only
supports disabling/enabling. Both are supported in this series.
Since v1:
- rebased on v4.4-rc1
- refactor out common code from clk-berlin4ct.c
- s/lock/berlin4ct_gateclk_lock
- drop WARN_ON for an allocation failure
- s/kzalloc/kcalloc
- add necessary handling in error code path, such as free memory, iounmap etc.
- initialize init.flags
- drop vcodiv_berlin[] array
Jisheng Zhang (6):
clk: berlin: add common pll driver
clk: berlin: add common clk driver for newer SoCs
clk: berlin: add common gateclk driver for newer SoCs
clk: berlin: add clk support for berlin4ct
dt-bindings: add binding for marvell berlin4ct SoC
arm64: dts: berlin4ct: add pll and clock nodes
.../bindings/clock/marvell,berlin4ct.txt | 38 ++++
arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++
drivers/clk/berlin/Makefile | 1 +
drivers/clk/berlin/clk-berlin4ct.c | 97 ++++++++++
drivers/clk/berlin/clk.c | 203 +++++++++++++++++++++
drivers/clk/berlin/clk.h | 45 +++++
drivers/clk/berlin/gate.c | 73 ++++++++
drivers/clk/berlin/pll.c | 133 ++++++++++++++
include/dt-bindings/clock/berlin4ct.h | 56 ++++++
9 files changed, 684 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/marvell,berlin4ct.txt
create mode 100644 drivers/clk/berlin/clk-berlin4ct.c
create mode 100644 drivers/clk/berlin/clk.c
create mode 100644 drivers/clk/berlin/clk.h
create mode 100644 drivers/clk/berlin/gate.c
create mode 100644 drivers/clk/berlin/pll.c
create mode 100644 include/dt-bindings/clock/berlin4ct.h
--
2.6.2
next reply other threads:[~2015-11-20 8:42 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-20 8:42 Jisheng Zhang [this message]
2015-11-20 8:42 ` [PATCH v2 1/6] clk: berlin: add common pll driver Jisheng Zhang
2015-11-20 20:46 ` Sebastian Hesselbarth
2015-11-20 8:42 ` [PATCH v2 2/6] clk: berlin: add common clk driver for newer SoCs Jisheng Zhang
2015-11-20 20:54 ` Sebastian Hesselbarth
2015-11-20 8:42 ` [PATCH v2 3/6] clk: berlin: add common gateclk " Jisheng Zhang
2015-11-20 8:42 ` [PATCH v2 4/6] clk: berlin: add clk support for berlin4ct Jisheng Zhang
2015-11-20 20:56 ` Sebastian Hesselbarth
2015-11-23 5:56 ` Jisheng Zhang
2015-11-20 8:42 ` [PATCH v2 5/6] dt-bindings: add binding for marvell berlin4ct SoC Jisheng Zhang
2015-11-20 14:37 ` Rob Herring
2015-11-20 8:42 ` [PATCH v2 6/6] arm64: dts: berlin4ct: add pll and clock nodes Jisheng Zhang
[not found] ` <1448008952-1787-7-git-send-email-jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
2015-11-20 21:06 ` Sebastian Hesselbarth
2015-11-23 7:21 ` Jisheng Zhang
2015-11-23 8:14 ` Jisheng Zhang
2015-11-23 8:30 ` Sebastian Hesselbarth
2015-11-23 8:54 ` Jisheng Zhang
2015-11-24 2:35 ` Jisheng Zhang
2015-11-27 7:51 ` Sebastian Hesselbarth
2015-11-27 8:39 ` Jisheng Zhang
2015-11-27 8:45 ` Jisheng Zhang
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