* [PATCH 00/14] Initial Microchip PIC32MZDA Support
@ 2015-11-21 0:17 Joshua Henderson
2015-11-21 0:17 ` [PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller Joshua Henderson
` (6 more replies)
0 siblings, 7 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-11-21 0:17 UTC (permalink / raw)
To: linux-kernel
Cc: linux-mips, Joshua Henderson, Alim Akhtar, Andrei Pistirica,
Andrew Bresticker, Andy Green, Ben Hutchings, Chaotian Jing,
Corneliu Doban, Cristian Birsan, devicetree, Haojian Zhuang,
Jean Delvare, Kevin Hao, linux-api, linux-clk, linux-gpio,
linux-mmc, linux-serial, Lokesh Vutla, ludovic.desroches
This patch series adds support for the Microchip PIC32MZDA MIPS
platform. All drivers required to boot from MMC uSD card are
included. Clock and external interrupt controller drivers are
included. USART, console, and SDHCI peripheral drivers along with
the dependent pinctrl driver are included. This has been tested on
an applicable PIC32MZDA Starter Kit. A tree with these changes is
available at [0].
[0] https://github.com/joshua-henderson/linux/tree/pic32-upstream-v1
Andrei Pistirica (6):
DEVICETREE: Add bindings for PIC32 pin control and GPIO
pinctrl: Add PIC32 pin control driver
DEVICETREE: Add bindings for PIC32 usart driver
serial: pic32_uart: Add PIC32 uart driver
mmc: sdhci-pic32: Add PIC32 SDHC host controller driver
DEVICETREE: Add bindings for PIC32 SDHC host controller
Cristian Birsan (2):
DEVICETREE: Add bindings for PIC32 interrupt controller
irqchip: irq-pic32-evic: Add support for PIC32 interrupt controller
Joshua Henderson (4):
DEVICETREE: Add bindings for PIC32/MZDA platforms
MIPS: Add support for PIC32MZDA platform
MIPS: dts: Add initial DTS for the PIC32MZDA Starter Kit
MIPS: pic32mzda: Add initial PIC32MZDA Starter Kit defconfig
Purna Chandra Mandal (2):
DEVICETREE: Add PIC32 clock binding documentation
clk: clk-pic32: Add PIC32 clock driver
.../devicetree/bindings/clock/microchip,pic32.txt | 263 +++
.../bindings/gpio/microchip,pic32-gpio.txt | 33 +
.../microchip,pic32mz-evic.txt | 65 +
.../bindings/mips/pic32/microchip,pic32mzda.txt | 33 +
.../devicetree/bindings/mmc/sdhci-pic32.txt | 24 +
.../bindings/pinctrl/microchip,pic32-pinctrl.txt | 100 +
.../bindings/serial/microchip,pic32-usart.txt | 29 +
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 9 +
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/pic32/Makefile | 12 +
arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi | 251 +++
arch/mips/boot/dts/pic32/pic32mzda.dtsi | 280 +++
arch/mips/boot/dts/pic32/pic32mzda_sk.dts | 150 ++
arch/mips/configs/pic32mzda_defconfig | 88 +
.../include/asm/mach-pic32/cpu-feature-overrides.h | 32 +
arch/mips/include/asm/mach-pic32/gpio.h | 26 +
arch/mips/include/asm/mach-pic32/irq.h | 22 +
arch/mips/include/asm/mach-pic32/pic32.h | 44 +
arch/mips/include/asm/mach-pic32/spaces.h | 24 +
arch/mips/pic32/Kconfig | 50 +
arch/mips/pic32/Makefile | 6 +
arch/mips/pic32/Platform | 7 +
arch/mips/pic32/common/Makefile | 5 +
arch/mips/pic32/common/irq.c | 20 +
arch/mips/pic32/common/reset.c | 62 +
arch/mips/pic32/pic32mzda/Makefile | 9 +
arch/mips/pic32/pic32mzda/config.c | 148 ++
arch/mips/pic32/pic32mzda/early_clk.c | 106 +
arch/mips/pic32/pic32mzda/early_console.c | 171 ++
arch/mips/pic32/pic32mzda/early_pin.c | 275 +++
arch/mips/pic32/pic32mzda/early_pin.h | 241 +++
arch/mips/pic32/pic32mzda/init.c | 156 ++
arch/mips/pic32/pic32mzda/pic32mzda.h | 30 +
arch/mips/pic32/pic32mzda/time.c | 47 +
drivers/clk/Kconfig | 3 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-pic32.c | 1947 ++++++++++++++++++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-pic32-evic.c | 309 +++
drivers/mmc/host/Kconfig | 11 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-pic32.c | 354 ++++
drivers/pinctrl/Kconfig | 17 +
drivers/pinctrl/Makefile | 2 +
drivers/pinctrl/pinctrl-pic32.c | 2127 ++++++++++++++++++++
drivers/pinctrl/pinctrl-pic32.h | 158 ++
drivers/pinctrl/pinctrl-pic32mzda.c | 294 +++
drivers/pinctrl/pinctrl-pic32mzda.h | 40 +
drivers/tty/serial/Kconfig | 21 +
drivers/tty/serial/Makefile | 1 +
drivers/tty/serial/pic32_uart.c | 930 +++++++++
drivers/tty/serial/pic32_uart.h | 199 ++
.../interrupt-controller/microchip,pic32mz-evic.h | 238 +++
include/dt-bindings/pinctrl/pic32mzda.h | 404 ++++
include/linux/irqchip/pic32-evic.h | 19 +
include/linux/platform_data/sdhci-pic32.h | 22 +
include/uapi/linux/serial_core.h | 3 +
58 files changed, 9922 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt
create mode 100644 Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
create mode 100644 Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
create mode 100644 arch/mips/boot/dts/pic32/Makefile
create mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
create mode 100644 arch/mips/boot/dts/pic32/pic32mzda.dtsi
create mode 100644 arch/mips/boot/dts/pic32/pic32mzda_sk.dts
create mode 100644 arch/mips/configs/pic32mzda_defconfig
create mode 100644 arch/mips/include/asm/mach-pic32/cpu-feature-overrides.h
create mode 100644 arch/mips/include/asm/mach-pic32/gpio.h
create mode 100644 arch/mips/include/asm/mach-pic32/irq.h
create mode 100644 arch/mips/include/asm/mach-pic32/pic32.h
create mode 100644 arch/mips/include/asm/mach-pic32/spaces.h
create mode 100644 arch/mips/pic32/Kconfig
create mode 100644 arch/mips/pic32/Makefile
create mode 100644 arch/mips/pic32/Platform
create mode 100644 arch/mips/pic32/common/Makefile
create mode 100644 arch/mips/pic32/common/irq.c
create mode 100644 arch/mips/pic32/common/reset.c
create mode 100644 arch/mips/pic32/pic32mzda/Makefile
create mode 100644 arch/mips/pic32/pic32mzda/config.c
create mode 100644 arch/mips/pic32/pic32mzda/early_clk.c
create mode 100644 arch/mips/pic32/pic32mzda/early_console.c
create mode 100644 arch/mips/pic32/pic32mzda/early_pin.c
create mode 100644 arch/mips/pic32/pic32mzda/early_pin.h
create mode 100644 arch/mips/pic32/pic32mzda/init.c
create mode 100644 arch/mips/pic32/pic32mzda/pic32mzda.h
create mode 100644 arch/mips/pic32/pic32mzda/time.c
create mode 100644 drivers/clk/clk-pic32.c
create mode 100644 drivers/irqchip/irq-pic32-evic.c
create mode 100644 drivers/mmc/host/sdhci-pic32.c
create mode 100644 drivers/pinctrl/pinctrl-pic32.c
create mode 100644 drivers/pinctrl/pinctrl-pic32.h
create mode 100644 drivers/pinctrl/pinctrl-pic32mzda.c
create mode 100644 drivers/pinctrl/pinctrl-pic32mzda.h
create mode 100644 drivers/tty/serial/pic32_uart.c
create mode 100644 drivers/tty/serial/pic32_uart.h
create mode 100644 include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
create mode 100644 include/dt-bindings/pinctrl/pic32mzda.h
create mode 100644 include/linux/irqchip/pic32-evic.h
create mode 100644 include/linux/platform_data/sdhci-pic32.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller
2015-11-21 0:17 [PATCH 00/14] Initial Microchip PIC32MZDA Support Joshua Henderson
@ 2015-11-21 0:17 ` Joshua Henderson
2015-11-21 20:47 ` Arnd Bergmann
[not found] ` <1448065205-15762-2-git-send-email-joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
2015-11-21 0:17 ` [PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation Joshua Henderson
` (5 subsequent siblings)
6 siblings, 2 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-11-21 0:17 UTC (permalink / raw)
To: linux-kernel
Cc: linux-mips, Cristian Birsan, Joshua Henderson, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, devicetree
From: Cristian Birsan <cristian.birsan@microchip.com>
Document the devicetree bindings for the interrupt controller on Microchip
PIC32 class devices. This also adds a header defining associated interrupts
and related settings.
Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
---
.../microchip,pic32mz-evic.txt | 65 ++++++
.../interrupt-controller/microchip,pic32mz-evic.h | 238 ++++++++++++++++++++
2 files changed, 303 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
create mode 100644 include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
new file mode 100644
index 0000000..12fb91f
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
@@ -0,0 +1,65 @@
+Microchip PIC32MZ Interrupt Controller
+======================================
+
+The Microchip PIC32MZ SOC contains an Enhanced Vectored Interrupt Controller
+(EVIC) version 2. It handles internal and external interrupts and provides
+support for priority, sub-priority, irq type and polarity.
+
+Required properties
+-------------------
+
+- compatible: Should be "microchip,evic-v2"
+
+- reg: specifies physical base address and size of register range.
+
+- interrupt-controller: Identifies the node as an interrupt controller.
+
+- #interrupt cells: Specifies the number of cells used to encode an interrupt
+source connected to this controller. The value shall be 3 and interrupt
+descriptor shall have the following format:
+ <hw_irq irq_priority_and_subpriority irq_type>
+
+hw_irq - represents the hardware interrupt number as in the data sheet.
+
+irq_priority_and_subpriority - sets the priority and sub-priority for the
+interrupt line. The INT_PRI(pri, subpri) macro can be used to set desired
+values or the DEFAULT_INT_PRI can be used for the default value.
+
+irq_type - is used to describe the type and polarity of an interrupt. For
+internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
+IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
+IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity.
+
+Example
+-------
+
+evic: interrupt-controller@1f810000 {
+ compatible = "microchip,evic-v2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x1f810000 0x1000>;
+ device_type="evic-v2";
+};
+
+Each device must request his interrupt line with the associated priority and
+polarity
+
+Internal interrupt DTS snippet
+------------------------------
+
+device@1f800000 {
+ ...
+ interrupt-parent = <&evic>;
+ interrupts = <UART1_RECEIVE_DONE DEFAULT_INT_PRI IRQ_TYPE_NONE>;
+ ...
+};
+
+External interrupt DTS snippet
+------------------------------
+
+device@1f800000 {
+ ...
+ interrupt-parent = <&evic>;
+ interrupts = <EXTERNAL_INTERRUPT_0 DEFAULT_INT_PRI IRQ_TYPE_EDGE_RISING>;
+ ...
+};
diff --git a/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h b/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
new file mode 100644
index 0000000..2c466b8
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
@@ -0,0 +1,238 @@
+/*
+ * This header provides constants for the MICROCHIP PIC32 EVIC.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_EVIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_EVIC_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* Hardware interrupt number */
+#define CORE_TIMER_INTERRUPT 0
+#define CORE_SOFTWARE_INTERRUPT_0 1
+#define CORE_SOFTWARE_INTERRUPT_1 2
+#define EXTERNAL_INTERRUPT_0 3
+#define TIMER1 4
+#define INPUT_CAPTURE_1_ERROR 5
+#define INPUT_CAPTURE_1 6
+#define OUTPUT_COMPARE_1 7
+#define EXTERNAL_INTERRUPT_1 8
+#define TIMER2 9
+#define INPUT_CAPTURE_2_ERROR 10
+#define INPUT_CAPTURE_2 11
+#define OUTPUT_COMPARE_2 12
+#define EXTERNAL_INTERRUPT_2 13
+#define TIMER3 14
+#define INPUT_CAPTURE_3_ERROR 15
+#define INPUT_CAPTURE_3 16
+#define OUTPUT_COMPARE_3 17
+#define EXTERNAL_INTERRUPT_3 18
+#define TIMER4 19
+#define INPUT_CAPTURE_4_ERROR 20
+#define INPUT_CAPTURE_4 21
+#define OUTPUT_COMPARE_4 22
+#define EXTERNAL_INTERRUPT_4 23
+#define TIMER5 24
+#define INPUT_CAPTURE_5_ERROR 25
+#define INPUT_CAPTURE_5 26
+#define OUTPUT_COMPARE_5 27
+#define TIMER6 28
+#define INPUT_CAPTURE_6_ERROR 29
+#define INPUT_CAPTURE_6 30
+#define OUTPUT_COMPARE_6 31
+#define TIMER7 32
+#define INPUT_CAPTURE_7_ERROR 33
+#define INPUT_CAPTURE_7 34
+#define OUTPUT_COMPARE_7 35
+#define TIMER8 36
+#define INPUT_CAPTURE_8_ERROR 37
+#define INPUT_CAPTURE_8 38
+#define OUTPUT_COMPARE_8 39
+#define TIMER9 40
+#define INPUT_CAPTURE_9_ERROR 41
+#define INPUT_CAPTURE_9 42
+#define OUTPUT_COMPARE_9 43
+/* ADC */
+#define ADC1_GLOBAL 44
+/* Reserved */
+#define ADC1_DIGITAL_COMPARATOR_1 46
+#define ADC1_DIGITAL_COMPARATOR_2 47
+#define ADC1_DIGITAL_COMPARATOR_3 48
+#define ADC1_DIGITAL_COMPARATOR_4 49
+#define ADC1_DIGITAL_COMPARATOR_5 50
+#define ADC1_DIGITAL_COMPARATOR_6 51
+#define ADC1_DIGITAL_FILTER_1 52
+#define ADC1_DIGITAL_FILTER_2 53
+#define ADC1_DIGITAL_FILTER_3 54
+#define ADC1_DIGITAL_FILTER_4 55
+#define ADC1_DIGITAL_FILTER_5 56
+#define ADC1_DIGITAL_FILTER_6 57
+/* Reserved */
+#define ADC1_DATA_0 59
+#define ADC1_DATA_1 60
+#define ADC1_DATA_2 61
+#define ADC1_DATA_3 62
+#define ADC1_DATA_4 63
+#define ADC1_DATA_5 64
+#define ADC1_DATA_6 65
+#define ADC1_DATA_7 66
+#define ADC1_DATA_8 67
+#define ADC1_DATA_9 68
+#define ADC1_DATA_10 69
+#define ADC1_DATA_11 70
+#define ADC1_DATA_12 71
+#define ADC1_DATA_13 72
+#define ADC1_DATA_14 73
+#define ADC1_DATA_15 74
+#define ADC1_DATA_16 75
+#define ADC1_DATA_17 76
+#define ADC1_DATA_18 77
+#define ADC1_DATA_19 78
+#define ADC1_DATA_20 79
+#define ADC1_DATA_21 80
+#define ADC1_DATA_22 81
+#define ADC1_DATA_23 82
+#define ADC1_DATA_24 83
+#define ADC1_DATA_25 84
+#define ADC1_DATA_26 85
+#define ADC1_DATA_27 86
+#define ADC1_DATA_28 87
+#define ADC1_DATA_29 88
+#define ADC1_DATA_30 89
+#define ADC1_DATA_31 90
+#define ADC1_DATA_32 91
+#define ADC1_DATA_33 92
+#define ADC1_DATA_34 93
+#define ADC1_DATA_35 94
+#define ADC1_DATA_36 95
+#define ADC1_DATA_37 96
+#define ADC1_DATA_38 97
+#define ADC1_DATA_39 98
+#define ADC1_DATA_40 99
+#define ADC1_DATA_41 100
+#define ADC1_DATA_42 101
+#define ADC1_DATA_43 102
+#define ADC1_DATA_44 103
+#define CORE_PERFORMANCE_COUNTER_INTERRUPT 104
+#define CORE_FAST_DEBUG_CHANNEL_INTERRUPT 105
+#define SYSTEM_BUS_PROTECTION_VIOLATION 106
+#define CRYPTO_ENGINE_EVENT 107
+/* Reserved */
+#define SPI1_FAULT 109
+#define SPI1_RECEIVE_DONE 110
+#define SPI1_TRANSFER_DONE 111
+#define UART1_FAULT 112
+#define UART1_RECEIVE_DONE 113
+#define UART1_TRANSFER_DONE 114
+#define I2C1_BUS_COLLISION_EVENT 115
+#define I2C1_SLAVE_EVENT 116
+#define I2C1_MASTER_EVENT 117
+#define PORTA_INPUT_CHANGE_INTERRUPT 118
+#define PORTB_INPUT_CHANGE_INTERRUPT 119
+#define PORTC_INPUT_CHANGE_INTERRUPT 120
+#define PORTD_INPUT_CHANGE_INTERRUPT 121
+#define PORTE_INPUT_CHANGE_INTERRUPT 122
+#define PORTF_INPUT_CHANGE_INTERRUPT 123
+#define PORTG_INPUT_CHANGE_INTERRUPT 124
+#define PORTH_INPUT_CHANGE_INTERRUPT 125
+#define PORTJ_INPUT_CHANGE_INTERRUPT 126
+#define PORTK_INPUT_CHANGE_INTERRUPT 127
+#define PARALLEL_MASTER_PORT 128
+#define PARALLEL_MASTER_PORT_ERROR 129
+#define COMPARATOR_1_INTERRUPT 130
+#define COMPARATOR_2_INTERRUPT 131
+#define USB_GENERAL_EVENT 132
+#define USB_DMA_EVENT 133
+#define DMA_CHANNEL_0 134
+#define DMA_CHANNEL_1 135
+#define DMA_CHANNEL_2 136
+#define DMA_CHANNEL_3 137
+#define DMA_CHANNEL_4 138
+#define DMA_CHANNEL_5 139
+#define DMA_CHANNEL_6 140
+#define DMA_CHANNEL_7 141
+#define SPI2_FAULT 142
+#define SPI2_RECEIVE_DONE 143
+#define SPI2_TRANSFER_DONE 144
+#define UART2_FAULT 145
+#define UART2_RECEIVE_DONE 146
+#define UART2_TRANSFER_DONE 147
+#define I2C2_BUS_COLLISION_EVENT 148
+#define I2C2_SLAVE_EVENT 149
+#define I2C2_MASTER_EVENT 150
+#define CONTROL_AREA_NETWORK_1 151
+#define CONTROL_AREA_NETWORK_2 152
+#define ETHERNET_INTERRUPT 153
+#define SPI3_FAULT 154
+#define SPI3_RECEIVE_DONE 155
+#define SPI3_TRANSFER_DONE 156
+#define UART3_FAULT 157
+#define UART3_RECEIVE_DONE 158
+#define UART3_TRANSFER_DONE 159
+#define I2C3_BUS_COLLISION_EVENT 160
+#define I2C3_SLAVE_EVENT 161
+#define I2C3_MASTER_EVENT 162
+#define SPI4_FAULT 163
+#define SPI4_RECEIVE_DONE 164
+#define SPI4_TRANSFER_DONE 165
+#define REAL_TIME_CLOCK 166
+#define FLASH_CONTROL_EVENT 167
+#define PREFETCH_MODULE_SEC_EVENT 168
+#define SQI1_EVENT 169
+#define UART4_FAULT 170
+#define UART4_RECEIVE_DONE 171
+#define UART4_TRANSFER_DONE 172
+#define I2C4_BUS_COLLISION_EVENT 173
+#define I2C4_SLAVE_EVENT 174
+#define I2C4_MASTER_EVENT 175
+#define SPI5_FAULT 176
+#define SPI5_RECEIVE_DONE 177
+#define SPI5_TRANSFER_DONE 178
+#define UART5_FAULT 179
+#define UART5_RECEIVE_DONE 180
+#define UART5_TRANSFER_DONE 181
+#define I2C5_BUS_COLLISION_EVENT 182
+#define I2C5_SLAVE_EVENT 183
+#define I2C5_MASTER_EVENT 184
+#define SPI6_FAULT 185
+#define SPI6_RECEIVE_DONE 186
+#define SPI6_TRANSFER_DONE 187
+#define UART6_FAULT 188
+#define UART6_RECEIVE_DONE 189
+#define UART6_TRANSFER_DONE 190
+#define SDHC_EVENT 191
+#define GLCD_INTERRUPT 192
+#define GPU_INTERRUPT 193
+
+/* Interrupt priority bits */
+#define PRI_0 0 /* Note:This priority disables the interrupt! */
+#define PRI_1 1
+#define PRI_2 2
+#define PRI_3 3
+#define PRI_4 4
+#define PRI_5 5
+#define PRI_6 6
+#define PRI_7 7
+
+/* Interrupt subpriority bits */
+#define SUB_PRI_0 0
+#define SUB_PRI_1 1
+#define SUB_PRI_2 2
+#define SUB_PRI_3 3
+
+#define PRI_MASK 0x7 /* 3 bit priority mask */
+#define SUBPRI_MASK 0x3 /* 2 bit subpriority mask */
+#define INT_MASK 0x1F /* 5 bit pri and subpri mask */
+#define NR_EXT_IRQS 5 /* 5 external interrupts sources */
+
+#define MICROCHIP_EVIC_MIN_PRIORITY 0
+#define MICROCHIP_EVIC_MAX_PRIORITY INT_MASK
+
+#define INT_PRI(pri, subpri) \
+ (((pri & PRI_MASK) << 2) | (subpri & SUBPRI_MASK))
+
+#define DEFINE_INT(irq, pri) { irq, pri }
+
+#define DEFAULT_INT_PRI INT_PRI(2, 0)
+
+#endif /*_DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_EVIC_H*/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation
2015-11-21 0:17 [PATCH 00/14] Initial Microchip PIC32MZDA Support Joshua Henderson
2015-11-21 0:17 ` [PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller Joshua Henderson
@ 2015-11-21 0:17 ` Joshua Henderson
2015-11-21 20:49 ` Arnd Bergmann
[not found] ` <1448065205-15762-4-git-send-email-joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
2015-11-21 0:17 ` [PATCH 05/14] DEVICETREE: Add bindings for PIC32/MZDA platforms Joshua Henderson
` (4 subsequent siblings)
6 siblings, 2 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-11-21 0:17 UTC (permalink / raw)
To: linux-kernel
Cc: linux-mips, Purna Chandra Mandal, Joshua Henderson, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, devicetree
From: Purna Chandra Mandal <purna.mandal@microchip.com>
Document the devicetree bindings for the clock driver found on Microchip
PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
---
.../devicetree/bindings/clock/microchip,pic32.txt | 263 ++++++++++++++++++++
1 file changed, 263 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt
diff --git a/Documentation/devicetree/bindings/clock/microchip,pic32.txt b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
new file mode 100644
index 0000000..4cef72d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
@@ -0,0 +1,263 @@
+Binding for a Clock hardware block found on
+certain Microchip PIC32 MCU devices.
+
+Microchip SoC clocks-node consists of few oscillators, PLL, multiplexer
+and few divider nodes.
+
+We will find only the base address of the clock tree, this base
+address is common for some of the subnodes, not all. If no address is
+specified for any of subnode base address of the clock tree will be
+treated as its base. Each of subnodes follow the same common clock
+binding with some additional optional properties.
+
+ clocks_node {
+ reg = <>;
+
+ spll_node {
+ ...
+ };
+
+ frcdiv_node {
+ ...
+ };
+
+ sysclk_mux_node {
+ ...
+ };
+
+ pbdiv_node {
+ ...
+ };
+
+ refoclk_node {
+ ...
+ };
+ ...
+ };
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : should have "microchip,pic32-clk".
+- reg : A Base address and length of the register set.
+- interrupts : source of interrupt.
+
+Optional properties (for subnodes):
+- #clock-cells: From common clock binding, should be 0.
+
+- microchip,clock-indices: in multiplexer node clock sources always aren't linear
+ and contiguous. This property helps define clock-sources with respect to
+ the mux clock node.
+
+- microchip,ignore-unused : ignore gate request even if the gated clock is unused.
+- microchip,status-bit-mask: bitmask for status check. This will be used to confirm
+ particular operation by clock sub-node is completed. It is dependent sub-node.
+- microchip,bit-mask: enable mask, similar to microchip,status-bit-mask.
+- microchip,slew-step: enable frequency slewing(stepping) during rate change;
+ applicable only to sys-clock subnode.
+
+Example:
+
+/* PIC32 specific clks */
+pic32_clktree {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1f801200 0x200>;
+ compatible = "microchip,pic32-clk";
+ interrupts = <12>;
+ ranges;
+
+ /* secondary oscillator; external input on SOSCI pin */
+ SOSC:sosc_clk {
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-sosc";
+ clock-frequency = <32768>;
+ reg = <0x1f801200 0x10 /* enable reg */
+ 0x1f801390 0x10>; /* status reg */
+ microchip,bit-mask = <0x02>; /* enable mask */
+ microchip,status-bit-mask = <0x10>; /* status-mask*/
+ };
+
+ FRCDIV:frcdiv_clk {
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-frcdivclk";
+ clocks = <&FRC>;
+ clock-output-names = "frcdiv_clk";
+ };
+
+ /* System PLL clock */
+ SYSPLL:spll_clk {
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-syspll";
+ reg = <0x1f801220 0x10 /* SPLL register */
+ 0x1f801390 0x10>; /* CLKSTAT register */
+ clocks = <&POSC>, <&FRC>;
+ clock-output-names = "sys_pll";
+ microchip,status-bit-mask = <0x80>; /* SPLLRDY */
+ };
+
+ /* system clock; mux with postdiv & slew */
+ SYSCLK:sys_clk {
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-sysclk-v2";
+ reg = <0x1f8013c0 0x04>; /* SLEWCON */
+ clocks = <&FRCDIV>, <&SYSPLL>, <&POSC>, <&SOSC>,
+ <&LPRC>, <&FRCDIV>;
+ microchip,clock-indices = <0>, <1>, <2>, <4>, <5>, <7>;
+ clock-output-names = "sys_clk";
+ };
+
+ /* DDR Ctrl & DDR PHY PLL */
+ MPLL: CLK_MPLL {
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-mpll";
+ reg = <0x1f800100 0x04>; /* CFGMPLL */
+ clocks = <&POSC>;
+ clock-output-names = "pic32-mpll";
+ status = "disabled";
+ };
+
+ /* Peripheral bus1 clock */
+ PBCLK1:pb1_clk {
+ reg = <0x1f801340 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ clock-output-names = "pb1_clk";
+ /* used by system modules, not gateable */
+ microchip,ignore-unused;
+ };
+
+ /* Peripheral bus2 clock */
+ PBCLK2:pb2_clk {
+ reg = <0x1f801350 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ clock-output-names = "pb2_clk";
+ /* avoid gating even if unused */
+ microchip,ignore-unused;
+ };
+
+ /* Peripheral bus3 clock */
+ PBCLK3:pb3_clk {
+ reg = <0x1f801360 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ clock-output-names = "pb3_clk";
+ };
+
+ /* Peripheral bus4 clock(I/O ports, GPIO) */
+ PBCLK4:pb4_clk {
+ reg = <0x1f801370 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ clock-output-names = "pb4_clk";
+ };
+
+ /* Peripheral bus clock */
+ PBCLK5:pb5_clk {
+ reg = <0x1f801380 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ clock-output-names = "pb5_clk";
+ };
+
+ /* Peripheral Bus6 clock; */
+ PBCLK6:pb6_clk {
+ reg = <0x1f801390 0x10>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ #clock-cells = <0>;
+ };
+
+ /* Peripheral bus7 clock */
+ PBCLK7:pb7_clk {
+ reg = <0x1f8013A0 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ /* CPU is driven by this clock; so named */
+ clock-output-names = "cpu_clk";
+ clocks = <&SYSCLK>;
+ };
+
+ /* Reference Oscillator clock for SPI/I2S */
+ REFCLKO1:refo1_clk {
+ reg = <0x1f801280 0x20>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-refoclk";
+ clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
+ <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
+ microchip,clock-indices = <0>, <1>, <2>, <3>, <4>, <5>,
+ <7>, <8>, <9>;
+ clock-output-names = "refo1_clk";
+ clock-frequency = <10000000>; /* 10Mhz for I2S MCLK */
+ };
+
+ /* Reference Oscillator clock for SQI */
+ REFCLKO2:refo2_clk {
+ reg = <0x1f8012A0 0x20>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-refoclk";
+ clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
+ <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
+ microchip,clock-indices = <0>, <1>, <2>, <3>, <4>, <5>,
+ <7>, <8>, <9>;
+ clock-output-names = "refo2_clk";
+ clock-frequency = <50000000>; /* 50MHz for SQI */
+ };
+
+ /* Reference Oscillator clock, ADC */
+ REFCLKO3:refo3_clk {
+ reg = <0x1f8012C0 0x20>;
+ compatible = "microchip,pic32-refoclk";
+ clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
+ <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
+ microchip,clock-indices = <0>, <1>, <2>, <3>, <4>, <5>,
+ <7>, <8>, <9>;
+ #clock-cells = <0>;
+ clock-output-names = "refo3_clk";
+ clock-frequency = <10000000>; /* 1Mhz */
+ };
+
+ /* Reference Oscillator clock */
+ REFCLKO4:refo4_clk {
+ reg = <0x1f8012E0 0x20>;
+ compatible = "microchip,pic32-refoclk";
+ clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
+ <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
+ microchip,clock-indices = <0>,<1>,<2>,<3>,<4>,<5>,<7>,
+ <8>,<9>;
+ #clock-cells = <0>;
+ clock-output-names = "refo4_clk";
+ clock-frequency = <25000000>; /* 25Mhz */
+ };
+
+ /* Reference Oscillator clock, LCD */
+ REFCLKO5:refo5_clk {
+ reg = <0x1f801300 0x20>;
+ compatible = "microchip,pic32-refoclk";
+ clocks = <&SYSCLK>,<&PBCLK1>,<&POSC>,<&FRC>,<&LPRC>,
+ <&SOSC>,<&SYSPLL>,<&REFIx>,<&BFRC>;
+ microchip,clock-indices = <0>, <1>, <2>, <3>, <4>, <5>,
+ <7>, <8>,<9>;
+ #clock-cells = <0>;
+ clock-output-names = "refo5_clk";
+ clock-frequency = <40000000>; /* 40Mhz */
+ };
+};
+
+The clock consumer should specify the desired clock by having the clocks in its
+"clock" phandle cell. For example for UART:
+
+uart2: serial@<> {
+ compatible = "microchip,pic32-uart";
+ reg = <>;
+ interrupts = <>;
+ clocks = <&PBCLK2>;
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 05/14] DEVICETREE: Add bindings for PIC32/MZDA platforms
2015-11-21 0:17 [PATCH 00/14] Initial Microchip PIC32MZDA Support Joshua Henderson
2015-11-21 0:17 ` [PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller Joshua Henderson
2015-11-21 0:17 ` [PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation Joshua Henderson
@ 2015-11-21 0:17 ` Joshua Henderson
2015-11-22 21:35 ` Rob Herring
2015-11-21 0:17 ` [PATCH 07/14] DEVICETREE: Add bindings for PIC32 pin control and GPIO Joshua Henderson
` (3 subsequent siblings)
6 siblings, 1 reply; 29+ messages in thread
From: Joshua Henderson @ 2015-11-21 0:17 UTC (permalink / raw)
To: linux-kernel
Cc: linux-mips, Joshua Henderson, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, devicetree
This adds support for the Microchip PIC32 platform along with the
specific variant PIC32MZDA on a PIC32MZDA Starter Kit.
Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
---
.../bindings/mips/pic32/microchip,pic32mzda.txt | 33 ++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
diff --git a/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt b/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
new file mode 100644
index 0000000..bcf3e04
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
@@ -0,0 +1,33 @@
+* Microchip PIC32MZDA Platforms
+
+PIC32MZDA Starter Kit
+Required root node properties:
+ - compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda"
+
+CPU nodes:
+----------
+A "cpus" node is required. Required properties:
+ - #address-cells: Must be 1.
+ - #size-cells: Must be 0.
+A CPU sub-node is also required. Required properties:
+ - device_type: Must be "cpu".
+ - compatible: Must be "mti,mips14KEc".
+Example:
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "mti,mips14KEc";
+ };
+ };
+
+Boot protocol
+--------------
+In accordance with the MIPS UHI specification[1], the bootloader must pass the
+following arguments to the kernel:
+ - $a0: -2.
+ - $a1: KSEG0 address of the flattened device-tree blob.
+
+[1] http://prplfoundation.org/wiki/MIPS_documentation
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 07/14] DEVICETREE: Add bindings for PIC32 pin control and GPIO
2015-11-21 0:17 [PATCH 00/14] Initial Microchip PIC32MZDA Support Joshua Henderson
` (2 preceding siblings ...)
2015-11-21 0:17 ` [PATCH 05/14] DEVICETREE: Add bindings for PIC32/MZDA platforms Joshua Henderson
@ 2015-11-21 0:17 ` Joshua Henderson
2015-11-22 21:47 ` Rob Herring
2015-11-21 0:17 ` [PATCH 09/14] DEVICETREE: Add bindings for PIC32 usart driver Joshua Henderson
` (2 subsequent siblings)
6 siblings, 1 reply; 29+ messages in thread
From: Joshua Henderson @ 2015-11-21 0:17 UTC (permalink / raw)
To: linux-kernel
Cc: linux-mips, Andrei Pistirica, Joshua Henderson, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, devicetree
From: Andrei Pistirica <andrei.pistirica@microchip.com>
Document the devicetree bindings for PINCTRL and GPIO found on Microchip
PIC32 class devices. This also adds a header defining related port and
peripheral pin select functionality.
Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
---
.../bindings/gpio/microchip,pic32-gpio.txt | 33 ++
.../bindings/pinctrl/microchip,pic32-pinctrl.txt | 100 +++++
include/dt-bindings/pinctrl/pic32mzda.h | 404 ++++++++++++++++++++
3 files changed, 537 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
create mode 100644 include/dt-bindings/pinctrl/pic32mzda.h
diff --git a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
new file mode 100644
index 0000000..f6eeb2f
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
@@ -0,0 +1,33 @@
+* Microchip PIC32 GPIO devices (PIO).
+
+Required properties:
+ - compatible: "microchip,pic32-gpio"
+ - reg: Base address and length for the device.
+ - interrupts: The port interrupt shared be all pins.
+ - gpio-controller: Marks the port as GPIO controller.
+ - #gpio-cells: Two. The first cell is the pin number and
+ the second cell is unused.
+ - interrupt-controller: Marks the device node as an interrupt controller.
+ - #interrupt-cells: Two. The first cell is the GPIO number and second cell
+ is used to specify the trigger type:
+ PIC32_PIN_CN_RISING : low-to-high edge triggered.
+ PIC32_PIN_CN_FALLING : high-to-low edge triggered.
+ PIC32_PIN_CN_BOTH : low-to-high and high-to-low edges triggered.
+
+Note:
+ - If gpio-ranges is missing, then all the pins (32) related to the gpio bank
+ are enabled.
+
+Example:
+ pioA: gpio@1f860000 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860000 0x24>;
+ interrupts = <PORTA_INPUT_CHANGE_INTERRUPT
+ DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&pic32_pinctrl 0 0 32>;
+ clocks = <&PBCLK4>;
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
new file mode 100644
index 0000000..7cf4167
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
@@ -0,0 +1,100 @@
+* Microchip PIC32 Pinmux device.
+
+Please refer to pinctrl-bindings.txt for details of the pinctrl properties and
+common bindings.
+
+PIC32 'pin configuration node' is a node of a group of pins which can be
+used for a specific device or function. This node represents configuraions of
+single pins or a pairs of mux and related configuration.
+
+Required properties for pic32 device:
+ - compatible: "microchip,pic32-pinctrl", "microchip,pic32mz-pinctrl"
+ - reg: Base address and length for pps:in and pps:out registers.
+
+Properties for 'pin configuration node':
+ - pic32,pins: each entry consists of 3 intergers and represents the mux and
+ config settings for one pin. The first integer represent the remappable pin,
+ the second represent the peripheral pin and the last the configuration.
+ The format is pic32,pins = <PIC32_RP_'dir'_'pin'
+ PIC32_PP_'dir'_'peripherl-pin' PIC32_PIN_CONF_'config'>. The configurations
+ are divided in 2 classes: IN and OUT and each in 4 buckets. Each entry must
+ contains items from the same class and bucket, otherwise the driver will
+ notify an error and the initialization will fail.
+ - pic32,single-pins: each entry consists of 3 intergers and represents a pin
+ (that is not remappable) and related configuraion. The format is
+ pic32,single-pins = <PORT_'x' 'pin' PIC32_PIN_CONF_'config'>. Each port has
+ 32 pins and please refer to chip documentation for details of remappable
+ pins.
+
+Available pin configurations (refer to dt-bindings/pinctrl/pic32.h):
+ PIC32_PIN_CONF_NONE : no configuration (default).
+ PIC32_PIN_CONF_OD : indicate this pin need a open-drain (no direction).
+ PIC32_PIN_CONF_OD_OUT : indicate this pin need a open-drain out.
+ PIC32_PIN_CONF_PU : indicate this pin need a pull up (no direction).
+ PIC32_PIN_CONF_PU_IN : indicate this pin need a pull up in.
+ PIC32_PIN_CONF_PD : indicate this pin need a pull down (no direction).
+ PIC32_PIN_CONF_PD_IN : indicate this pin need a pull down input.
+ PIC32_PIN_CONF_AN : indicate this pin as analogic (no direction).
+ PIC32_PIN_CONF_AN_IN : indicate this pin as analogic input.
+ PIC32_PIN_CONF_DG : indicate this pin as digital (no direction).
+ PIC32_PIN_CONF_DG_IN : indicate this pin as digital input.
+ PIC32_PIN_CONF_DG_OUT : indicate this pin as digital output.
+
+NOTEs:
+1. The pins functions nods are defined under pic32 pinctrl node. The function's
+ pin groups are defined under functions node.
+2. Each pin group can have both pic32,pins and pic32,single-pins properties to
+ specify re-mappable or non-remappable pins with related mux and configs or
+ at least one.
+3. Each pin configuration node can have a phandle and devices can set pins
+ configurations by referring to the phandle of that pin configuration node.
+4. The pinctrl bindings are listed in dt-bindings/pinctrl/pic32.h.
+5. The gpio controller must be described in the pinctrl simple-bus.
+
+Example:
+pinctrl@1f800000{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "microchip,pic32-pinctrl", "simple-bus";
+ ranges;
+ reg = <0x1f801404 0x3c>, /* in */
+ <0x1f801538 0x57>; /* out */
+
+ pioA: gpio@1f860000 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860000 0x24>;
+ gpio-controller;
+ };
+
+ /* functions */
+ sw1 {
+ pinctrl_sw1: sw1-0 {
+ pic32,single-pins = <PORT_B 12 PIC32_PIN_CONF_PULLUP>;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1: uart1-0 {
+ pic32,pins =
+ <PIC32_RP_OUT_RPG7 PIC32_PP_OUT_U1TX PIC32_PIN_CONF_NONE
+ PIC32_RP_IN_RPG8 PIC32_PP_IN_U1RX PIC32_PIN_CONF_NONE>;
+ };
+ };
+};
+
+uart1: serial@1f822000 {
+ compatible = "microchip,pic32-uart";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+sw@1 {
+ compatible = "microchip,pic32-switch";
+
+ interrupt-parent = <&pioB>;
+ interrupts = <12 PIC32_CN_RISING>;/* GPIO_B_12 */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sw1>;
+};
diff --git a/include/dt-bindings/pinctrl/pic32mzda.h b/include/dt-bindings/pinctrl/pic32mzda.h
new file mode 100644
index 0000000..2fb86e8
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pic32mzda.h
@@ -0,0 +1,404 @@
+/*
+ * This header provides constants for PIC32MZDA pinctrl bindings.
+ *
+ * Copyright (C) 2015 Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
+ *
+ * GPLv2 or later.
+*/
+
+#ifndef __DT_BINDINGS_PIC32MZDA_PINCTRL_H__
+#define __DT_BINDINGS_PIC32MZDA_PINCTRL_H__
+
+/* cods offsets */
+#define BANK_OFF 0
+#define RP_OFF 5
+#define PP_OFF 0
+#define BUCKET_OFF 10
+#define DIR_OFF 15
+#define COD_OFF 16
+
+#define BANK(x) ((x) << (BANK_OFF))
+#define RPIN(x) ((x) << (RP_OFF))
+#define PPIN(x) ((x) << (PP_OFF))
+#define BUCKET(x) ((x) << (BUCKET_OFF))
+#define PINDIR(x) ((x) << (DIR_OFF))
+#define COD(x) ((x) << (COD_OFF))
+
+#define PP(x_pin, x_bucket, x_dir) \
+ ((PPIN(x_pin)) | (BUCKET(x_bucket)) | (PINDIR(x_dir)))
+
+#define RP(x_bank, x_pin, x_bucket, x_dir) \
+ ((BANK(x_bank)) | (RPIN(x_pin)) | \
+ (BUCKET(x_bucket)) | (PINDIR(x_dir)))
+
+/* pin direction
+ * Note: for PPS direction has 1 bit: IN or OUT and
+ * for CONF direction has 2 bit: IN, OUT or NONE
+ */
+#ifdef DIR_IN
+#undef DIR_IN
+#endif
+#ifdef DIR_OUT
+#undef DIR_OUT
+#endif
+#define DIR_IN 0 /* 00 */
+#define DIR_OUT 1 /* 01 */
+#define DIR_NONE 2 /* 10 */
+
+/* buckets */
+#define BUCKET_A (0x1) /* 00001 */
+#define BUCKET_B (0x2) /* 00010 */
+#define BUCKET_C (0x4) /* 00100 */
+#define BUCKET_D (0x8) /* 01000 */
+#define BUCKET_AB (BUCKET_A | BUCKET_B) /* 00011 */
+#define BUCKET_BD (BUCKET_B | BUCKET_D) /* 01010 */
+#define BUCKET_CD (BUCKET_C | BUCKET_D) /* 01100 */
+
+/* port, bank */
+#define PORT_A 0
+#define PORT_B 1
+#define PORT_C 2
+#define PORT_D 3
+#define PORT_E 4
+#define PORT_F 5
+#define PORT_G 6
+#define PORT_H 7
+#define PORT_J 8
+#define PORT_K 9
+
+/* peripheral pins */
+#define PP_INT0 0
+#define PP_INT1 1
+#define PP_INT2 2
+#define PP_INT3 3
+#define PP_INT4 4
+#define PP_T2CK 5
+#define PP_T3CK 6
+#define PP_T4CK 7
+#define PP_T5CK 8
+#define PP_T6CK 9
+#define PP_T7CK 10
+#define PP_T8CK 11
+#define PP_T9CK 12
+#define PP_IC1 13
+#define PP_IC2 14
+#define PP_IC3 15
+#define PP_IC4 16
+#define PP_IC5 17
+#define PP_IC6 18
+#define PP_IC7 19
+#define PP_IC8 20
+#define PP_IC9 21
+#define PP_OCFA 22
+#define PP_OCFB 23
+#define PP_U1RX 24
+#define PP_U1CTS 25
+#define PP_U2RX 26
+#define PP_U2CTS 27
+#define PP_U3RX 28
+#define PP_U3CTS 29
+#define PP_U4RX 30
+#define PP_U4CTS 31
+#define PP_U5RX 32
+#define PP_U5CTS 33
+#define PP_U6RX 34
+#define PP_U6CTS 35
+#define PP_SDI1 36
+#define PP_SS1 37
+#define PP_SDI2 38
+#define PP_SS2 39
+#define PP_SDI3 40
+#define PP_SS3 41
+#define PP_SDI4 42
+#define PP_SS4 43
+#define PP_SDI5 44
+#define PP_SS5 45
+#define PP_SDI6 46
+#define PP_SS6 47
+#define PP_C1RX 48
+#define PP_C2RX 49
+#define PP_REFCLKI1 50
+#define PP_REFCLKI3 51
+#define PP_REFCLKI4 52
+#define PP_U1RTS 53
+#define PP_U2RTS 54
+#define PP_U3RTS 55
+#define PP_U4RTS 56
+#define PP_U5RTS 57
+#define PP_U6RTS 58
+#define PP_U1TX 59
+#define PP_U2TX 60
+#define PP_U3TX 61
+#define PP_U4TX 62
+#define PP_U5TX 63
+#define PP_U6TX 64
+#define PP_REFCLKO1 65
+#define PP_REFCLKO3 66
+#define PP_REFCLKO4 67
+#define PP_SDO1 68
+#define PP_SDO2 69
+#define PP_SDO3 70
+#define PP_SDO4 71
+#define PP_SDO5 72
+#define PP_SDO6 73
+#define PP_OC1 74
+#define PP_OC2 75
+#define PP_OC3 76
+#define PP_OC4 77
+#define PP_OC5 78
+#define PP_OC6 79
+#define PP_OC7 80
+#define PP_OC8 81
+#define PP_OC9 82
+#define PP_C1OUT 83
+#define PP_C2OUT 84
+#define PP_C1TX 85
+#define PP_C2TX 86
+#define PP_SENTINEL 87
+/* add above this line and update the PP_MAX accordingly */
+#define PP_MAX 88
+
+/* MUX INPUT ----------------------------------------------------------------*/
+/* Peripheral pins: BUCKET A */
+#define PIC32_PP_IN_INT3 (PP(PP_INT3, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_T2CK (PP(PP_T2CK, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_T6CK (PP(PP_T6CK, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_IC3 (PP(PP_IC3, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_IC7 (PP(PP_IC7, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_U1RX (PP(PP_U1RX, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_U2CTS (PP(PP_U2CTS, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_U5RX (PP(PP_U5RX, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_U6CTS (PP(PP_U6CTS, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_SDI1 (PP(PP_SDI1, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_SDI3 (PP(PP_SDI3, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_SDI5 (PP(PP_SDI5, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_SS6 (PP(PP_SS6, BUCKET_A, DIR_IN))
+#define PIC32_PP_IN_REFCLKI1 (PP(PP_REFCLKI1, BUCKET_A, DIR_IN))
+
+/* Peripheral pins: BUCKET B */
+#define PIC32_PP_IN_INT4 (PP(PP_INT4, BUCKET_B, DIR_IN))
+#define PIC32_PP_IN_T5CK (PP(PP_T5CK, BUCKET_B, DIR_IN))
+#define PIC32_PP_IN_T7CK (PP(PP_T7CK, BUCKET_B, DIR_IN))
+#define PIC32_PP_IN_IC4 (PP(PP_IC4, BUCKET_B, DIR_IN))
+#define PIC32_PP_IN_IC8 (PP(PP_IC8, BUCKET_B, DIR_IN))
+#define PIC32_PP_IN_U3RX (PP(PP_U3RX, BUCKET_B, DIR_IN))
+#define PIC32_PP_IN_U4CTS (PP(PP_U4CTS, BUCKET_B, DIR_IN))
+#define PIC32_PP_IN_SDI2 (PP(PP_SDI2, BUCKET_B, DIR_IN))
+#define PIC32_PP_IN_SDI4 (PP(PP_SDI4, BUCKET_B, DIR_IN))
+#define PIC32_PP_IN_C1RX (PP(PP_C1RX, BUCKET_B, DIR_IN))
+#define PIC32_PP_IN_REFCLKI4 (PP(PP_REFCLKI4, BUCKET_A, DIR_IN))
+
+/* Peripheral pins: BUCKET C */
+#define PIC32_PP_IN_INT2 (PP(PP_INT2, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_T3CK (PP(PP_T3CK, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_T8CK (PP(PP_T8CK, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_IC2 (PP(PP_IC2, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_IC5 (PP(PP_IC5, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_IC9 (PP(PP_IC9, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_U1CTS (PP(PP_U1CTS, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_U2RX (PP(PP_U2RX, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_U5CTS (PP(PP_U5CTS, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_SS1 (PP(PP_SS1, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_SS3 (PP(PP_SS3, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_SS4 (PP(PP_SS4, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_SS5 (PP(PP_SS5, BUCKET_C, DIR_IN))
+#define PIC32_PP_IN_C2RX (PP(PP_C2RX, BUCKET_C, DIR_IN))
+
+/* Peripheral pins: BUCKET D */
+#define PIC32_PP_IN_INT1 (PP(PP_INT1, BUCKET_D, DIR_IN))
+#define PIC32_PP_IN_T4CK (PP(PP_T4CK, BUCKET_D, DIR_IN))
+#define PIC32_PP_IN_T9CK (PP(PP_T9CK, BUCKET_D, DIR_IN))
+#define PIC32_PP_IN_IC1 (PP(PP_IC1, BUCKET_D, DIR_IN))
+#define PIC32_PP_IN_IC6 (PP(PP_IC6, BUCKET_D, DIR_IN))
+#define PIC32_PP_IN_U3CTS (PP(PP_U3CTS, BUCKET_D, DIR_IN))
+#define PIC32_PP_IN_U4RX (PP(PP_U4RX, BUCKET_D, DIR_IN))
+#define PIC32_PP_IN_U6RX (PP(PP_U6RX, BUCKET_D, DIR_IN))
+#define PIC32_PP_IN_SS2 (PP(PP_SS2, BUCKET_D, DIR_IN))
+#define PIC32_PP_IN_SDI6 (PP(PP_SDI6, BUCKET_D, DIR_IN))
+#define PIC32_PP_IN_OCFA (PP(PP_OCFA, BUCKET_D, DIR_IN))
+#define PIC32_PP_IN_REFCLKI3 (PP(PP_REFCLKI3, BUCKET_D, DIR_IN))
+
+/* Remappable pins: BUCKET A */
+#define PIC32_RP_IN_RPD2 (RP(PORT_D, 2, BUCKET_A, DIR_IN) | COD(0x0))
+#define PIC32_RP_IN_RPG8 (RP(PORT_G, 8, BUCKET_A, DIR_IN) | COD(0x1))
+#define PIC32_RP_IN_RPF4 (RP(PORT_F, 4, BUCKET_A, DIR_IN) | COD(0x2))
+#define PIC32_RP_IN_RPF1 (RP(PORT_F, 1, BUCKET_A, DIR_IN) | COD(0x4))
+#define PIC32_RP_IN_RPB9 (RP(PORT_B, 9, BUCKET_A, DIR_IN) | COD(0x5))
+#define PIC32_RP_IN_RPB10 (RP(PORT_B, 10, BUCKET_A, DIR_IN) | COD(0x6))
+#define PIC32_RP_IN_RPC14 (RP(PORT_C, 14, BUCKET_A, DIR_IN) | COD(0x7))
+#define PIC32_RP_IN_RPB5 (RP(PORT_B, 5, BUCKET_A, DIR_IN) | COD(0x8))
+#define PIC32_RP_IN_RPC1 (RP(PORT_C, 1, BUCKET_A, DIR_IN) | COD(0xA))
+#define PIC32_RP_IN_RPD14 (RP(PORT_D, 14, BUCKET_A, DIR_IN) | COD(0xB))
+#define PIC32_RP_IN_RPG1 (RP(PORT_G, 1, BUCKET_A, DIR_IN) | COD(0xC))
+#define PIC32_RP_IN_RPA14 (RP(PORT_A, 14, BUCKET_A, DIR_IN) | COD(0xD))
+#define PIC32_RP_IN_RPD6 (RP(PORT_D, 6, BUCKET_A, DIR_IN) | COD(0xE))
+
+/* Remappable pins: BUCKET B */
+#define PIC32_RP_IN_RPD3 (RP(PORT_D, 3, BUCKET_B, DIR_IN) | COD(0x0))
+#define PIC32_RP_IN_RPG7 (RP(PORT_G, 7, BUCKET_B, DIR_IN) | COD(0x1))
+#define PIC32_RP_IN_RPF5 (RP(PORT_F, 5, BUCKET_B, DIR_IN) | COD(0x2))
+#define PIC32_RP_IN_RPD11 (RP(PORT_D, 11, BUCKET_B, DIR_IN) | COD(0x3))
+#define PIC32_RP_IN_RPF0 (RP(PORT_F, 0, BUCKET_B, DIR_IN) | COD(0x4))
+#define PIC32_RP_IN_RPB1 (RP(PORT_B, 1, BUCKET_B, DIR_IN) | COD(0x5))
+#define PIC32_RP_IN_RPE5 (RP(PORT_E, 5, BUCKET_B, DIR_IN) | COD(0x6))
+#define PIC32_RP_IN_RPC13 (RP(PORT_C, 13, BUCKET_B, DIR_IN) | COD(0x7))
+#define PIC32_RP_IN_RPB3 (RP(PORT_B, 3, BUCKET_B, DIR_IN) | COD(0x8))
+#define PIC32_RP_IN_RPC4 (RP(PORT_C, 4, BUCKET_B, DIR_IN) | COD(0xA))
+#define PIC32_RP_IN_RPG0 (RP(PORT_G, 0, BUCKET_B, DIR_IN) | COD(0xC))
+#define PIC32_RP_IN_RPA15 (RP(PORT_A, 15, BUCKET_B, DIR_IN) | COD(0xD))
+#define PIC32_RP_IN_RPD7 (RP(PORT_D, 7, BUCKET_B, DIR_IN) | COD(0xE))
+
+/* Remappable pins: BUCKET C */
+#define PIC32_RP_IN_RPD9 (RP(PORT_D, 9, BUCKET_C, DIR_IN) | COD(0x0))
+#define PIC32_RP_IN_RPB8 (RP(PORT_B, 8, BUCKET_C, DIR_IN) | COD(0x2))
+#define PIC32_RP_IN_RPB15 (RP(PORT_B, 15, BUCKET_C, DIR_IN) | COD(0x3))
+#define PIC32_RP_IN_RPD4 (RP(PORT_D, 4, BUCKET_C, DIR_IN) | COD(0x4))
+#define PIC32_RP_IN_RPB0 (RP(PORT_B, 0, BUCKET_C, DIR_IN) | COD(0x5))
+#define PIC32_RP_IN_RPE3 (RP(PORT_E, 3, BUCKET_C, DIR_IN) | COD(0x6))
+#define PIC32_RP_IN_RPB7 (RP(PORT_B, 7, BUCKET_C, DIR_IN) | COD(0x7))
+#define PIC32_RP_IN_RPF12 (RP(PORT_F, 12, BUCKET_C, DIR_IN) | COD(0x9))
+#define PIC32_RP_IN_RPD12 (RP(PORT_D, 12, BUCKET_C, DIR_IN) | COD(0xA))
+#define PIC32_RP_IN_RPF8 (RP(PORT_F, 8, BUCKET_C, DIR_IN) | COD(0xB))
+#define PIC32_RP_IN_RPC3 (RP(PORT_C, 3, BUCKET_C, DIR_IN) | COD(0xC))
+#define PIC32_RP_IN_RPE9 (RP(PORT_E, 9, BUCKET_C, DIR_IN) | COD(0xD))
+
+/* Remappable pins: BUCKET D */
+#define PIC32_RP_IN_RPG9 (RP(PORT_G, 9, BUCKET_D, DIR_IN) | COD(0x1))
+#define PIC32_RP_IN_RPD0 (RP(PORT_D, 0, BUCKET_D, DIR_IN) | COD(0x3))
+#define PIC32_RP_IN_RPB6 (RP(PORT_B, 6, BUCKET_D, DIR_IN) | COD(0x5))
+#define PIC32_RP_IN_RPD5 (RP(PORT_D, 5, BUCKET_D, DIR_IN) | COD(0x6))
+#define PIC32_RP_IN_RPB2 (RP(PORT_B, 2, BUCKET_D, DIR_IN) | COD(0x7))
+#define PIC32_RP_IN_RPF3 (RP(PORT_F, 3, BUCKET_D, DIR_IN) | COD(0x8))
+#define PIC32_RP_IN_RPF2 (RP(PORT_F, 2, BUCKET_D, DIR_IN) | COD(0xB))
+#define PIC32_RP_IN_RPC2 (RP(PORT_C, 2, BUCKET_D, DIR_IN) | COD(0xC))
+#define PIC32_RP_IN_RPE8 (RP(PORT_E, 8, BUCKET_D, DIR_IN) | COD(0xD))
+
+/* MUX OUTPUT ---------------------------------------------------------------*/
+/* Remappable pins: BUCKET A */
+#define PIC32_RP_OUT_RPD2 (RP(PORT_D, 2, BUCKET_A, DIR_OUT))
+#define PIC32_RP_OUT_RPG8 (RP(PORT_G, 8, BUCKET_A, DIR_OUT))
+#define PIC32_RP_OUT_RPF4 (RP(PORT_F, 4, BUCKET_A, DIR_OUT))
+#define PIC32_RP_OUT_RPF1 (RP(PORT_F, 1, BUCKET_A, DIR_OUT))
+#define PIC32_RP_OUT_RPB9 (RP(PORT_B, 9, BUCKET_A, DIR_OUT))
+#define PIC32_RP_OUT_RPB10 (RP(PORT_B, 10, BUCKET_A, DIR_OUT))
+#define PIC32_RP_OUT_RPB5 (RP(PORT_B, 5, BUCKET_A, DIR_OUT))
+#define PIC32_RP_OUT_RPC1 (RP(PORT_C, 1, BUCKET_A, DIR_OUT))
+#define PIC32_RP_OUT_RPD14 (RP(PORT_D, 14, BUCKET_A, DIR_OUT))
+#define PIC32_RP_OUT_RPG1 (RP(PORT_G, 1, BUCKET_A, DIR_OUT))
+#define PIC32_RP_OUT_RPA14 (RP(PORT_A, 14, BUCKET_A, DIR_OUT))
+#define PIC32_RP_OUT_RPD6 (RP(PORT_D, 6, BUCKET_A, DIR_OUT))
+
+/* Remappable pins: BUCKET B */
+#define PIC32_RP_OUT_RPD3 (RP(PORT_D, 3, BUCKET_B, DIR_OUT))
+#define PIC32_RP_OUT_RPG7 (RP(PORT_G, 7, BUCKET_B, DIR_OUT))
+#define PIC32_RP_OUT_RPF5 (RP(PORT_F, 5, BUCKET_B, DIR_OUT))
+#define PIC32_RP_OUT_RPD11 (RP(PORT_D, 11, BUCKET_B, DIR_OUT))
+#define PIC32_RP_OUT_RPF0 (RP(PORT_F, 0, BUCKET_B, DIR_OUT))
+#define PIC32_RP_OUT_RPB1 (RP(PORT_B, 1, BUCKET_B, DIR_OUT))
+#define PIC32_RP_OUT_RPE5 (RP(PORT_E, 5, BUCKET_B, DIR_OUT))
+#define PIC32_RP_OUT_RPB3 (RP(PORT_B, 3, BUCKET_B, DIR_OUT))
+#define PIC32_RP_OUT_RPC4 (RP(PORT_C, 4, BUCKET_B, DIR_OUT))
+#define PIC32_RP_OUT_RPG0 (RP(PORT_G, 0, BUCKET_B, DIR_OUT))
+#define PIC32_RP_OUT_RPA15 (RP(PORT_A, 15, BUCKET_B, DIR_OUT))
+#define PIC32_RP_OUT_RPD7 (RP(PORT_D, 7, BUCKET_B, DIR_OUT))
+
+/* Remappable pins: BUCKET C */
+#define PIC32_RP_OUT_RPD9 (RP(PORT_D, 9, BUCKET_C, DIR_OUT))
+#define PIC32_RP_OUT_RPB8 (RP(PORT_B, 8, BUCKET_C, DIR_OUT))
+#define PIC32_RP_OUT_RPB15 (RP(PORT_B, 15, BUCKET_C, DIR_OUT))
+#define PIC32_RP_OUT_RPD4 (RP(PORT_D, 4, BUCKET_C, DIR_OUT))
+#define PIC32_RP_OUT_RPB0 (RP(PORT_B, 0, BUCKET_C, DIR_OUT))
+#define PIC32_RP_OUT_RPE3 (RP(PORT_E, 3, BUCKET_C, DIR_OUT))
+#define PIC32_RP_OUT_RPB7 (RP(PORT_B, 7, BUCKET_C, DIR_OUT))
+#define PIC32_RP_OUT_RPF12 (RP(PORT_F, 12, BUCKET_C, DIR_OUT))
+#define PIC32_RP_OUT_RPD12 (RP(PORT_D, 12, BUCKET_C, DIR_OUT))
+#define PIC32_RP_OUT_RPF8 (RP(PORT_F, 8, BUCKET_C, DIR_OUT))
+#define PIC32_RP_OUT_RPC3 (RP(PORT_C, 3, BUCKET_C, DIR_OUT))
+#define PIC32_RP_OUT_RPE9 (RP(PORT_E, 9, BUCKET_C, DIR_OUT))
+
+/* Remappable pins: BUCKET D */
+#define PIC32_RP_OUT_RPG9 (RP(PORT_G, 9, BUCKET_D, DIR_OUT))
+#define PIC32_RP_OUT_RPD0 (RP(PORT_D, 0, BUCKET_D, DIR_OUT))
+#define PIC32_RP_OUT_RPB6 (RP(PORT_B, 6, BUCKET_D, DIR_OUT))
+#define PIC32_RP_OUT_RPD5 (RP(PORT_D, 5, BUCKET_D, DIR_OUT))
+#define PIC32_RP_OUT_RPB2 (RP(PORT_B, 2, BUCKET_D, DIR_OUT))
+#define PIC32_RP_OUT_RPF3 (RP(PORT_F, 3, BUCKET_D, DIR_OUT))
+#define PIC32_RP_OUT_RPC2 (RP(PORT_C, 2, BUCKET_D, DIR_OUT))
+#define PIC32_RP_OUT_RPE8 (RP(PORT_E, 8, BUCKET_D, DIR_OUT))
+#define PIC32_RP_OUT_RPF2 (RP(PORT_F, 2, BUCKET_D, DIR_OUT))
+
+/* Peripheral pins: all buckets */
+#define PIC32_PP_OUT_U3TX (PP(PP_U3TX, BUCKET_A, DIR_OUT) | COD(0x1))
+#define PIC32_PP_OUT_U4RTS (PP(PP_U4RTS, BUCKET_A, DIR_OUT) | COD(0x2))
+#define PIC32_PP_OUT_SDO1 (PP(PP_SDO1, BUCKET_AB, DIR_OUT) | COD(0x5))
+#define PIC32_PP_OUT_SDO2 (PP(PP_SDO2, BUCKET_AB, DIR_OUT) | COD(0x6))
+#define PIC32_PP_OUT_SDO3 (PP(PP_SDO3, BUCKET_AB, DIR_OUT) | COD(0x7))
+#define PIC32_PP_OUT_SDO5 (PP(PP_SDO5, BUCKET_AB, DIR_OUT) | COD(0x9))
+#define PIC32_PP_OUT_SS6 (PP(PP_SS6, BUCKET_A, DIR_OUT) | COD(0xA))
+#define PIC32_PP_OUT_OC3 (PP(PP_OC3, BUCKET_A, DIR_OUT) | COD(0xB))
+#define PIC32_PP_OUT_OC6 (PP(PP_OC6, BUCKET_A, DIR_OUT) | COD(0xC))
+#define PIC32_PP_OUT_REFCLKO4 (PP(PP_REFCLKO4, BUCKET_A, DIR_OUT) | COD(0xD))
+#define PIC32_PP_OUT_C2OUT (PP(PP_C2OUT, BUCKET_A, DIR_OUT) | COD(0xE))
+#define PIC32_PP_OUT_C1TX (PP(PP_C1TX, BUCKET_A, DIR_OUT) | COD(0xF))
+
+#define PIC32_PP_OUT_U1TX (PP(PP_U1TX, BUCKET_B, DIR_OUT) | COD(0x1))
+#define PIC32_PP_OUT_U2RTS (PP(PP_U2RTS, BUCKET_B, DIR_OUT) | COD(0x2))
+#define PIC32_PP_OUT_U5TX (PP(PP_U5TX, BUCKET_B, DIR_OUT) | COD(0x3))
+#define PIC32_PP_OUT_U6RTS (PP(PP_U6RTS, BUCKET_B, DIR_OUT) | COD(0x4))
+#define PIC32_PP_OUT_SDO4 (PP(PP_SDO4, BUCKET_BD, DIR_OUT) | COD(0x8))
+#define PIC32_PP_OUT_OC4 (PP(PP_OC4, BUCKET_B, DIR_OUT) | COD(0xB))
+#define PIC32_PP_OUT_OC7 (PP(PP_OC7, BUCKET_B, DIR_OUT) | COD(0xC))
+#define PIC32_PP_OUT_REFCLKO1 (PP(PP_REFCLKO1, BUCKET_B, DIR_OUT) | COD(0xF))
+
+#define PIC32_PP_OUT_U3RTS (PP(PP_U3RTS, BUCKET_C, DIR_OUT) | COD(0x1))
+#define PIC32_PP_OUT_U4TX (PP(PP_U4TX, BUCKET_C, DIR_OUT) | COD(0x2))
+#define PIC32_PP_OUT_U6TX (PP(PP_U6TX, BUCKET_CD, DIR_OUT) | COD(0x4))
+#define PIC32_PP_OUT_SS1 (PP(PP_SS1, BUCKET_C, DIR_OUT) | COD(0x5))
+#define PIC32_PP_OUT_SS3 (PP(PP_SS3, BUCKET_C, DIR_OUT) | COD(0x7))
+#define PIC32_PP_OUT_SS4 (PP(PP_SS4, BUCKET_C, DIR_OUT) | COD(0x8))
+#define PIC32_PP_OUT_SS5 (PP(PP_SS5, BUCKET_C, DIR_OUT) | COD(0x9))
+#define PIC32_PP_OUT_SDO6 (PP(PP_SDO6, BUCKET_CD, DIR_OUT) | COD(0xA))
+#define PIC32_PP_OUT_OC5 (PP(PP_OC5, BUCKET_C, DIR_OUT) | COD(0xB))
+#define PIC32_PP_OUT_OC8 (PP(PP_OC8, BUCKET_C, DIR_OUT) | COD(0xC))
+#define PIC32_PP_OUT_C1OUT (PP(PP_C1OUT, BUCKET_C, DIR_OUT) | COD(0xE))
+#define PIC32_PP_OUT_REFCLKO3 (PP(PP_REFCLKO3, BUCKET_C, DIR_OUT) | COD(0xF))
+
+#define PIC32_PP_OUT_U1RTS (PP(PP_U1RTS, BUCKET_D, DIR_OUT) | COD(0x1))
+#define PIC32_PP_OUT_U2TX (PP(PP_U2TX, BUCKET_D, DIR_OUT) | COD(0x2))
+#define PIC32_PP_OUT_U5RTS (PP(PP_U5RTS, BUCKET_D, DIR_OUT) | COD(0x3))
+#define PIC32_PP_OUT_SS2 (PP(PP_SS2, BUCKET_D, DIR_OUT) | COD(0x6))
+#define PIC32_PP_OUT_OC2 (PP(PP_OC2, BUCKET_D, DIR_OUT) | COD(0xB))
+#define PIC32_PP_OUT_OC1 (PP(PP_OC1, BUCKET_D, DIR_OUT) | COD(0xC))
+#define PIC32_PP_OUT_OC9 (PP(PP_OC9, BUCKET_D, DIR_OUT) | COD(0xD))
+#define PIC32_PP_OUT_C2TX (PP(PP_C2TX, BUCKET_D, DIR_OUT) | COD(0xF))
+
+/* pin configurations flags */
+#define CONF_DIR_OFF 0
+#define CONF_COD_OFF 2
+#define CONF_DIR(x) ((x) << (CONF_DIR_OFF))
+#define CONF_COD(x) ((x) << (CONF_COD_OFF))
+
+#define PIC32_PIN_CONF_NONE (CONF_DIR(DIR_NONE) | CONF_COD(0x0))
+
+#define PIC32_PIN_CONF_OD (CONF_DIR(DIR_NONE) | CONF_COD(0x1))
+#define PIC32_PIN_CONF_OD_OUT (CONF_DIR(DIR_OUT) | CONF_COD(0x2))
+
+#define PIC32_PIN_CONF_PU (CONF_DIR(DIR_NONE) | CONF_COD(0x3))
+#define PIC32_PIN_CONF_PU_IN (CONF_DIR(DIR_IN) | CONF_COD(0x4))
+
+#define PIC32_PIN_CONF_PD (CONF_DIR(DIR_NONE) | CONF_COD(0x5))
+#define PIC32_PIN_CONF_PD_IN (CONF_DIR(DIR_IN) | CONF_COD(0x6))
+
+#define PIC32_PIN_CONF_AN (CONF_DIR(DIR_NONE) | CONF_COD(0x7))
+#define PIC32_PIN_CONF_AN_IN (CONF_DIR(DIR_IN) | CONF_COD(0x8))
+
+#define PIC32_PIN_CONF_DG (CONF_DIR(DIR_NONE) | CONF_COD(0x9))
+#define PIC32_PIN_CONF_DG_IN (CONF_DIR(DIR_IN) | CONF_COD(0xA))
+#define PIC32_PIN_CONF_DG_OUT (CONF_DIR(DIR_OUT) | CONF_COD(0xB))
+
+/* change notification trigger type */
+#define PIC32_CN_RISING 1
+#define PIC32_CN_FALLING 2
+#define PIC32_CN_BOTH 3
+
+#endif /* __DT_BINDINGS_PIC32MZDA_PINCTRL_H__ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 09/14] DEVICETREE: Add bindings for PIC32 usart driver
2015-11-21 0:17 [PATCH 00/14] Initial Microchip PIC32MZDA Support Joshua Henderson
` (3 preceding siblings ...)
2015-11-21 0:17 ` [PATCH 07/14] DEVICETREE: Add bindings for PIC32 pin control and GPIO Joshua Henderson
@ 2015-11-21 0:17 ` Joshua Henderson
2015-11-21 15:20 ` Sergei Shtylyov
2015-11-22 21:56 ` Rob Herring
2015-11-21 0:17 ` [PATCH 12/14] DEVICETREE: Add bindings for PIC32 SDHC host controller Joshua Henderson
2015-11-21 0:17 ` [PATCH 13/14] MIPS: dts: Add initial DTS for the PIC32MZDA Starter Kit Joshua Henderson
6 siblings, 2 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-11-21 0:17 UTC (permalink / raw)
To: linux-kernel
Cc: linux-mips, Andrei Pistirica, Joshua Henderson, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, devicetree
From: Andrei Pistirica <andrei.pistirica@microchip.com>
Document the devicetree bindings for the USART peripheral found on
Microchip PIC32 class devices.
Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
---
.../bindings/serial/microchip,pic32-usart.txt | 29 ++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt b/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
new file mode 100644
index 0000000..c87321c
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
@@ -0,0 +1,29 @@
+* Microchip Universal Synchronous Asynchronous Receiver/Transmitter (USART)
+
+Required properties:
+- compatible: Should be "microchip,pic32-usart"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt
+- pinctrl: Should contain pinctrl for TX/RX/RTS/CTS
+
+Optional properties:
+- microchip,uart-has-rtscts : Indicate the uart has hardware flow control
+- rts-gpios: RTS pin for USP-based UART if microchip,uart-has-rtscts
+- cts-gpios: CTS pin for USP-based UART if microchip,uart-has-rtscts
+
+Example:
+ usart0: serial@1f822000 {
+ compatible = "microchip,pic32-usart";
+ reg = <0x1f822000 0x50>;
+ interrupts = <UART1_FAULT DEFAULT_INT_PRI IRQ_TYPE_NONE>,
+ <UART1_RECEIVE_DONE DEFAULT_INT_PRI IRQ_TYPE_NONE>,
+ <UART1_TRANSFER_DONE DEFAULT_INT_PRI IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_uart1
+ &pinctrl_uart1_cts
+ &pinctrl_uart1_rts>;
+ microchip,uart-has-rtscts;
+ cts-gpios = <&pioB 15 0>;
+ rts-gpios = <&pioD 1 0>;
+ };
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 12/14] DEVICETREE: Add bindings for PIC32 SDHC host controller
2015-11-21 0:17 [PATCH 00/14] Initial Microchip PIC32MZDA Support Joshua Henderson
` (4 preceding siblings ...)
2015-11-21 0:17 ` [PATCH 09/14] DEVICETREE: Add bindings for PIC32 usart driver Joshua Henderson
@ 2015-11-21 0:17 ` Joshua Henderson
2015-11-21 15:19 ` Sergei Shtylyov
2015-11-22 21:57 ` Rob Herring
2015-11-21 0:17 ` [PATCH 13/14] MIPS: dts: Add initial DTS for the PIC32MZDA Starter Kit Joshua Henderson
6 siblings, 2 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-11-21 0:17 UTC (permalink / raw)
To: linux-kernel
Cc: linux-mips, Andrei Pistirica, Joshua Henderson, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, devicetree
From: Andrei Pistirica <andrei.pistirica@microchip.com>
Document the devicetree bindings for the SDHC peripheral found on
Microchip PIC32 class devices.
Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
---
.../devicetree/bindings/mmc/sdhci-pic32.txt | 24 ++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
new file mode 100644
index 0000000..f16388c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
@@ -0,0 +1,24 @@
+* Microchip PIC32 SDHCI Controller
+
+This file documents differences between the core properties in mmc.txt
+and the properties used by the sdhci-pic32 driver.
+
+Required properties:
+- compatible: Should be "microchip,pic32-sdhci"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt
+- pinctrl: Should contain pinctrl for data and command lines
+
+Optional properties:
+- no-1-8-v: 1.8V voltage selection not supported
+- piomode: disable DMA support
+
+Example:
+
+ sdhci@1f8ec000 {
+ compatible = "microchip,pic32-sdhci";
+ reg = <0x1f8ec000 0x100>;
+ interrupts = <SDHC_EVENT DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&REFCLKO4>, <&PBCLK5>;
+ clock-names = "base_clk", "sys_clk";
+ };
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 13/14] MIPS: dts: Add initial DTS for the PIC32MZDA Starter Kit
2015-11-21 0:17 [PATCH 00/14] Initial Microchip PIC32MZDA Support Joshua Henderson
` (5 preceding siblings ...)
2015-11-21 0:17 ` [PATCH 12/14] DEVICETREE: Add bindings for PIC32 SDHC host controller Joshua Henderson
@ 2015-11-21 0:17 ` Joshua Henderson
6 siblings, 0 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-11-21 0:17 UTC (permalink / raw)
To: linux-kernel
Cc: linux-mips, Joshua Henderson, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, Ralf Baechle,
Andrew Bresticker, Paul Burton, devicetree
This adds basic DTS configuration for the PIC32MZDA and in turn the
PIC32MZDA Starter Kit.
Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
---
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/pic32/Makefile | 12 ++
arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi | 251 ++++++++++++++++++++++++
arch/mips/boot/dts/pic32/pic32mzda.dtsi | 280 +++++++++++++++++++++++++++
arch/mips/boot/dts/pic32/pic32mzda_sk.dts | 150 ++++++++++++++
arch/mips/pic32/Kconfig | 16 ++
6 files changed, 710 insertions(+)
create mode 100644 arch/mips/boot/dts/pic32/Makefile
create mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
create mode 100644 arch/mips/boot/dts/pic32/pic32mzda.dtsi
create mode 100644 arch/mips/boot/dts/pic32/pic32mzda_sk.dts
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index a0bf516..fc7a0a9 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ dts-dirs += ingenic
dts-dirs += lantiq
dts-dirs += mti
dts-dirs += netlogic
+dts-dirs += pic32
dts-dirs += qca
dts-dirs += ralink
dts-dirs += xilfpga
diff --git a/arch/mips/boot/dts/pic32/Makefile b/arch/mips/boot/dts/pic32/Makefile
new file mode 100644
index 0000000..7ac7905
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/Makefile
@@ -0,0 +1,12 @@
+dtb-$(CONFIG_DTB_PIC32_MZDA_SK) += pic32mzda_sk.dtb
+
+dtb-$(CONFIG_DTB_PIC32_NONE) += \
+ pic32mzda_sk.dtb
+
+obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+
+# Force kbuild to make empty built-in.o if necessary
+obj- += dummy.o
+
+always := $(dtb-y)
+clean-files := *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
new file mode 100644
index 0000000..fa1d2bb
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
@@ -0,0 +1,251 @@
+/*
+ * Device Tree Source for PIC32MZDA clock data
+ *
+ * Purna Chandra Mandal <purna.mandal@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/* all fixed rate clocks */
+
+/ {
+ POSC:posc_clk { /* On-chip primary oscillator */
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ FRC:frc_clk { /* internal FRC oscillator */
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <8000000>;
+ };
+
+ BFRC:bfrc_clk { /* internal backup FRC oscillator */
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <8000000>;
+ };
+
+ LPRC:lprc_clk { /* internal low-power FRC oscillator */
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ /* UPLL provides UTMI clock to USBCORE */
+ UPLL:usb_phy_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "usbphy_clk";
+ };
+
+ TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000000>;
+ status = "disabled";
+ };
+
+ /* external clock input on REFCLKIx pin */
+ REFIx:refix_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ /* PIC32 specific clks */
+ pic32_clktree {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1f801200 0x200>;
+ compatible = "microchip,pic32-clk";
+ interrupts = <12>;
+ ranges;
+
+ /* secondary oscillator; external input on SOSCI pin */
+ SOSC:sosc_clk {
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-sosc";
+ clock-frequency = <32768>;
+ reg = <0x1f801200 0x10 /* enable reg */
+ 0x1f8013d0 0x10>; /* status reg */
+ microchip,bit-mask = <0x02>; /* enable mask */
+ microchip,status-bit-mask = <0x10>; /* status-mask*/
+ };
+
+ FRCDIV:frcdiv_clk {
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-frcdivclk";
+ clocks = <&FRC>;
+ clock-output-names = "frcdiv_clk";
+ };
+
+ /* System PLL clock */
+ SYSPLL:spll_clk {
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-syspll";
+ reg = <0x1f801220 0x10 /* SPLL register */
+ 0x1f8013d0 0x10>; /* CLKSTAT register */
+ clocks = <&POSC>, <&FRC>;
+ clock-output-names = "sys_pll";
+ microchip,status-bit-mask = <0x80>; /* SPLLRDY */
+ };
+
+ /* system clock; mux with postdiv & slew */
+ SYSCLK:sys_clk {
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-sysclk-v2";
+ reg = <0x1f8013c0 0x04>; /* SLEWCON */
+ clocks = <&FRCDIV>, <&SYSPLL>, <&POSC>, <&SOSC>,
+ <&LPRC>, <&FRCDIV>;
+ microchip,clock-indices = <0>, <1>, <2>, <4>, <5>, <7>;
+ clock-output-names = "sys_clk";
+ };
+
+ /* DDR Ctrl & DDR PHY PLL */
+ MPLL: CLK_MPLL {
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-mpll";
+ reg = <0x1f800100 0x04>; /* CFGMPLL */
+ clocks = <&POSC>;
+ clock-output-names = "pic32-mpll";
+ status = "disabled";
+ };
+
+ /* Peripheral bus1 clock */
+ PBCLK1:pb1_clk {
+ reg = <0x1f801340 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ clock-output-names = "pb1_clk";
+ /* used by system modules, not gateable */
+ microchip,ignore-unused;
+ };
+
+ /* Peripheral bus2 clock */
+ PBCLK2:pb2_clk {
+ reg = <0x1f801350 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ clock-output-names = "pb2_clk";
+ /* avoid gating even if unused */
+ microchip,ignore-unused;
+ };
+
+ /* Peripheral bus3 clock */
+ PBCLK3:pb3_clk {
+ reg = <0x1f801360 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ clock-output-names = "pb3_clk";
+ };
+
+ /* Peripheral bus4 clock(I/O ports, GPIO) */
+ PBCLK4:pb4_clk {
+ reg = <0x1f801370 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ clock-output-names = "pb4_clk";
+ };
+
+ /* Peripheral bus clock */
+ PBCLK5:pb5_clk {
+ reg = <0x1f801380 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ clock-output-names = "pb5_clk";
+ };
+
+ /* Peripheral Bus6 clock; */
+ PBCLK6:pb6_clk {
+ reg = <0x1f801390 0x10>;
+ compatible = "microchip,pic32-pbclk";
+ clocks = <&SYSCLK>;
+ #clock-cells = <0>;
+ };
+
+ /* Peripheral bus7 clock */
+ PBCLK7:pb7_clk {
+ reg = <0x1f8013A0 0x10>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-pbclk";
+ /* CPU is driven by this clock; so named */
+ clock-output-names = "cpu_clk";
+ clocks = <&SYSCLK>;
+ };
+
+ /* Reference Oscillator clock for SPI/I2S */
+ REFCLKO1:refo1_clk {
+ reg = <0x1f801280 0x20>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-refoclk";
+ clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
+ <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
+ microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
+ <5>, <7>, <8>, <9>;
+ clock-output-names = "refo1_clk";
+ clock-frequency = <10000000>; /* 10Mhz for I2S MCLK */
+ };
+
+ /* Reference Oscillator clock for SQI */
+ REFCLKO2:refo2_clk {
+ reg = <0x1f8012A0 0x20>;
+ #clock-cells = <0>;
+ compatible = "microchip,pic32-refoclk";
+ clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
+ <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
+ microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
+ <5>, <7>, <8>, <9>;
+ clock-output-names = "refo2_clk";
+ clock-frequency = <50000000>; /* 50MHz for SQI */
+ };
+
+ /* Reference Oscillator clock, ADC */
+ REFCLKO3:refo3_clk {
+ reg = <0x1f8012C0 0x20>;
+ compatible = "microchip,pic32-refoclk";
+ clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
+ <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
+ microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
+ <5>, <7>, <8>, <9>;
+ #clock-cells = <0>;
+ clock-output-names = "refo3_clk";
+ clock-frequency = <10000000>; /* 1Mhz */
+ };
+
+ /* Reference Oscillator clock */
+ REFCLKO4:refo4_clk {
+ reg = <0x1f8012E0 0x20>;
+ compatible = "microchip,pic32-refoclk";
+ clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
+ <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
+ microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
+ <5>, <7>, <8>, <9>;
+ #clock-cells = <0>;
+ clock-output-names = "refo4_clk";
+ clock-frequency = <25000000>; /* 25Mhz */
+ };
+
+ /* Reference Oscillator clock, LCD */
+ REFCLKO5:refo5_clk {
+ reg = <0x1f801300 0x20>;
+ compatible = "microchip,pic32-refoclk";
+ clocks = <&SYSCLK>,<&PBCLK1>,<&POSC>,<&FRC>,<&LPRC>,
+ <&SOSC>,<&SYSPLL>,<&REFIx>,<&BFRC>;
+ microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
+ <5>, <7>, <8>, <9>;
+ #clock-cells = <0>;
+ clock-output-names = "refo5_clk";
+ clock-frequency = <40000000>; /* 40Mhz */
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/pic32/pic32mzda.dtsi b/arch/mips/boot/dts/pic32/pic32mzda.dtsi
new file mode 100644
index 0000000..08d3156
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/pic32mzda.dtsi
@@ -0,0 +1,280 @@
+/*
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/microchip,pic32mz-evic.h>
+
+#include "pic32mzda-clk.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&evic>;
+
+ aliases {
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ gpio2 = &pioC;
+ gpio3 = &pioD;
+ gpio4 = &pioE;
+ gpio5 = &pioF;
+ gpio6 = &pioG;
+ gpio7 = &pioH;
+ gpio8 = &pioJ;
+ gpio9 = &pioK;
+ serial1 = &usart2;
+ serial3 = &usart4;
+ serial5 = &usart6;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mti,mips14KEc";
+ device_type = "cpu";
+ };
+ };
+
+ evic: interrupt-controller@1f810000 {
+ compatible = "microchip,evic-v2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x1f810000 0x1000>;
+ device_type="evic-v2";
+ };
+
+ pic32_pinctrl: pinctrl@1f800000{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #gpio-range-cells = <3>;
+ compatible = "microchip,pic32-pinctrl", "simple-bus";
+ ranges;
+ reg = <0x1f801400 0x100>, /* in */
+ <0x1f801500 0x200>; /* out */
+ clocks = <&PBCLK1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pic32_pinctrl 0 0 32
+ &pic32_pinctrl 0 32 32
+ &pic32_pinctrl 0 64 32
+ &pic32_pinctrl 0 96 32
+ &pic32_pinctrl 0 128 32
+ &pic32_pinctrl 0 160 32
+ &pic32_pinctrl 0 192 32
+ &pic32_pinctrl 0 224 32
+ &pic32_pinctrl 0 256 32
+ &pic32_pinctrl 0 288 32>;
+
+ /* GPIO banks */
+ pioA: gpio@1f860000 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860000 0x24>;
+ interrupts = <PORTA_INPUT_CHANGE_INTERRUPT
+ DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&PBCLK4>;
+ };
+
+ pioB: gpio@1f860100 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860100 0x24>;
+ interrupts = <PORTB_INPUT_CHANGE_INTERRUPT
+ DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&PBCLK4>;
+ };
+
+ pioC: gpio@1f860200 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860200 0x24>;
+ interrupts = <PORTC_INPUT_CHANGE_INTERRUPT
+ DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&PBCLK4>;
+ };
+
+ pioD: gpio@1f860300 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860300 0x24>;
+ interrupts = <PORTD_INPUT_CHANGE_INTERRUPT
+ DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&PBCLK4>;
+ };
+
+ pioE: gpio@1f860400 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860400 0x24>;
+ interrupts = <PORTE_INPUT_CHANGE_INTERRUPT
+ DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&PBCLK4>;
+ };
+
+ pioF: gpio@1f860500 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860500 0x24>;
+ interrupts = <PORTF_INPUT_CHANGE_INTERRUPT
+ DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&PBCLK4>;
+ };
+
+ pioG: gpio@1f860600 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860600 0x24>;
+ interrupts = <PORTG_INPUT_CHANGE_INTERRUPT
+ DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&PBCLK4>;
+ };
+
+ pioH: gpio@1f860700 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860700 0x24>;
+ interrupts = <PORTH_INPUT_CHANGE_INTERRUPT
+ DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&PBCLK4>;
+ };
+
+ /* There is no pioI */
+
+ pioJ: gpio@1f860800 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860800 0x24>;
+ interrupts = <PORTJ_INPUT_CHANGE_INTERRUPT
+ DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&PBCLK4>;
+ };
+
+ pioK: gpio@1f860900 {
+ compatible = "microchip,pic32-gpio";
+ reg = <0x1f860900 0x24>;
+ interrupts = <PORTK_INPUT_CHANGE_INTERRUPT
+ DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&PBCLK4>;
+ };
+ };
+
+ sdhci: sdhci@1f8ec000 {
+ compatible = "microchip,pic32-sdhci";
+ reg = <0x1f8ec000 0x100>;
+ interrupts = <SDHC_EVENT DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&REFCLKO4>, <&PBCLK5>;
+ clock-names = "base_clk", "sys_clk";
+ no-1-8-v;
+ status = "disabled";
+ };
+
+ usart1: serial@1f822000 {
+ compatible = "microchip,pic32-usart";
+ reg = <0x1f822000 0x50>;
+ interrupts = <UART1_FAULT DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>,
+ <UART1_RECEIVE_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>,
+ <UART1_TRANSFER_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&PBCLK2>;
+ status = "disabled";
+ };
+
+ usart2: serial@1f822200 {
+ compatible = "microchip,pic32-usart";
+ reg = <0x1f822200 0x50>;
+ interrupts = <UART2_FAULT DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>,
+ <UART2_RECEIVE_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>,
+ <UART2_TRANSFER_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&PBCLK2>;
+ status = "disabled";
+ };
+
+ usart3: serial@1f822400 {
+ compatible = "microchip,pic32-usart";
+ reg = <0x1f822400 0x50>;
+ interrupts = <UART3_FAULT DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>,
+ <UART3_RECEIVE_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>,
+ <UART3_TRANSFER_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&PBCLK2>;
+ status = "disabled";
+ };
+
+ usart4: serial@1f822600 {
+ compatible = "microchip,pic32-usart";
+ reg = <0x1f822600 0x50>;
+ interrupts = <UART4_FAULT DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>,
+ <UART4_RECEIVE_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>,
+ <UART4_TRANSFER_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&PBCLK2>;
+ status = "disabled";
+ };
+
+ usart5: serial@1f822800 {
+ compatible = "microchip,pic32-usart";
+ reg = <0x1f822800 0x50>;
+ interrupts = <UART5_FAULT DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>,
+ <UART5_RECEIVE_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>,
+ <UART5_TRANSFER_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&PBCLK2>;
+ status = "disabled";
+ };
+
+ usart6: serial@1f822A00 {
+ compatible = "microchip,pic32-usart";
+ reg = <0x1f822A00 0x50>;
+ interrupts = <UART6_FAULT DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>,
+ <UART6_RECEIVE_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>,
+ <UART6_TRANSFER_DONE DEFAULT_INT_PRI
+ IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&PBCLK2>;
+ status = "disabled";
+ };
+};
diff --git a/arch/mips/boot/dts/pic32/pic32mzda_sk.dts b/arch/mips/boot/dts/pic32/pic32mzda_sk.dts
new file mode 100644
index 0000000..5c62228
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/pic32mzda_sk.dts
@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pic32mzda.h>
+
+#include "pic32mzda.dtsi"
+
+/ {
+ compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda";
+ model = "Microchip PIC32MZDA Starter Kit";
+
+ memory {
+ device_type = "memory";
+ reg = <0x08000000 0x08000000>;
+ };
+
+ chosen {
+ bootargs = "earlyprintk=ttyS1,115200n8r console=ttyS1,115200n8";
+ };
+
+ leds0 {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds_s0>;
+
+ led@1 {
+ label = "pic32mzda_sk:red:led1";
+ gpios = <&pioH 0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led@2 {
+ label = "pic32mzda_sk:yellow:led2";
+ gpios = <&pioH 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+
+ led@3 {
+ label = "pic32mzda_sk:green:led3";
+ gpios = <&pioH 2 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ keys0 {
+ compatible = "gpio-keys-polled";
+ pinctrl-0 = <&user_buttons_s0>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <300>;
+
+ button@sw1 {
+ label = "ESC";
+ linux,code = <1>;
+ gpios = <&pioB 12 0>;
+ };
+
+ button@sw2 {
+ label = "Home";
+ linux,code = <102>;
+ gpios = <&pioB 13 0>;
+ };
+
+ button@sw3 {
+ label = "Menu";
+ linux,code = <139>;
+ gpios = <&pioB 14 0>;
+ };
+ };
+};
+
+&usart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&sdhci {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhc1>;
+ status = "okay";
+};
+
+&pic32_pinctrl {
+
+ sdhc1 {
+ pinctrl_sdhc1: sdhc1_pins0 {
+ /* SDCLK */
+ pic32,single-pins = <PORT_A 6 PIC32_PIN_CONF_DG>,
+ <PORT_D 4 PIC32_PIN_CONF_DG>, /* SDCMD */
+ <PORT_G 13 PIC32_PIN_CONF_DG>, /* SDDATA0 */
+ <PORT_G 12 PIC32_PIN_CONF_DG>, /* SDDATA1 */
+ <PORT_G 14 PIC32_PIN_CONF_DG>, /* SDDATA2 */
+ <PORT_A 7 PIC32_PIN_CONF_DG>, /* SDDATA3 */
+ <PORT_A 0 PIC32_PIN_CONF_DG>; /* SDCD */
+ };
+ };
+
+ leds {
+
+ user_leds_s0: user_leds_s0 {
+ pic32,single-pins = <PORT_H 0 PIC32_PIN_CONF_DG_OUT
+ PORT_H 1 PIC32_PIN_CONF_DG_OUT
+ PORT_H 2 PIC32_PIN_CONF_DG_OUT>;
+ };
+ };
+
+ buttons0 {
+ user_buttons_s0: user_buttons_s0 {
+ pic32,single-pins = <PORT_B 12 PIC32_PIN_CONF_PU_IN
+ PORT_B 13 PIC32_PIN_CONF_PU_IN
+ PORT_B 14 PIC32_PIN_CONF_PU_IN>;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2: uart2-0 {
+ pic32,pins = <PIC32_RP_OUT_RPG9 PIC32_PP_OUT_U2TX
+ PIC32_PIN_CONF_DG_OUT
+ PIC32_RP_IN_RPB0 PIC32_PP_IN_U2RX
+ PIC32_PIN_CONF_DG_IN>;
+ };
+ };
+
+ uart4 {
+ pinctrl_uart4: uart4-0 {
+ pic32,pins = <PIC32_RP_OUT_RPC3 PIC32_PP_OUT_U4TX
+ PIC32_PIN_CONF_DG_OUT
+ PIC32_RP_IN_RPE8 PIC32_PP_IN_U4RX
+ PIC32_PIN_CONF_DG_IN>;
+ };
+ };
+};
diff --git a/arch/mips/pic32/Kconfig b/arch/mips/pic32/Kconfig
index 0161f09..b1bd7ba 100644
--- a/arch/mips/pic32/Kconfig
+++ b/arch/mips/pic32/Kconfig
@@ -31,4 +31,20 @@ config PIC32MZDA
endchoice
+choice
+ prompt "Devicetree selection"
+ default DTB_PIC32_NONE
+ help
+ Select the devicetree.
+
+config DTB_PIC32_NONE
+ bool "None"
+
+config DTB_PIC32_MZDA_SK
+ bool "PIC32MZDA Starter Kit"
+ depends on PIC32MZDA
+ select BUILTIN_DTB
+
+endchoice
+
endif # MACH_PIC32
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH 12/14] DEVICETREE: Add bindings for PIC32 SDHC host controller
2015-11-21 0:17 ` [PATCH 12/14] DEVICETREE: Add bindings for PIC32 SDHC host controller Joshua Henderson
@ 2015-11-21 15:19 ` Sergei Shtylyov
2015-11-26 4:40 ` Joshua Henderson
2015-11-22 21:57 ` Rob Herring
1 sibling, 1 reply; 29+ messages in thread
From: Sergei Shtylyov @ 2015-11-21 15:19 UTC (permalink / raw)
To: Joshua Henderson, linux-kernel
Cc: linux-mips, Andrei Pistirica, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, devicetree
Hello.
On 11/21/2015 3:17 AM, Joshua Henderson wrote:
> From: Andrei Pistirica <andrei.pistirica@microchip.com>
>
> Document the devicetree bindings for the SDHC peripheral found on
> Microchip PIC32 class devices.
>
> Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
> ---
> .../devicetree/bindings/mmc/sdhci-pic32.txt | 24 ++++++++++++++++++++
> 1 file changed, 24 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
> new file mode 100644
> index 0000000..f16388c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
> @@ -0,0 +1,24 @@
> +* Microchip PIC32 SDHCI Controller
> +
> +This file documents differences between the core properties in mmc.txt
> +and the properties used by the sdhci-pic32 driver.
> +
> +Required properties:
> +- compatible: Should be "microchip,pic32-sdhci"
> +- reg: Should contain registers location and length
> +- interrupts: Should contain interrupt
> +- pinctrl: Should contain pinctrl for data and command lines
This is a required prop, yet the example doesn't contain it?
> +
> +Optional properties:
> +- no-1-8-v: 1.8V voltage selection not supported
> +- piomode: disable DMA support
> +
> +Example:
> +
> + sdhci@1f8ec000 {
> + compatible = "microchip,pic32-sdhci";
> + reg = <0x1f8ec000 0x100>;
> + interrupts = <SDHC_EVENT DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&REFCLKO4>, <&PBCLK5>;
> + clock-names = "base_clk", "sys_clk";
The "clocks" and "clock-names" props are not documented.
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 09/14] DEVICETREE: Add bindings for PIC32 usart driver
2015-11-21 0:17 ` [PATCH 09/14] DEVICETREE: Add bindings for PIC32 usart driver Joshua Henderson
@ 2015-11-21 15:20 ` Sergei Shtylyov
2015-11-22 21:56 ` Rob Herring
1 sibling, 0 replies; 29+ messages in thread
From: Sergei Shtylyov @ 2015-11-21 15:20 UTC (permalink / raw)
To: Joshua Henderson, linux-kernel
Cc: linux-mips, Andrei Pistirica, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, devicetree
Hello.
On 11/21/2015 3:17 AM, Joshua Henderson wrote:
> From: Andrei Pistirica <andrei.pistirica@microchip.com>
>
> Document the devicetree bindings for the USART peripheral found on
> Microchip PIC32 class devices.
>
> Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
> ---
> .../bindings/serial/microchip,pic32-usart.txt | 29 ++++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
>
> diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt b/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
> new file mode 100644
> index 0000000..c87321c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
> @@ -0,0 +1,29 @@
> +* Microchip Universal Synchronous Asynchronous Receiver/Transmitter (USART)
> +
> +Required properties:
> +- compatible: Should be "microchip,pic32-usart"
> +- reg: Should contain registers location and length
> +- interrupts: Should contain interrupt
> +- pinctrl: Should contain pinctrl for TX/RX/RTS/CTS
No such prop in the example.
> +
> +Optional properties:
> +- microchip,uart-has-rtscts : Indicate the uart has hardware flow control
> +- rts-gpios: RTS pin for USP-based UART if microchip,uart-has-rtscts
> +- cts-gpios: CTS pin for USP-based UART if microchip,uart-has-rtscts
> +
> +Example:
> + usart0: serial@1f822000 {
> + compatible = "microchip,pic32-usart";
> + reg = <0x1f822000 0x50>;
> + interrupts = <UART1_FAULT DEFAULT_INT_PRI IRQ_TYPE_NONE>,
> + <UART1_RECEIVE_DONE DEFAULT_INT_PRI IRQ_TYPE_NONE>,
> + <UART1_TRANSFER_DONE DEFAULT_INT_PRI IRQ_TYPE_NONE>;
> + pinctrl-names = "default";
> + pinctrl-0 = <
> + &pinctrl_uart1
> + &pinctrl_uart1_cts
> + &pinctrl_uart1_rts>;
The above 2 props are undocumented.
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller
2015-11-21 0:17 ` [PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller Joshua Henderson
@ 2015-11-21 20:47 ` Arnd Bergmann
2015-11-25 18:22 ` Joshua Henderson
[not found] ` <1448065205-15762-2-git-send-email-joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
1 sibling, 1 reply; 29+ messages in thread
From: Arnd Bergmann @ 2015-11-21 20:47 UTC (permalink / raw)
To: Joshua Henderson
Cc: linux-kernel, linux-mips, Cristian Birsan, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, devicetree
On Friday 20 November 2015 17:17:13 Joshua Henderson wrote:
> +Example
> +-------
> +
> +evic: interrupt-controller@1f810000 {
> + compatible = "microchip,evic-v2";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x1f810000 0x1000>;
> + device_type="evic-v2";
> +};
This is not a correct use of device_type. Just drop that property.
> diff --git a/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h b/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
> new file mode 100644
> index 0000000..2c466b8
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
> @@ -0,0 +1,238 @@
> +/*
> + * This header provides constants for the MICROCHIP PIC32 EVIC.
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_EVIC_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_EVIC_H
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/* Hardware interrupt number */
> +#define CORE_TIMER_INTERRUPT 0
> +#define CORE_SOFTWARE_INTERRUPT_0 1
> +#define CORE_SOFTWARE_INTERRUPT_1 2
> +#define EXTERNAL_INTERRUPT_0 3
> +#define TIMER1 4
A header file like this is just going to make everyone's life
miserable. Try to remove as much as possible here: normally
you can just use the numbers from the data sheet that match
the actual hardware registers, and put them into the dts file.
> +/* Interrupt priority bits */
> +#define PRI_0 0 /* Note:This priority disables the interrupt! */
> +#define PRI_1 1
> +#define PRI_2 2
> +#define PRI_3 3
> +#define PRI_4 4
> +#define PRI_5 5
> +#define PRI_6 6
> +#define PRI_7 7
> +/* Interrupt subpriority bits */
> +#define SUB_PRI_0 0
> +#define SUB_PRI_1 1
> +#define SUB_PRI_2 2
> +#define SUB_PRI_3 3
These are obviously silly and should be removed/
> +#define PRI_MASK 0x7 /* 3 bit priority mask */
> +#define SUBPRI_MASK 0x3 /* 2 bit subpriority mask */
> +#define INT_MASK 0x1F /* 5 bit pri and subpri mask */
> +#define NR_EXT_IRQS 5 /* 5 external interrupts sources */
> +
> +#define MICROCHIP_EVIC_MIN_PRIORITY 0
> +#define MICROCHIP_EVIC_MAX_PRIORITY INT_MASK
> +
> +#define INT_PRI(pri, subpri) \
> + (((pri & PRI_MASK) << 2) | (subpri & SUBPRI_MASK))
> +
> +#define DEFINE_INT(irq, pri) { irq, pri }
> +
> +#define DEFAULT_INT_PRI INT_PRI(2, 0)
Is it required to have a specific priority configured for each line?
If these are software selectable, it's probably better to not put
them into DT in the first place.
If you absolutely need them, I would suggest using two separate cells
for pri and subpri so you can avoid the macro.
Arnd
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation
2015-11-21 0:17 ` [PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation Joshua Henderson
@ 2015-11-21 20:49 ` Arnd Bergmann
2015-11-26 4:05 ` Joshua Henderson
[not found] ` <1448065205-15762-4-git-send-email-joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
1 sibling, 1 reply; 29+ messages in thread
From: Arnd Bergmann @ 2015-11-21 20:49 UTC (permalink / raw)
To: Joshua Henderson
Cc: linux-kernel, linux-mips, Purna Chandra Mandal, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, devicetree
On Friday 20 November 2015 17:17:15 Joshua Henderson wrote:
> +/* PIC32 specific clks */
> +pic32_clktree {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x1f801200 0x200>;
> + compatible = "microchip,pic32-clk";
> + interrupts = <12>;
> + ranges;
> +
> + /* secondary oscillator; external input on SOSCI pin */
> + SOSC:sosc_clk {
> + #clock-cells = <0>;
> + compatible = "microchip,pic32-sosc";
> + clock-frequency = <32768>;
> + reg = <0x1f801200 0x10 /* enable reg */
> + 0x1f801390 0x10>; /* status reg */
> + microchip,bit-mask = <0x02>; /* enable mask */
> + microchip,status-bit-mask = <0x10>; /* status-mask*/
> + };
>
If you want to use the reg property in this way for each cell,
at least use a 'ranges' that only translates the actual registers
like this
ranges = <0 0x1f801200 0x200>
sosc_clk {
...
reg = <0x000 0x10>, <0x190 0x10>;
...
};
Arnd
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller
[not found] ` <1448065205-15762-2-git-send-email-joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
@ 2015-11-22 21:14 ` Rob Herring
2015-11-26 5:01 ` Joshua Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Rob Herring @ 2015-11-22 21:14 UTC (permalink / raw)
To: Joshua Henderson
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Cristian Birsan,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Fri, Nov 20, 2015 at 05:17:13PM -0700, Joshua Henderson wrote:
> From: Cristian Birsan <cristian.birsan-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>
> Document the devicetree bindings for the interrupt controller on Microchip
> PIC32 class devices. This also adds a header defining associated interrupts
> and related settings.
>
> Signed-off-by: Cristian Birsan <cristian.birsan-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
> Signed-off-by: Joshua Henderson <joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
> ---
> .../microchip,pic32mz-evic.txt | 65 ++++++
> .../interrupt-controller/microchip,pic32mz-evic.h | 238 ++++++++++++++++++++
> 2 files changed, 303 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
> create mode 100644 include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
> new file mode 100644
> index 0000000..12fb91f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
> @@ -0,0 +1,65 @@
> +Microchip PIC32MZ Interrupt Controller
> +======================================
> +
> +The Microchip PIC32MZ SOC contains an Enhanced Vectored Interrupt Controller
> +(EVIC) version 2. It handles internal and external interrupts and provides
> +support for priority, sub-priority, irq type and polarity.
> +
> +Required properties
> +-------------------
> +
> +- compatible: Should be "microchip,evic-v2"
This should be more specific like "microchip,pic32mz-evic". You can keep
this one in addition if you like for matching.
Rob
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^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation
[not found] ` <1448065205-15762-4-git-send-email-joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
@ 2015-11-22 21:31 ` Rob Herring
2015-11-26 5:36 ` Joshua Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Rob Herring @ 2015-11-22 21:31 UTC (permalink / raw)
To: Joshua Henderson
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Purna Chandra Mandal,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Fri, Nov 20, 2015 at 05:17:15PM -0700, Joshua Henderson wrote:
> From: Purna Chandra Mandal <purna.mandal-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>
> Document the devicetree bindings for the clock driver found on Microchip
> PIC32 class devices.
>
> Signed-off-by: Purna Chandra Mandal <purna.mandal-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
> Signed-off-by: Joshua Henderson <joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
> ---
> .../devicetree/bindings/clock/microchip,pic32.txt | 263 ++++++++++++++++++++
> 1 file changed, 263 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/microchip,pic32.txt b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
> new file mode 100644
> index 0000000..4cef72d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
> @@ -0,0 +1,263 @@
> +Binding for a Clock hardware block found on
> +certain Microchip PIC32 MCU devices.
> +
> +Microchip SoC clocks-node consists of few oscillators, PLL, multiplexer
> +and few divider nodes.
[...]
> +Required properties:
> +- compatible : should have "microchip,pic32-clk".
> +- reg : A Base address and length of the register set.
> +- interrupts : source of interrupt.
> +
> +Optional properties (for subnodes):
> +- #clock-cells: From common clock binding, should be 0.
> +
> +- microchip,clock-indices: in multiplexer node clock sources always aren't linear
> + and contiguous. This property helps define clock-sources with respect to
> + the mux clock node.
> +
> +- microchip,ignore-unused : ignore gate request even if the gated clock is unused.
There is some discussion about this upstream with "critical-clocks"
binding. Can you use and wait for that?
> +- microchip,status-bit-mask: bitmask for status check. This will be used to confirm
> + particular operation by clock sub-node is completed. It is dependent sub-node.
> +- microchip,bit-mask: enable mask, similar to microchip,status-bit-mask.
We've generally decided not to describe clocks at this level of detail
in DT. It's fine though for simple clock trees. This one seems to be
borderline IMO.
> +- microchip,slew-step: enable frequency slewing(stepping) during rate change;
> + applicable only to sys-clock subnode.
--
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^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 05/14] DEVICETREE: Add bindings for PIC32/MZDA platforms
2015-11-21 0:17 ` [PATCH 05/14] DEVICETREE: Add bindings for PIC32/MZDA platforms Joshua Henderson
@ 2015-11-22 21:35 ` Rob Herring
0 siblings, 0 replies; 29+ messages in thread
From: Rob Herring @ 2015-11-22 21:35 UTC (permalink / raw)
To: Joshua Henderson
Cc: linux-kernel, linux-mips, Pawel Moll, Mark Rutland, Ian Campbell,
Kumar Gala, devicetree
On Fri, Nov 20, 2015 at 05:17:17PM -0700, Joshua Henderson wrote:
> This adds support for the Microchip PIC32 platform along with the
> specific variant PIC32MZDA on a PIC32MZDA Starter Kit.
>
> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/mips/pic32/microchip,pic32mzda.txt | 33 ++++++++++++++++++++
> 1 file changed, 33 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
>
> diff --git a/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt b/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
> new file mode 100644
> index 0000000..bcf3e04
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
> @@ -0,0 +1,33 @@
> +* Microchip PIC32MZDA Platforms
> +
> +PIC32MZDA Starter Kit
> +Required root node properties:
> + - compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda"
> +
> +CPU nodes:
> +----------
> +A "cpus" node is required. Required properties:
> + - #address-cells: Must be 1.
> + - #size-cells: Must be 0.
> +A CPU sub-node is also required. Required properties:
> + - device_type: Must be "cpu".
> + - compatible: Must be "mti,mips14KEc".
> +Example:
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "mti,mips14KEc";
> + };
> + };
> +
> +Boot protocol
This probably belongs somewhere else if it is common.
> +--------------
> +In accordance with the MIPS UHI specification[1], the bootloader must pass the
> +following arguments to the kernel:
> + - $a0: -2.
> + - $a1: KSEG0 address of the flattened device-tree blob.
> +
> +[1] http://prplfoundation.org/wiki/MIPS_documentation
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 07/14] DEVICETREE: Add bindings for PIC32 pin control and GPIO
2015-11-21 0:17 ` [PATCH 07/14] DEVICETREE: Add bindings for PIC32 pin control and GPIO Joshua Henderson
@ 2015-11-22 21:47 ` Rob Herring
2015-12-04 13:02 ` Andrei.Pistirica
2015-12-08 22:13 ` Joshua Henderson
0 siblings, 2 replies; 29+ messages in thread
From: Rob Herring @ 2015-11-22 21:47 UTC (permalink / raw)
To: Joshua Henderson
Cc: linux-kernel, linux-mips, Andrei Pistirica, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, devicetree
On Fri, Nov 20, 2015 at 05:17:19PM -0700, Joshua Henderson wrote:
> From: Andrei Pistirica <andrei.pistirica@microchip.com>
>
> Document the devicetree bindings for PINCTRL and GPIO found on Microchip
> PIC32 class devices. This also adds a header defining related port and
> peripheral pin select functionality.
>
> Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
> ---
> .../bindings/gpio/microchip,pic32-gpio.txt | 33 ++
> .../bindings/pinctrl/microchip,pic32-pinctrl.txt | 100 +++++
> include/dt-bindings/pinctrl/pic32mzda.h | 404 ++++++++++++++++++++
> 3 files changed, 537 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
> create mode 100644 include/dt-bindings/pinctrl/pic32mzda.h
>
> diff --git a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
> new file mode 100644
> index 0000000..f6eeb2f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
> @@ -0,0 +1,33 @@
> +* Microchip PIC32 GPIO devices (PIO).
> +
> +Required properties:
> + - compatible: "microchip,pic32-gpio"
This should have a chip specific compatible string.
> + - reg: Base address and length for the device.
> + - interrupts: The port interrupt shared be all pins.
> + - gpio-controller: Marks the port as GPIO controller.
> + - #gpio-cells: Two. The first cell is the pin number and
> + the second cell is unused.
> + - interrupt-controller: Marks the device node as an interrupt controller.
> + - #interrupt-cells: Two. The first cell is the GPIO number and second cell
> + is used to specify the trigger type:
> + PIC32_PIN_CN_RISING : low-to-high edge triggered.
> + PIC32_PIN_CN_FALLING : high-to-low edge triggered.
> + PIC32_PIN_CN_BOTH : low-to-high and high-to-low edges triggered.
Can't you use the standard flags?
> +
> +Note:
> + - If gpio-ranges is missing, then all the pins (32) related to the gpio bank
> + are enabled.
> +
> +Example:
> + pioA: gpio@1f860000 {
> + compatible = "microchip,pic32-gpio";
> + reg = <0x1f860000 0x24>;
> + interrupts = <PORTA_INPUT_CHANGE_INTERRUPT
> + DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&pic32_pinctrl 0 0 32>;
> + clocks = <&PBCLK4>;
> + };
> diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
> new file mode 100644
> index 0000000..7cf4167
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
> @@ -0,0 +1,100 @@
> +* Microchip PIC32 Pinmux device.
> +
> +Please refer to pinctrl-bindings.txt for details of the pinctrl properties and
> +common bindings.
> +
> +PIC32 'pin configuration node' is a node of a group of pins which can be
> +used for a specific device or function. This node represents configuraions of
> +single pins or a pairs of mux and related configuration.
> +
> +Required properties for pic32 device:
> + - compatible: "microchip,pic32-pinctrl", "microchip,pic32mz-pinctrl"
Is this both or either one. For both, it should be most specific first.
> + - reg: Base address and length for pps:in and pps:out registers.
> +
> +Properties for 'pin configuration node':
> + - pic32,pins: each entry consists of 3 intergers and represents the mux and
> + config settings for one pin. The first integer represent the remappable pin,
> + the second represent the peripheral pin and the last the configuration.
> + The format is pic32,pins = <PIC32_RP_'dir'_'pin'
> + PIC32_PP_'dir'_'peripherl-pin' PIC32_PIN_CONF_'config'>. The configurations
> + are divided in 2 classes: IN and OUT and each in 4 buckets. Each entry must
> + contains items from the same class and bucket, otherwise the driver will
> + notify an error and the initialization will fail.
> + - pic32,single-pins: each entry consists of 3 intergers and represents a pin
> + (that is not remappable) and related configuraion. The format is
> + pic32,single-pins = <PORT_'x' 'pin' PIC32_PIN_CONF_'config'>. Each port has
> + 32 pins and please refer to chip documentation for details of remappable
> + pins.
> +
> +Available pin configurations (refer to dt-bindings/pinctrl/pic32.h):
> + PIC32_PIN_CONF_NONE : no configuration (default).
> + PIC32_PIN_CONF_OD : indicate this pin need a open-drain (no direction).
> + PIC32_PIN_CONF_OD_OUT : indicate this pin need a open-drain out.
> + PIC32_PIN_CONF_PU : indicate this pin need a pull up (no direction).
> + PIC32_PIN_CONF_PU_IN : indicate this pin need a pull up in.
> + PIC32_PIN_CONF_PD : indicate this pin need a pull down (no direction).
> + PIC32_PIN_CONF_PD_IN : indicate this pin need a pull down input.
> + PIC32_PIN_CONF_AN : indicate this pin as analogic (no direction).
> + PIC32_PIN_CONF_AN_IN : indicate this pin as analogic input.
> + PIC32_PIN_CONF_DG : indicate this pin as digital (no direction).
> + PIC32_PIN_CONF_DG_IN : indicate this pin as digital input.
> + PIC32_PIN_CONF_DG_OUT : indicate this pin as digital output.
> +
> +NOTEs:
> +1. The pins functions nods are defined under pic32 pinctrl node. The function's
> + pin groups are defined under functions node.
> +2. Each pin group can have both pic32,pins and pic32,single-pins properties to
> + specify re-mappable or non-remappable pins with related mux and configs or
> + at least one.
> +3. Each pin configuration node can have a phandle and devices can set pins
> + configurations by referring to the phandle of that pin configuration node.
> +4. The pinctrl bindings are listed in dt-bindings/pinctrl/pic32.h.
> +5. The gpio controller must be described in the pinctrl simple-bus.
> +
> +Example:
> +pinctrl@1f800000{
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "microchip,pic32-pinctrl", "simple-bus";
> + ranges;
> + reg = <0x1f801404 0x3c>, /* in */
> + <0x1f801538 0x57>; /* out */
> +
> + pioA: gpio@1f860000 {
> + compatible = "microchip,pic32-gpio";
The gpio controller is a sub-function of the pinctrl? That doesn't
really seem to be the case based on the addresses.
> + reg = <0x1f860000 0x24>;
> + gpio-controller;
> + };
> +
> + /* functions */
> + sw1 {
> + pinctrl_sw1: sw1-0 {
> + pic32,single-pins = <PORT_B 12 PIC32_PIN_CONF_PULLUP>;
Why isn't this using standard pinctrl properties?
> + };
> + };
> +
> + uart1 {
> + pinctrl_uart1: uart1-0 {
> + pic32,pins =
> + <PIC32_RP_OUT_RPG7 PIC32_PP_OUT_U1TX PIC32_PIN_CONF_NONE
> + PIC32_RP_IN_RPG8 PIC32_PP_IN_U1RX PIC32_PIN_CONF_NONE>;
> + };
> + };
> +};
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 09/14] DEVICETREE: Add bindings for PIC32 usart driver
2015-11-21 0:17 ` [PATCH 09/14] DEVICETREE: Add bindings for PIC32 usart driver Joshua Henderson
2015-11-21 15:20 ` Sergei Shtylyov
@ 2015-11-22 21:56 ` Rob Herring
2015-12-11 16:16 ` Joshua Henderson
1 sibling, 1 reply; 29+ messages in thread
From: Rob Herring @ 2015-11-22 21:56 UTC (permalink / raw)
To: Joshua Henderson
Cc: linux-kernel, linux-mips, Andrei Pistirica, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, devicetree
On Fri, Nov 20, 2015 at 05:17:21PM -0700, Joshua Henderson wrote:
> From: Andrei Pistirica <andrei.pistirica@microchip.com>
>
> Document the devicetree bindings for the USART peripheral found on
> Microchip PIC32 class devices.
>
> Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
> ---
> .../bindings/serial/microchip,pic32-usart.txt | 29 ++++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
>
> diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt b/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
> new file mode 100644
> index 0000000..c87321c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
> @@ -0,0 +1,29 @@
> +* Microchip Universal Synchronous Asynchronous Receiver/Transmitter (USART)
> +
> +Required properties:
> +- compatible: Should be "microchip,pic32-usart"
Again, should be more specific.
> +- reg: Should contain registers location and length
> +- interrupts: Should contain interrupt
> +- pinctrl: Should contain pinctrl for TX/RX/RTS/CTS
> +
> +Optional properties:
> +- microchip,uart-has-rtscts : Indicate the uart has hardware flow control
> +- rts-gpios: RTS pin for USP-based UART if microchip,uart-has-rtscts
> +- cts-gpios: CTS pin for USP-based UART if microchip,uart-has-rtscts
This appears to just be copied for Sirf UART.
Doesn't *-gpios being present imply having h/w
flow-control (i.e. microchip,uart-has-rtscts)?
Rob
> +
> +Example:
> + usart0: serial@1f822000 {
> + compatible = "microchip,pic32-usart";
> + reg = <0x1f822000 0x50>;
> + interrupts = <UART1_FAULT DEFAULT_INT_PRI IRQ_TYPE_NONE>,
> + <UART1_RECEIVE_DONE DEFAULT_INT_PRI IRQ_TYPE_NONE>,
> + <UART1_TRANSFER_DONE DEFAULT_INT_PRI IRQ_TYPE_NONE>;
> + pinctrl-names = "default";
> + pinctrl-0 = <
> + &pinctrl_uart1
> + &pinctrl_uart1_cts
> + &pinctrl_uart1_rts>;
> + microchip,uart-has-rtscts;
> + cts-gpios = <&pioB 15 0>;
> + rts-gpios = <&pioD 1 0>;
> + };
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 12/14] DEVICETREE: Add bindings for PIC32 SDHC host controller
2015-11-21 0:17 ` [PATCH 12/14] DEVICETREE: Add bindings for PIC32 SDHC host controller Joshua Henderson
2015-11-21 15:19 ` Sergei Shtylyov
@ 2015-11-22 21:57 ` Rob Herring
2015-11-26 5:16 ` Joshua Henderson
1 sibling, 1 reply; 29+ messages in thread
From: Rob Herring @ 2015-11-22 21:57 UTC (permalink / raw)
To: Joshua Henderson
Cc: linux-kernel, linux-mips, Andrei Pistirica, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, devicetree
On Fri, Nov 20, 2015 at 05:17:24PM -0700, Joshua Henderson wrote:
> From: Andrei Pistirica <andrei.pistirica@microchip.com>
>
> Document the devicetree bindings for the SDHC peripheral found on
> Microchip PIC32 class devices.
>
> Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
> ---
> .../devicetree/bindings/mmc/sdhci-pic32.txt | 24 ++++++++++++++++++++
> 1 file changed, 24 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
> new file mode 100644
> index 0000000..f16388c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
> @@ -0,0 +1,24 @@
> +* Microchip PIC32 SDHCI Controller
> +
> +This file documents differences between the core properties in mmc.txt
> +and the properties used by the sdhci-pic32 driver.
> +
> +Required properties:
> +- compatible: Should be "microchip,pic32-sdhci"
> +- reg: Should contain registers location and length
> +- interrupts: Should contain interrupt
> +- pinctrl: Should contain pinctrl for data and command lines
> +
> +Optional properties:
> +- no-1-8-v: 1.8V voltage selection not supported
There's a standard property for this one.
> +- piomode: disable DMA support
Proably this one too IIRC.
> +
> +Example:
> +
> + sdhci@1f8ec000 {
> + compatible = "microchip,pic32-sdhci";
> + reg = <0x1f8ec000 0x100>;
> + interrupts = <SDHC_EVENT DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&REFCLKO4>, <&PBCLK5>;
> + clock-names = "base_clk", "sys_clk";
> + };
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller
2015-11-21 20:47 ` Arnd Bergmann
@ 2015-11-25 18:22 ` Joshua Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-11-25 18:22 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-kernel, linux-mips, Cristian Birsan, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, devicetree
On 11/21/2015 1:47 PM, Arnd Bergmann wrote:
> On Friday 20 November 2015 17:17:13 Joshua Henderson wrote:
>
>> +Example
>> +-------
>> +
>> +evic: interrupt-controller@1f810000 {
>> + compatible = "microchip,evic-v2";
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + reg = <0x1f810000 0x1000>;
>> + device_type="evic-v2";
>> +};
>
> This is not a correct use of device_type. Just drop that property.
Ack.
>
>> diff --git a/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h b/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
>> new file mode 100644
>> index 0000000..2c466b8
>> --- /dev/null
>> +++ b/include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
>> @@ -0,0 +1,238 @@
>> +/*
>> + * This header provides constants for the MICROCHIP PIC32 EVIC.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_EVIC_H
>> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_EVIC_H
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +/* Hardware interrupt number */
>> +#define CORE_TIMER_INTERRUPT 0
>> +#define CORE_SOFTWARE_INTERRUPT_0 1
>> +#define CORE_SOFTWARE_INTERRUPT_1 2
>> +#define EXTERNAL_INTERRUPT_0 3
>> +#define TIMER1 4
>
> A header file like this is just going to make everyone's life
> miserable. Try to remove as much as possible here: normally
> you can just use the numbers from the data sheet that match
> the actual hardware registers, and put them into the dts file.
>
Agreed. Removing these defines along with removing the priorities from the bindings as suggested makes sense. With doing that, this header file becomes pointless and it will be dropped.
>> +/* Interrupt priority bits */
>> +#define PRI_0 0 /* Note:This priority disables the interrupt! */
>> +#define PRI_1 1
>> +#define PRI_2 2
>> +#define PRI_3 3
>> +#define PRI_4 4
>> +#define PRI_5 5
>> +#define PRI_6 6
>> +#define PRI_7 7
>
>> +/* Interrupt subpriority bits */
>> +#define SUB_PRI_0 0
>> +#define SUB_PRI_1 1
>> +#define SUB_PRI_2 2
>> +#define SUB_PRI_3 3
>
> These are obviously silly and should be removed/
>
Ack.
>> +#define PRI_MASK 0x7 /* 3 bit priority mask */
>> +#define SUBPRI_MASK 0x3 /* 2 bit subpriority mask */
>> +#define INT_MASK 0x1F /* 5 bit pri and subpri mask */
>> +#define NR_EXT_IRQS 5 /* 5 external interrupts sources */
>> +
>> +#define MICROCHIP_EVIC_MIN_PRIORITY 0
>> +#define MICROCHIP_EVIC_MAX_PRIORITY INT_MASK
>> +
>> +#define INT_PRI(pri, subpri) \
>> + (((pri & PRI_MASK) << 2) | (subpri & SUBPRI_MASK))
>> +
>> +#define DEFINE_INT(irq, pri) { irq, pri }
>> +
>> +#define DEFAULT_INT_PRI INT_PRI(2, 0)
>
> Is it required to have a specific priority configured for each line?
> If these are software selectable, it's probably better to not put
> them into DT in the first place.
>
> If you absolutely need them, I would suggest using two separate cells
> for pri and subpri so you can avoid the macro.
>
These priorities are hardware priorities that arbitrate pending interrupts to the CPU. These are indeed software configurable and we can agree that DT is probably not the best place to put this configuration in light of this. We'll default to something sane instead. They will be removed from the binding.
Josh
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation
2015-11-21 20:49 ` Arnd Bergmann
@ 2015-11-26 4:05 ` Joshua Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-11-26 4:05 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-kernel, linux-mips, Purna Chandra Mandal, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, devicetree
Hi Arnd,
On 11/21/2015 1:49 PM, Arnd Bergmann wrote:
> On Friday 20 November 2015 17:17:15 Joshua Henderson wrote:
>> +/* PIC32 specific clks */
>> +pic32_clktree {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + reg = <0x1f801200 0x200>;
>> + compatible = "microchip,pic32-clk";
>> + interrupts = <12>;
>> + ranges;
>> +
>> + /* secondary oscillator; external input on SOSCI pin */
>> + SOSC:sosc_clk {
>> + #clock-cells = <0>;
>> + compatible = "microchip,pic32-sosc";
>> + clock-frequency = <32768>;
>> + reg = <0x1f801200 0x10 /* enable reg */
>> + 0x1f801390 0x10>; /* status reg */
>> + microchip,bit-mask = <0x02>; /* enable mask */
>> + microchip,status-bit-mask = <0x10>; /* status-mask*/
>> + };
>>
>
> If you want to use the reg property in this way for each cell,
> at least use a 'ranges' that only translates the actual registers
> like this
>
> ranges = <0 0x1f801200 0x200>
>
> sosc_clk {
> ...
> reg = <0x000 0x10>, <0x190 0x10>;
> ...
> };
>
> Arnd
>
This does indeed seem to be the correct way to use ranges in this case. Consider it done.
Thanks for the feedback,
Josh
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 12/14] DEVICETREE: Add bindings for PIC32 SDHC host controller
2015-11-21 15:19 ` Sergei Shtylyov
@ 2015-11-26 4:40 ` Joshua Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-11-26 4:40 UTC (permalink / raw)
To: Sergei Shtylyov, linux-kernel
Cc: linux-mips, Andrei Pistirica, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, devicetree
Hi Sergei,
On 11/21/2015 8:19 AM, Sergei Shtylyov wrote:
> Hello.
>
> On 11/21/2015 3:17 AM, Joshua Henderson wrote:
>
>> From: Andrei Pistirica <andrei.pistirica@microchip.com>
>>
>> Document the devicetree bindings for the SDHC peripheral found on
>> Microchip PIC32 class devices.
>>
>> Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
>> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
>> ---
>> .../devicetree/bindings/mmc/sdhci-pic32.txt | 24 ++++++++++++++++++++
>> 1 file changed, 24 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
>> new file mode 100644
>> index 0000000..f16388c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
>> @@ -0,0 +1,24 @@
>> +* Microchip PIC32 SDHCI Controller
>> +
>> +This file documents differences between the core properties in mmc.txt
>> +and the properties used by the sdhci-pic32 driver.
>> +
>> +Required properties:
>> +- compatible: Should be "microchip,pic32-sdhci"
>> +- reg: Should contain registers location and length
>> +- interrupts: Should contain interrupt
>> +- pinctrl: Should contain pinctrl for data and command lines
>
> This is a required prop, yet the example doesn't contain it?
>
Ack. Both the required properties and example need to contain pinctrl-names and pinctrl-0, not pinctrl.
>> +
>> +Optional properties:
>> +- no-1-8-v: 1.8V voltage selection not supported
>> +- piomode: disable DMA support
>> +
>> +Example:
>> +
>> + sdhci@1f8ec000 {
>> + compatible = "microchip,pic32-sdhci";
>> + reg = <0x1f8ec000 0x100>;
>> + interrupts = <SDHC_EVENT DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&REFCLKO4>, <&PBCLK5>;
>> + clock-names = "base_clk", "sys_clk";
>
> The "clocks" and "clock-names" props are not documented.
>
> [...]
>
> MBR, Sergei
>
Ack.
Thanks for the feedback,
Josh
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller
2015-11-22 21:14 ` Rob Herring
@ 2015-11-26 5:01 ` Joshua Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-11-26 5:01 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel, linux-mips, Cristian Birsan, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, devicetree
Hi Rob,
On 11/22/2015 2:14 PM, Rob Herring wrote:
> On Fri, Nov 20, 2015 at 05:17:13PM -0700, Joshua Henderson wrote:
>> From: Cristian Birsan <cristian.birsan@microchip.com>
>>
>> Document the devicetree bindings for the interrupt controller on Microchip
>> PIC32 class devices. This also adds a header defining associated interrupts
>> and related settings.
>>
>> Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
>> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
>> ---
>> .../microchip,pic32mz-evic.txt | 65 ++++++
>> .../interrupt-controller/microchip,pic32mz-evic.h | 238 ++++++++++++++++++++
>> 2 files changed, 303 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
>> create mode 100644 include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
>> new file mode 100644
>> index 0000000..12fb91f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
>> @@ -0,0 +1,65 @@
>> +Microchip PIC32MZ Interrupt Controller
>> +======================================
>> +
>> +The Microchip PIC32MZ SOC contains an Enhanced Vectored Interrupt Controller
>> +(EVIC) version 2. It handles internal and external interrupts and provides
>> +support for priority, sub-priority, irq type and polarity.
>> +
>> +Required properties
>> +-------------------
>> +
>> +- compatible: Should be "microchip,evic-v2"
>
> This should be more specific like "microchip,pic32mz-evic". You can keep
> this one in addition if you like for matching.
>
> Rob
>
Agreed. Due to feedback, we are settling on microchip,pic32mzda-evic and similar for all compatible properties in this patch series. I don't see a need to keep a more abstract name around here if you don't.
Josh
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 12/14] DEVICETREE: Add bindings for PIC32 SDHC host controller
2015-11-22 21:57 ` Rob Herring
@ 2015-11-26 5:16 ` Joshua Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-11-26 5:16 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Andrei Pistirica, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi Rob,
On 11/22/2015 2:57 PM, Rob Herring wrote:
> On Fri, Nov 20, 2015 at 05:17:24PM -0700, Joshua Henderson wrote:
>> From: Andrei Pistirica <andrei.pistirica-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>>
>> Document the devicetree bindings for the SDHC peripheral found on
>> Microchip PIC32 class devices.
>>
>> Signed-off-by: Andrei Pistirica <andrei.pistirica-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>> Signed-off-by: Joshua Henderson <joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>> ---
>> .../devicetree/bindings/mmc/sdhci-pic32.txt | 24 ++++++++++++++++++++
>> 1 file changed, 24 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
>> new file mode 100644
>> index 0000000..f16388c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mmc/sdhci-pic32.txt
>> @@ -0,0 +1,24 @@
>> +* Microchip PIC32 SDHCI Controller
>> +
>> +This file documents differences between the core properties in mmc.txt
>> +and the properties used by the sdhci-pic32 driver.
>> +
>> +Required properties:
>> +- compatible: Should be "microchip,pic32-sdhci"
>> +- reg: Should contain registers location and length
>> +- interrupts: Should contain interrupt
>> +- pinctrl: Should contain pinctrl for data and command lines
>> +
>> +Optional properties:
>> +- no-1-8-v: 1.8V voltage selection not supported
>
> There's a standard property for this one.
>
Correct. This is indeed a standard property that should not be here. There is currently discussion to avoid using this property anyway.
>> +- piomode: disable DMA support
>
> Proably this one too IIRC.
>
We will be dropping this. There are other ways to accomplish the same thing outside of DT.
Josh
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^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation
2015-11-22 21:31 ` Rob Herring
@ 2015-11-26 5:36 ` Joshua Henderson
2015-11-30 21:43 ` Rob Herring
0 siblings, 1 reply; 29+ messages in thread
From: Joshua Henderson @ 2015-11-26 5:36 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Purna Chandra Mandal,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi Rob,
On 11/22/2015 2:31 PM, Rob Herring wrote:
> On Fri, Nov 20, 2015 at 05:17:15PM -0700, Joshua Henderson wrote:
>> From: Purna Chandra Mandal <purna.mandal-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>>
>> Document the devicetree bindings for the clock driver found on Microchip
>> PIC32 class devices.
>>
>> Signed-off-by: Purna Chandra Mandal <purna.mandal-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>> Signed-off-by: Joshua Henderson <joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>> ---
>> .../devicetree/bindings/clock/microchip,pic32.txt | 263 ++++++++++++++++++++
>> 1 file changed, 263 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/microchip,pic32.txt b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
>> new file mode 100644
>> index 0000000..4cef72d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
>> @@ -0,0 +1,263 @@
>> +Binding for a Clock hardware block found on
>> +certain Microchip PIC32 MCU devices.
>> +
>> +Microchip SoC clocks-node consists of few oscillators, PLL, multiplexer
>> +and few divider nodes.
>
> [...]
>
>> +Required properties:
>> +- compatible : should have "microchip,pic32-clk".
>> +- reg : A Base address and length of the register set.
>> +- interrupts : source of interrupt.
>> +
>> +Optional properties (for subnodes):
>> +- #clock-cells: From common clock binding, should be 0.
>> +
>> +- microchip,clock-indices: in multiplexer node clock sources always aren't linear
>> + and contiguous. This property helps define clock-sources with respect to
>> + the mux clock node.
>> +
>> +- microchip,ignore-unused : ignore gate request even if the gated clock is unused.
>
> There is some discussion about this upstream with "critical-clocks"
> binding. Can you use and wait for that?
>
The way this is going, we might not have to wait. :) Is there a patch available yet to try it out?
>> +- microchip,status-bit-mask: bitmask for status check. This will be used to confirm
>> + particular operation by clock sub-node is completed. It is dependent sub-node.
>> +- microchip,bit-mask: enable mask, similar to microchip,status-bit-mask.
>
> We've generally decided not to describe clocks at this level of detail
> in DT. It's fine though for simple clock trees. This one seems to be
> borderline IMO.
>
The binding example is the entire clock tree. These masks are right from the datasheet. For reference, do you have an example of a better alternative?
>> +- microchip,slew-step: enable frequency slewing(stepping) during rate change;
>> + applicable only to sys-clock subnode.
>
Thanks,
Josh
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^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation
2015-11-26 5:36 ` Joshua Henderson
@ 2015-11-30 21:43 ` Rob Herring
2015-12-03 17:37 ` Joshua Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Rob Herring @ 2015-11-30 21:43 UTC (permalink / raw)
To: Joshua Henderson
Cc: linux-kernel, linux-mips, Purna Chandra Mandal, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, devicetree
On Wed, Nov 25, 2015 at 10:36:55PM -0700, Joshua Henderson wrote:
> Hi Rob,
>
> On 11/22/2015 2:31 PM, Rob Herring wrote:
> > On Fri, Nov 20, 2015 at 05:17:15PM -0700, Joshua Henderson wrote:
> >> From: Purna Chandra Mandal <purna.mandal@microchip.com>
> >>
> >> Document the devicetree bindings for the clock driver found on Microchip
> >> PIC32 class devices.
> >>
> >> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
> >> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
> >> ---
> >> .../devicetree/bindings/clock/microchip,pic32.txt | 263 ++++++++++++++++++++
> >> 1 file changed, 263 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/microchip,pic32.txt b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
> >> new file mode 100644
> >> index 0000000..4cef72d
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
> >> @@ -0,0 +1,263 @@
> >> +Binding for a Clock hardware block found on
> >> +certain Microchip PIC32 MCU devices.
> >> +
> >> +Microchip SoC clocks-node consists of few oscillators, PLL, multiplexer
> >> +and few divider nodes.
> >
> > [...]
> >
> >> +Required properties:
> >> +- compatible : should have "microchip,pic32-clk".
BTW, this should list out the actual compatible strings.
> > There is some discussion about this upstream with "critical-clocks"
> > binding. Can you use and wait for that?
> >
>
> The way this is going, we might not have to wait. :) Is there a patch available yet to try it out?
Yes, googling "Lee Jones critical-clocks" should find it.
> >> +- microchip,status-bit-mask: bitmask for status check. This will be used to confirm
> >> + particular operation by clock sub-node is completed. It is dependent sub-node.
> >> +- microchip,bit-mask: enable mask, similar to microchip,status-bit-mask.
> >
> > We've generally decided not to describe clocks at this level of detail
> > in DT. It's fine though for simple clock trees. This one seems to be
> > borderline IMO.
> >
>
> The binding example is the entire clock tree. These masks are right from the datasheet. For reference, do you have an example of a better alternative?
Okay, like I said, borderline. If this is complete, then it is fine.
Adding more clocks or a newer version of the SoC with more clocks would
change that opinion.
Rob
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation
2015-11-30 21:43 ` Rob Herring
@ 2015-12-03 17:37 ` Joshua Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-12-03 17:37 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Purna Chandra Mandal,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA
Rob,
On 11/30/2015 02:43 PM, Rob Herring wrote:
> On Wed, Nov 25, 2015 at 10:36:55PM -0700, Joshua Henderson wrote:
>> Hi Rob,
>>
>> On 11/22/2015 2:31 PM, Rob Herring wrote:
>>> On Fri, Nov 20, 2015 at 05:17:15PM -0700, Joshua Henderson wrote:
>>>> From: Purna Chandra Mandal <purna.mandal-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>>>>
>>>> Document the devicetree bindings for the clock driver found on Microchip
>>>> PIC32 class devices.
>>>>
>>>> Signed-off-by: Purna Chandra Mandal <purna.mandal-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>>>> Signed-off-by: Joshua Henderson <joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>>>> ---
>>>> .../devicetree/bindings/clock/microchip,pic32.txt | 263 ++++++++++++++++++++
>>>> 1 file changed, 263 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/microchip,pic32.txt b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
>>>> new file mode 100644
>>>> index 0000000..4cef72d
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/microchip,pic32.txt
>>>> @@ -0,0 +1,263 @@
>>>> +Binding for a Clock hardware block found on
>>>> +certain Microchip PIC32 MCU devices.
>>>> +
>>>> +Microchip SoC clocks-node consists of few oscillators, PLL, multiplexer
>>>> +and few divider nodes.
>>>
>>> [...]
>>>
>>>> +Required properties:
>>>> +- compatible : should have "microchip,pic32-clk".
>
> BTW, this should list out the actual compatible strings.
Ack. These are also being changed to microchip,pic32mzda-* due to other feedback.
>
>>> There is some discussion about this upstream with "critical-clocks"
>>> binding. Can you use and wait for that?
>>>
>>
>> The way this is going, we might not have to wait. :) Is there a patch available yet to try it out?
>
> Yes, googling "Lee Jones critical-clocks" should find it.
The change for this on our side is in the queue should the stars align on timing.
[...]
>
> Rob
>
Thanks,
Josh
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^ permalink raw reply [flat|nested] 29+ messages in thread
* RE: [PATCH 07/14] DEVICETREE: Add bindings for PIC32 pin control and GPIO
2015-11-22 21:47 ` Rob Herring
@ 2015-12-04 13:02 ` Andrei.Pistirica
2015-12-08 22:13 ` Joshua Henderson
1 sibling, 0 replies; 29+ messages in thread
From: Andrei.Pistirica @ 2015-12-04 13:02 UTC (permalink / raw)
To: robh, Joshua.Henderson
Cc: linux-kernel, linux-mips, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree
Hi Rob,
Thank you for feedback. All the comments will be address in the next driver version.
We are currently working for a solution to use the standard bindings for pinctrl.
Regards,
Andrei
-----Original Message-----
From: Rob Herring [mailto:robh@kernel.org]
Sent: Sunday, November 22, 2015 11:47 PM
To: Joshua Henderson - C16205
Cc: linux-kernel@vger.kernel.org; linux-mips@linux-mips.org; Andrei Pistirica - M16132; Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; devicetree@vger.kernel.org
Subject: Re: [PATCH 07/14] DEVICETREE: Add bindings for PIC32 pin control and GPIO
On Fri, Nov 20, 2015 at 05:17:19PM -0700, Joshua Henderson wrote:
> From: Andrei Pistirica <andrei.pistirica@microchip.com>
>
> Document the devicetree bindings for PINCTRL and GPIO found on
> Microchip
> PIC32 class devices. This also adds a header defining related port and
> peripheral pin select functionality.
>
> Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
> ---
> .../bindings/gpio/microchip,pic32-gpio.txt | 33 ++
> .../bindings/pinctrl/microchip,pic32-pinctrl.txt | 100 +++++
> include/dt-bindings/pinctrl/pic32mzda.h | 404 ++++++++++++++++++++
> 3 files changed, 537 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
> create mode 100644
> Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
> create mode 100644 include/dt-bindings/pinctrl/pic32mzda.h
>
> diff --git
> a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
> b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
> new file mode 100644
> index 0000000..f6eeb2f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
> @@ -0,0 +1,33 @@
> +* Microchip PIC32 GPIO devices (PIO).
> +
> +Required properties:
> + - compatible: "microchip,pic32-gpio"
This should have a chip specific compatible string.
> + - reg: Base address and length for the device.
> + - interrupts: The port interrupt shared be all pins.
> + - gpio-controller: Marks the port as GPIO controller.
> + - #gpio-cells: Two. The first cell is the pin number and
> + the second cell is unused.
> + - interrupt-controller: Marks the device node as an interrupt controller.
> + - #interrupt-cells: Two. The first cell is the GPIO number and second cell
> + is used to specify the trigger type:
> + PIC32_PIN_CN_RISING : low-to-high edge triggered.
> + PIC32_PIN_CN_FALLING : high-to-low edge triggered.
> + PIC32_PIN_CN_BOTH : low-to-high and high-to-low edges triggered.
Can't you use the standard flags?
> +
> +Note:
> + - If gpio-ranges is missing, then all the pins (32) related to the gpio bank
> + are enabled.
> +
> +Example:
> + pioA: gpio@1f860000 {
> + compatible = "microchip,pic32-gpio";
> + reg = <0x1f860000 0x24>;
> + interrupts = <PORTA_INPUT_CHANGE_INTERRUPT
> + DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&pic32_pinctrl 0 0 32>;
> + clocks = <&PBCLK4>;
> + };
> diff --git
> a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.tx
> t
> b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.tx
> t
> new file mode 100644
> index 0000000..7cf4167
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctr
> +++ l.txt
> @@ -0,0 +1,100 @@
> +* Microchip PIC32 Pinmux device.
> +
> +Please refer to pinctrl-bindings.txt for details of the pinctrl
> +properties and common bindings.
> +
> +PIC32 'pin configuration node' is a node of a group of pins which can
> +be used for a specific device or function. This node represents
> +configuraions of single pins or a pairs of mux and related configuration.
> +
> +Required properties for pic32 device:
> + - compatible: "microchip,pic32-pinctrl", "microchip,pic32mz-pinctrl"
Is this both or either one. For both, it should be most specific first.
> + - reg: Base address and length for pps:in and pps:out registers.
> +
> +Properties for 'pin configuration node':
> + - pic32,pins: each entry consists of 3 intergers and represents the mux and
> + config settings for one pin. The first integer represent the remappable pin,
> + the second represent the peripheral pin and the last the configuration.
> + The format is pic32,pins = <PIC32_RP_'dir'_'pin'
> + PIC32_PP_'dir'_'peripherl-pin' PIC32_PIN_CONF_'config'>. The configurations
> + are divided in 2 classes: IN and OUT and each in 4 buckets. Each entry must
> + contains items from the same class and bucket, otherwise the driver will
> + notify an error and the initialization will fail.
> + - pic32,single-pins: each entry consists of 3 intergers and represents a pin
> + (that is not remappable) and related configuraion. The format is
> + pic32,single-pins = <PORT_'x' 'pin' PIC32_PIN_CONF_'config'>. Each port has
> + 32 pins and please refer to chip documentation for details of remappable
> + pins.
> +
> +Available pin configurations (refer to dt-bindings/pinctrl/pic32.h):
> + PIC32_PIN_CONF_NONE : no configuration (default).
> + PIC32_PIN_CONF_OD : indicate this pin need a open-drain (no direction).
> + PIC32_PIN_CONF_OD_OUT : indicate this pin need a open-drain out.
> + PIC32_PIN_CONF_PU : indicate this pin need a pull up (no direction).
> + PIC32_PIN_CONF_PU_IN : indicate this pin need a pull up in.
> + PIC32_PIN_CONF_PD : indicate this pin need a pull down (no direction).
> + PIC32_PIN_CONF_PD_IN : indicate this pin need a pull down input.
> + PIC32_PIN_CONF_AN : indicate this pin as analogic (no direction).
> + PIC32_PIN_CONF_AN_IN : indicate this pin as analogic input.
> + PIC32_PIN_CONF_DG : indicate this pin as digital (no direction).
> + PIC32_PIN_CONF_DG_IN : indicate this pin as digital input.
> + PIC32_PIN_CONF_DG_OUT : indicate this pin as digital output.
> +
> +NOTEs:
> +1. The pins functions nods are defined under pic32 pinctrl node. The function's
> + pin groups are defined under functions node.
> +2. Each pin group can have both pic32,pins and pic32,single-pins properties to
> + specify re-mappable or non-remappable pins with related mux and configs or
> + at least one.
> +3. Each pin configuration node can have a phandle and devices can set pins
> + configurations by referring to the phandle of that pin configuration node.
> +4. The pinctrl bindings are listed in dt-bindings/pinctrl/pic32.h.
> +5. The gpio controller must be described in the pinctrl simple-bus.
> +
> +Example:
> +pinctrl@1f800000{
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "microchip,pic32-pinctrl", "simple-bus";
> + ranges;
> + reg = <0x1f801404 0x3c>, /* in */
> + <0x1f801538 0x57>; /* out */
> +
> + pioA: gpio@1f860000 {
> + compatible = "microchip,pic32-gpio";
The gpio controller is a sub-function of the pinctrl? That doesn't really seem to be the case based on the addresses.
> + reg = <0x1f860000 0x24>;
> + gpio-controller;
> + };
> +
> + /* functions */
> + sw1 {
> + pinctrl_sw1: sw1-0 {
> + pic32,single-pins = <PORT_B 12 PIC32_PIN_CONF_PULLUP>;
Why isn't this using standard pinctrl properties?
> + };
> + };
> +
> + uart1 {
> + pinctrl_uart1: uart1-0 {
> + pic32,pins =
> + <PIC32_RP_OUT_RPG7 PIC32_PP_OUT_U1TX PIC32_PIN_CONF_NONE
> + PIC32_RP_IN_RPG8 PIC32_PP_IN_U1RX PIC32_PIN_CONF_NONE>;
> + };
> + };
> +};
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 07/14] DEVICETREE: Add bindings for PIC32 pin control and GPIO
2015-11-22 21:47 ` Rob Herring
2015-12-04 13:02 ` Andrei.Pistirica
@ 2015-12-08 22:13 ` Joshua Henderson
1 sibling, 0 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-12-08 22:13 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Andrei Pistirica, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi Rob,
On 11/22/2015 02:47 PM, Rob Herring wrote:
> On Fri, Nov 20, 2015 at 05:17:19PM -0700, Joshua Henderson wrote:
>> From: Andrei Pistirica <andrei.pistirica-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>>
>> Document the devicetree bindings for PINCTRL and GPIO found on Microchip
>> PIC32 class devices. This also adds a header defining related port and
>> peripheral pin select functionality.
>>
>> Signed-off-by: Andrei Pistirica <andrei.pistirica-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>> Signed-off-by: Joshua Henderson <joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>> ---
>> .../bindings/gpio/microchip,pic32-gpio.txt | 33 ++
>> .../bindings/pinctrl/microchip,pic32-pinctrl.txt | 100 +++++
>> include/dt-bindings/pinctrl/pic32mzda.h | 404 ++++++++++++++++++++
>> 3 files changed, 537 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
>> create mode 100644 include/dt-bindings/pinctrl/pic32mzda.h
>>
>> diff --git a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
>> new file mode 100644
>> index 0000000..f6eeb2f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
>> @@ -0,0 +1,33 @@
>> +* Microchip PIC32 GPIO devices (PIO).
>> +
>> +Required properties:
>> + - compatible: "microchip,pic32-gpio"
>
> This should have a chip specific compatible string.
>
Will change to "microchip,pic32mzda-gpio".
>> + - reg: Base address and length for the device.
>> + - interrupts: The port interrupt shared be all pins.
>> + - gpio-controller: Marks the port as GPIO controller.
>> + - #gpio-cells: Two. The first cell is the pin number and
>> + the second cell is unused.
>> + - interrupt-controller: Marks the device node as an interrupt controller.
>> + - #interrupt-cells: Two. The first cell is the GPIO number and second cell
>> + is used to specify the trigger type:
>> + PIC32_PIN_CN_RISING : low-to-high edge triggered.
>> + PIC32_PIN_CN_FALLING : high-to-low edge triggered.
>> + PIC32_PIN_CN_BOTH : low-to-high and high-to-low edges triggered.
>
> Can't you use the standard flags?
>
Yes. This will be changed.
>> +
>> +Note:
>> + - If gpio-ranges is missing, then all the pins (32) related to the gpio bank
>> + are enabled.
>> +
>> +Example:
>> + pioA: gpio@1f860000 {
>> + compatible = "microchip,pic32-gpio";
>> + reg = <0x1f860000 0x24>;
>> + interrupts = <PORTA_INPUT_CHANGE_INTERRUPT
>> + DEFAULT_INT_PRI IRQ_TYPE_LEVEL_HIGH>;
>> + #gpio-cells = <2>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + gpio-ranges = <&pic32_pinctrl 0 0 32>;
>> + clocks = <&PBCLK4>;
>> + };
>> diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
>> new file mode 100644
>> index 0000000..7cf4167
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
>> @@ -0,0 +1,100 @@
>> +* Microchip PIC32 Pinmux device.
>> +
>> +Please refer to pinctrl-bindings.txt for details of the pinctrl properties and
>> +common bindings.
>> +
>> +PIC32 'pin configuration node' is a node of a group of pins which can be
>> +used for a specific device or function. This node represents configuraions of
>> +single pins or a pairs of mux and related configuration.
>> +
>> +Required properties for pic32 device:
>> + - compatible: "microchip,pic32-pinctrl", "microchip,pic32mz-pinctrl"
>
> Is this both or either one. For both, it should be most specific first.
>
This is a mistake. Will change to only "microchip,pic32mzda-pinctrl".
>
>> + - reg: Base address and length for pps:in and pps:out registers.
>> +
>> +Properties for 'pin configuration node':
>> + - pic32,pins: each entry consists of 3 intergers and represents the mux and
>> + config settings for one pin. The first integer represent the remappable pin,
>> + the second represent the peripheral pin and the last the configuration.
>> + The format is pic32,pins = <PIC32_RP_'dir'_'pin'
>> + PIC32_PP_'dir'_'peripherl-pin' PIC32_PIN_CONF_'config'>. The configurations
>> + are divided in 2 classes: IN and OUT and each in 4 buckets. Each entry must
>> + contains items from the same class and bucket, otherwise the driver will
>> + notify an error and the initialization will fail.
>> + - pic32,single-pins: each entry consists of 3 intergers and represents a pin
>> + (that is not remappable) and related configuraion. The format is
>> + pic32,single-pins = <PORT_'x' 'pin' PIC32_PIN_CONF_'config'>. Each port has
>> + 32 pins and please refer to chip documentation for details of remappable
>> + pins.
>> +
>> +Available pin configurations (refer to dt-bindings/pinctrl/pic32.h):
>> + PIC32_PIN_CONF_NONE : no configuration (default).
>> + PIC32_PIN_CONF_OD : indicate this pin need a open-drain (no direction).
>> + PIC32_PIN_CONF_OD_OUT : indicate this pin need a open-drain out.
>> + PIC32_PIN_CONF_PU : indicate this pin need a pull up (no direction).
>> + PIC32_PIN_CONF_PU_IN : indicate this pin need a pull up in.
>> + PIC32_PIN_CONF_PD : indicate this pin need a pull down (no direction).
>> + PIC32_PIN_CONF_PD_IN : indicate this pin need a pull down input.
>> + PIC32_PIN_CONF_AN : indicate this pin as analogic (no direction).
>> + PIC32_PIN_CONF_AN_IN : indicate this pin as analogic input.
>> + PIC32_PIN_CONF_DG : indicate this pin as digital (no direction).
>> + PIC32_PIN_CONF_DG_IN : indicate this pin as digital input.
>> + PIC32_PIN_CONF_DG_OUT : indicate this pin as digital output.
>> +
>> +NOTEs:
>> +1. The pins functions nods are defined under pic32 pinctrl node. The function's
>> + pin groups are defined under functions node.
>> +2. Each pin group can have both pic32,pins and pic32,single-pins properties to
>> + specify re-mappable or non-remappable pins with related mux and configs or
>> + at least one.
>> +3. Each pin configuration node can have a phandle and devices can set pins
>> + configurations by referring to the phandle of that pin configuration node.
>> +4. The pinctrl bindings are listed in dt-bindings/pinctrl/pic32.h.
>> +5. The gpio controller must be described in the pinctrl simple-bus.
>> +
>> +Example:
>> +pinctrl@1f800000{
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "microchip,pic32-pinctrl", "simple-bus";
>> + ranges;
>> + reg = <0x1f801404 0x3c>, /* in */
>> + <0x1f801538 0x57>; /* out */
>> +
>> + pioA: gpio@1f860000 {
>> + compatible = "microchip,pic32-gpio";
>
> The gpio controller is a sub-function of the pinctrl? That doesn't
> really seem to be the case based on the addresses.
>
PIC32MZDA has a group of hardware registers that only handles assigning
functions to pins. We have related this set of hardware registers to a
pinctrl node. Separately, each bank of pins has its own set of registers
that handle setting input, output, pullup, gpio interrupts, etc. We have
mapped each of those banks to gpio-controller nodes. However, the
functionality in hardware for pinmux and pinconf spans both the pinctrl
and gpio node registers. It seems that there is overlap in hardware with
functionality that seems to usually be considered somewhat separate
definitions in standard bindings which is the source of some confusion.
We can make the gpio-controller and pinctrl nodes siblings, but they are
still tightly related. Does the following working example make more sense?
pic32_pinctrl: pinctrl@1f801400{
#address-cells = <1>;
#size-cells = <1>;
compatible = "microchip,pic32mzda-pinctrl";
reg = <0x1f801400 0x400>;
clocks = <&PBCLK1>;
};
gpio0: gpio0@1f860000 {
compatible = "microchip,pic32mzda-gpio";
reg = <0x1f860000 0x100>;
interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
gpio-ranges = <&pic32_pinctrl 0 0 16>;
};
gpio1: gpio1@1f860100 {
compatible = "microchip,pic32mzda-gpio";
reg = <0x1f860100 0x100>;
interrupts = <119 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
gpio-ranges = <&pic32_pinctrl 0 16 16>;
};
>> + reg = <0x1f860000 0x24>;
>> + gpio-controller;
>> + };
>> +
>> + /* functions */
>> + sw1 {
>> + pinctrl_sw1: sw1-0 {
>> + pic32,single-pins = <PORT_B 12 PIC32_PIN_CONF_PULLUP>;
>
> Why isn't this using standard pinctrl properties?
>
There is no technical reason other than it was based off of existing
bindings in the kernel, albeit, non-standard ones. This will be reworked
to use standard bindings, with a couple additional microchip, properties
for digital and analog. The following example is the target:
pinctrl_uart2: uart2_0 {
uart2-tx {
pins = "G9";
function = "U2TX";
microchip,digital;
};
uart2-rx {
pins = "B0";
function = "U2RX";
microchip,digital;
};
};
pinctrl_adc1: adc1_0 {
pins = "A10";
microchip,analog-level;
input-enable;
};
>> + };
>> + };
>> +
>> + uart1 {
>> + pinctrl_uart1: uart1-0 {
>> + pic32,pins =
>> + <PIC32_RP_OUT_RPG7 PIC32_PP_OUT_U1TX PIC32_PIN_CONF_NONE
>> + PIC32_RP_IN_RPG8 PIC32_PP_IN_U1RX PIC32_PIN_CONF_NONE>;
>> + };
>> + };
>> +};
Thanks for your time,
Josh
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^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 09/14] DEVICETREE: Add bindings for PIC32 usart driver
2015-11-22 21:56 ` Rob Herring
@ 2015-12-11 16:16 ` Joshua Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Joshua Henderson @ 2015-12-11 16:16 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA, Andrei Pistirica, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA
Rob,
On 11/22/2015 02:56 PM, Rob Herring wrote:
> On Fri, Nov 20, 2015 at 05:17:21PM -0700, Joshua Henderson wrote:
>> From: Andrei Pistirica <andrei.pistirica-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>>
>> Document the devicetree bindings for the USART peripheral found on
>> Microchip PIC32 class devices.
>>
>> Signed-off-by: Andrei Pistirica <andrei.pistirica-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>> Signed-off-by: Joshua Henderson <joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
>> ---
>> .../bindings/serial/microchip,pic32-usart.txt | 29 ++++++++++++++++++++
>> 1 file changed, 29 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
>>
>> diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt b/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
>> new file mode 100644
>> index 0000000..c87321c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/serial/microchip,pic32-usart.txt
>> @@ -0,0 +1,29 @@
>> +* Microchip Universal Synchronous Asynchronous Receiver/Transmitter (USART)
>> +
>> +Required properties:
>> +- compatible: Should be "microchip,pic32-usart"
>
> Again, should be more specific.
>
Ack. In addition, will replace all instances of USART with UART.
>> +- reg: Should contain registers location and length
>> +- interrupts: Should contain interrupt
>> +- pinctrl: Should contain pinctrl for TX/RX/RTS/CTS
>> +
>> +Optional properties:
>> +- microchip,uart-has-rtscts : Indicate the uart has hardware flow control
>> +- rts-gpios: RTS pin for USP-based UART if microchip,uart-has-rtscts
>> +- cts-gpios: CTS pin for USP-based UART if microchip,uart-has-rtscts
>
> This appears to just be copied for Sirf UART.
>
> Doesn't *-gpios being present imply having h/w
> flow-control (i.e. microchip,uart-has-rtscts)?
>
> Rob
Agreed. microchip,uart-has-rtscts will be dropped and it turns out we don't really need the rtc-gpios property.
Josh
>
>> +
>> +Example:
>> + usart0: serial@1f822000 {
>> + compatible = "microchip,pic32-usart";
>> + reg = <0x1f822000 0x50>;
>> + interrupts = <UART1_FAULT DEFAULT_INT_PRI IRQ_TYPE_NONE>,
>> + <UART1_RECEIVE_DONE DEFAULT_INT_PRI IRQ_TYPE_NONE>,
>> + <UART1_TRANSFER_DONE DEFAULT_INT_PRI IRQ_TYPE_NONE>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <
>> + &pinctrl_uart1
>> + &pinctrl_uart1_cts
>> + &pinctrl_uart1_rts>;
>> + microchip,uart-has-rtscts;
>> + cts-gpios = <&pioB 15 0>;
>> + rts-gpios = <&pioD 1 0>;
>> + };
>> --
>> 1.7.9.5
>>
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^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2015-12-11 16:16 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-11-21 0:17 [PATCH 00/14] Initial Microchip PIC32MZDA Support Joshua Henderson
2015-11-21 0:17 ` [PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller Joshua Henderson
2015-11-21 20:47 ` Arnd Bergmann
2015-11-25 18:22 ` Joshua Henderson
[not found] ` <1448065205-15762-2-git-send-email-joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
2015-11-22 21:14 ` Rob Herring
2015-11-26 5:01 ` Joshua Henderson
2015-11-21 0:17 ` [PATCH 03/14] DEVICETREE: Add PIC32 clock binding documentation Joshua Henderson
2015-11-21 20:49 ` Arnd Bergmann
2015-11-26 4:05 ` Joshua Henderson
[not found] ` <1448065205-15762-4-git-send-email-joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
2015-11-22 21:31 ` Rob Herring
2015-11-26 5:36 ` Joshua Henderson
2015-11-30 21:43 ` Rob Herring
2015-12-03 17:37 ` Joshua Henderson
2015-11-21 0:17 ` [PATCH 05/14] DEVICETREE: Add bindings for PIC32/MZDA platforms Joshua Henderson
2015-11-22 21:35 ` Rob Herring
2015-11-21 0:17 ` [PATCH 07/14] DEVICETREE: Add bindings for PIC32 pin control and GPIO Joshua Henderson
2015-11-22 21:47 ` Rob Herring
2015-12-04 13:02 ` Andrei.Pistirica
2015-12-08 22:13 ` Joshua Henderson
2015-11-21 0:17 ` [PATCH 09/14] DEVICETREE: Add bindings for PIC32 usart driver Joshua Henderson
2015-11-21 15:20 ` Sergei Shtylyov
2015-11-22 21:56 ` Rob Herring
2015-12-11 16:16 ` Joshua Henderson
2015-11-21 0:17 ` [PATCH 12/14] DEVICETREE: Add bindings for PIC32 SDHC host controller Joshua Henderson
2015-11-21 15:19 ` Sergei Shtylyov
2015-11-26 4:40 ` Joshua Henderson
2015-11-22 21:57 ` Rob Herring
2015-11-26 5:16 ` Joshua Henderson
2015-11-21 0:17 ` [PATCH 13/14] MIPS: dts: Add initial DTS for the PIC32MZDA Starter Kit Joshua Henderson
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