[PATCH v5 0/4] ARM: shmobile: r8a7740/sh73a0 DT Cache Handling

[PATCH v5 0/4] ARM: shmobile: r8a7740/sh73a0 DT Cache Handling

[Geert Uytterhoeven]

	Hi Simon, Magnus,

This patch series add minimal L1 and L2 cache descriptions to DT for
r8a7740 and sh73a0, and migrates the shmobile DT-based generic r8a7740
platform from calling l2x0_of_init() to the generic l2c OF
initialization.

Note that the conversion to the generic l2c OF initialization is not
done yet for sh73a0, as this initializes the L2 cache earlier, breaking
the (fragile) sh73a0 secondary CPU bringup code.

Also note that this conversion should be done on r8a7778, and r8a7779,
too.

Changes compared to v4 ("[PATCH v4 0/6] ARM: shmobile: r8a7740/sh73a0 DT
Cache Handling",
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/340636.html):
  - Drop optional cache-{size,sets,{block,line}-size} properties, as
    this information is auto-detected (I verified this for both L1 and
    L2 cache properties),
  - Merge the L1 patches into the L2 patches, as the only part left from
    the L1 patches was adding the links from CPU to L2 cache nodes.

Changes compared to v3 ("[PATCH v3 0/6] ARM: l2c / shmobile: r8a7740 :
Shared Override",
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/340636.html):
  - "l2c: Add support for the "arm,shared-override" property" was split
    off into an independent patch, and is now queued for v4.3 in
    arm/for-next,
  - Dropped armadillo legacy migration, as it no longer exists,
  - Added sh73a0 L1 and L2 DT cache description.

Changes compared to v2 ("[PATCH v2 0/5] ARM: shmobile: r8a7740/armadillo:
Migrate to generic l2c OF",
http://www.spinics.net/lists/devicetree/msg68176.html):
  - Add DT support for Shared Override,
  - Setting Shared Override is done only if CMA is not available (as
    Russell claims it's not needed if CMA is available),
  - Use 0/~0 in machine_desc.l2c_aux_{val,mask}, as DT now supports
    "arm,shared-override".

Changes compared to v1:
  - Fix interrupt reference in DT,
  - Describe L2 better in DT,
  - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE in
    machine_desc.l2c_aux_{val,mask}, as there's no DT property for
    this.
  - Add L1 cache to DT.

Dependencies:
  - This series applies to renesas-devel-20151123-v4.4-rc2,
  - Patch 3 depends on patch 1,
  - Patch 4 depends on patch 3.

Given C code changesets depending on DT changesets in the same branch
are frowned upon, you may want to postpone patches 3 and 4 to v4.6.
Of course I'll sleep better if you just apply all 4 of them now ;-)

I've been running this on r8a7740/armadillo and sh73a0/kzm9g for more
than a year.

Thanks for applying!

Geert Uytterhoeven (4):
  ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node
  ARM: shmobile: sh73a0 dtsi: Add L2 cache-controller node
  ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization
  ARM: shmobile: r8a7740: Remove mapping of L2 cache controller
    registers

 arch/arm/boot/dts/r8a7740.dtsi         | 13 +++++++++++++
 arch/arm/boot/dts/sh73a0.dtsi          | 14 ++++++++++++++
 arch/arm/mach-shmobile/setup-r8a7740.c | 18 ++----------------
 3 files changed, 29 insertions(+), 16 deletions(-)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds
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[PATCH v5 1/4] ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add the missing L2 cache-controller node, and link the CPU node to it.
This will allow migration to the generic l2c OF initialization.

The L2 cache is an ARM L2C-310 (r3p1-150rel0), of size 256 KiB (32 KiB x
8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v5:
  - Drop optional cache-{size,sets,{block,line}-size} properties, as
    this information is auto-detected,
  - Integrate adding the link from CPU to L2 cache into this patch,

v4:
  - Commit eeedcea69e927857 ("ARM: 8395/1: l2c: Add support for the
    "arm,shared-override" property") is queued for 4.3 in arm/for-next,

v3:
  - Add "arm,shared-override",

v2:
  - Fix interrupt (should be 3 cells, not 1),
  - Describe cache better.
---
 arch/arm/boot/dts/r8a7740.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 387aef60c825bc24..ff3dedb63ef48ea7 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -26,6 +26,7 @@
 			reg = <0x0>;
 			clock-frequency = <800000000>;
 			power-domains = <&pd_a3sm>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -37,6 +38,18 @@
 		      <0xc2000000 0x1000>;
 	};
 
+	L2: cache-controller {
+		compatible = "arm,pl310-cache";
+		reg = <0xf0100000 0x1000>;
+		interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_a3sm>;
+		arm,data-latency = <3 3 3>;
+		arm,tag-latency = <2 2 2>;
+		arm,shared-override;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	dbsc3: memory-controller@fe400000 {
 		compatible = "renesas,dbsc3-r8a7740";
 		reg = <0xfe400000 0x400>;
-- 
1.9.1

[PATCH v5 2/4] ARM: shmobile: sh73a0 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add the missing L2 cache-controller node, and link the CPU nodes to it.
This will allow migration to the generic l2c OF initialization.

The L2 cache is an ARM L2C-310 (r3p1), of size 512 KiB (64 KiB x 8
ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v5:
  - Drop optional cache-{size,sets,{block,line}-size} properties, as
    this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,

v4:
  - New.
---
 arch/arm/boot/dts/sh73a0.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index cbc885e46c504f56..f90ef9c93d3df3aa 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -28,6 +28,7 @@
 			reg = <0>;
 			clock-frequency = <1196000000>;
 			power-domains = <&pd_a2sl>;
+			next-level-cache = <&L2>;
 		};
 		cpu@1 {
 			device_type = "cpu";
@@ -35,6 +36,7 @@
 			reg = <1>;
 			clock-frequency = <1196000000>;
 			power-domains = <&pd_a2sl>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -53,6 +55,18 @@
 		      <0xf0000100 0x100>;
 	};
 
+	L2: cache-controller {
+		compatible = "arm,pl310-cache";
+		reg = <0xf0100000 0x1000>;
+		interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_a3sm>;
+		arm,data-latency = <3 3 3>;
+		arm,tag-latency = <2 2 2>;
+		arm,shared-override;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	sbsc2: memory-controller@fb400000 {
 		compatible = "renesas,sbsc-sh73a0";
 		reg = <0xfb400000 0x400>;
-- 
1.9.1

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[PATCH v5 3/4] ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization

[Geert Uytterhoeven]

Migrate the generic r8a7740 platform from calling l2x0_of_init() to the
generic l2c OF initialization.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v5:
  - No changes,

v4:
  - This depends on commit eeedcea69e927857 ("ARM: 8395/1: l2c: Add
    support for the "arm,shared-override" property"), which is queued
    for 4.3 in arm/for-next,

v3:
  - Use 0/~0 now DT supports "arm,shared-override",

v2:
  - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE.
---
 arch/arm/mach-shmobile/setup-r8a7740.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 0c8f80c5b04df34d..7b16c12e3f816f7f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -110,10 +110,6 @@ static void __init r8a7740_generic_init(void)
 {
 	r8a7740_meram_workaround();
 
-#ifdef CONFIG_CACHE_L2X0
-	/* Shared attribute override enable, 32K*8way */
-	l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
-#endif
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
@@ -123,6 +119,8 @@ static const char *const r8a7740_boards_compat_dt[] __initconst = {
 };
 
 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.map_io		= r8a7740_map_io,
 	.init_early	= shmobile_init_delay,
 	.init_irq	= r8a7740_init_irq_of,
-- 
1.9.1

[PATCH v5 4/4] ARM: shmobile: r8a7740: Remove mapping of L2 cache controller registers

[Geert Uytterhoeven]

Now all r8a7740-based platforms have been migrated to the generic l2c OF
initialization, it's no longer needed to map the L2 cache controller
registers from .map_io().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v5:
  - No changes,

v4:
  - No changes,

v3:
  - No changes,

v2:
  - No changes.
---
 arch/arm/mach-shmobile/setup-r8a7740.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 7b16c12e3f816f7f..496569f9d578b863 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -38,18 +38,6 @@ static struct map_desc r8a7740_io_desc[] __initdata = {
 		.length		= 160 << 20,
 		.type		= MT_DEVICE_NONSHARED
 	},
-#ifdef CONFIG_CACHE_L2X0
-	/*
-	 * for l2x0_init()
-	 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
-	 */
-	{
-		.virtual	= 0xf0002000,
-		.pfn		= __phys_to_pfn(0xf0100000),
-		.length		= PAGE_SIZE,
-		.type		= MT_DEVICE_NONSHARED
-	},
-#endif
 };
 
 static void __init r8a7740_map_io(void)
-- 
1.9.1

Re: [PATCH v5 0/4] ARM: shmobile: r8a7740/sh73a0 DT Cache Handling

[Simon Horman]

On Mon, Nov 23, 2015 at 02:55:58PM +0100, Geert Uytterhoeven wrote:
> 	Hi Simon, Magnus,
> 
> This patch series add minimal L1 and L2 cache descriptions to DT for
> r8a7740 and sh73a0, and migrates the shmobile DT-based generic r8a7740
> platform from calling l2x0_of_init() to the generic l2c OF
> initialization.
> 
> Note that the conversion to the generic l2c OF initialization is not
> done yet for sh73a0, as this initializes the L2 cache earlier, breaking
> the (fragile) sh73a0 secondary CPU bringup code.
> 
> Also note that this conversion should be done on r8a7778, and r8a7779,
> too.

Based on your work I have prepared a DT patch for the r8a7779.
I don't think that a C patch is necessary, please correct me if I am wrong.

Regarding the r8a7778: My reading of the documentation is that although a
pl310 L2 cache controller is present it is not available for use as there
is no L2 cache memory present. For this reason I do not think any patches
are required for the r8a7798.

> Changes compared to v4 ("[PATCH v4 0/6] ARM: shmobile: r8a7740/sh73a0 DT
> Cache Handling",
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/340636.html):
>   - Drop optional cache-{size,sets,{block,line}-size} properties, as
>     this information is auto-detected (I verified this for both L1 and
>     L2 cache properties),
>   - Merge the L1 patches into the L2 patches, as the only part left from
>     the L1 patches was adding the links from CPU to L2 cache nodes.
> 
> Changes compared to v3 ("[PATCH v3 0/6] ARM: l2c / shmobile: r8a7740 :
> Shared Override",
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/340636.html):
>   - "l2c: Add support for the "arm,shared-override" property" was split
>     off into an independent patch, and is now queued for v4.3 in
>     arm/for-next,
>   - Dropped armadillo legacy migration, as it no longer exists,
>   - Added sh73a0 L1 and L2 DT cache description.
> 
> Changes compared to v2 ("[PATCH v2 0/5] ARM: shmobile: r8a7740/armadillo:
> Migrate to generic l2c OF",
> http://www.spinics.net/lists/devicetree/msg68176.html):
>   - Add DT support for Shared Override,
>   - Setting Shared Override is done only if CMA is not available (as
>     Russell claims it's not needed if CMA is available),
>   - Use 0/~0 in machine_desc.l2c_aux_{val,mask}, as DT now supports
>     "arm,shared-override".
> 
> Changes compared to v1:
>   - Fix interrupt reference in DT,
>   - Describe L2 better in DT,
>   - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE in
>     machine_desc.l2c_aux_{val,mask}, as there's no DT property for
>     this.
>   - Add L1 cache to DT.
> 
> Dependencies:
>   - This series applies to renesas-devel-20151123-v4.4-rc2,
>   - Patch 3 depends on patch 1,
>   - Patch 4 depends on patch 3.
> 
> Given C code changesets depending on DT changesets in the same branch
> are frowned upon, you may want to postpone patches 3 and 4 to v4.6.
> Of course I'll sleep better if you just apply all 4 of them now ;-)

I have queued up the DT changes for v4.5.
And tentatively queued up the C changes for v4.6.

> I've been running this on r8a7740/armadillo and sh73a0/kzm9g for more
> than a year.
> 
> Thanks for applying!
> 
> Geert Uytterhoeven (4):
>   ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node
>   ARM: shmobile: sh73a0 dtsi: Add L2 cache-controller node
>   ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization
>   ARM: shmobile: r8a7740: Remove mapping of L2 cache controller
>     registers
> 
>  arch/arm/boot/dts/r8a7740.dtsi         | 13 +++++++++++++
>  arch/arm/boot/dts/sh73a0.dtsi          | 14 ++++++++++++++
>  arch/arm/mach-shmobile/setup-r8a7740.c | 18 ++----------------
>  3 files changed, 29 insertions(+), 16 deletions(-)
> 
> -- 
> 1.9.1
> 
> Gr{oetje,eeting}s,
> 
> 						Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> 							    -- Linus Torvalds
> 

Re: [PATCH v5 0/4] ARM: shmobile: r8a7740/sh73a0 DT Cache Handling

[Geert Uytterhoeven]

Hi Simon,

On Wed, Nov 25, 2015 at 2:50 AM, Simon Horman <horms@verge.net.au> wrote:
> On Mon, Nov 23, 2015 at 02:55:58PM +0100, Geert Uytterhoeven wrote:
>> This patch series add minimal L1 and L2 cache descriptions to DT for
>> r8a7740 and sh73a0, and migrates the shmobile DT-based generic r8a7740
>> platform from calling l2x0_of_init() to the generic l2c OF
>> initialization.
>>
>> Note that the conversion to the generic l2c OF initialization is not
>> done yet for sh73a0, as this initializes the L2 cache earlier, breaking
>> the (fragile) sh73a0 secondary CPU bringup code.
>>
>> Also note that this conversion should be done on r8a7778, and r8a7779,
>> too.
>
> Based on your work I have prepared a DT patch for the r8a7779.

Thanks for following up.

> I don't think that a C patch is necessary, please correct me if I am wrong.

Yes you do!
Without machine_desc.l2x_aux_{val,mask}, the information in DT is not used.
Cfr. arch/arm/mach-shmobile/setup-r8a7740.c

> Regarding the r8a7778: My reading of the documentation is that although a
> pl310 L2 cache controller is present it is not available for use as there
> is no L2 cache memory present. For this reason I do not think any patches
> are required for the r8a7798.

I agree after consulting the datasheet.

>> Dependencies:
>>   - This series applies to renesas-devel-20151123-v4.4-rc2,
>>   - Patch 3 depends on patch 1,
>>   - Patch 4 depends on patch 3.
>>
>> Given C code changesets depending on DT changesets in the same branch
>> are frowned upon, you may want to postpone patches 3 and 4 to v4.6.
>> Of course I'll sleep better if you just apply all 4 of them now ;-)
>
> I have queued up the DT changes for v4.5.
> And tentatively queued up the C changes for v4.6.

Thank you!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v5 0/4] ARM: shmobile: r8a7740/sh73a0 DT Cache Handling

[Simon Horman]

On Wed, Nov 25, 2015 at 09:45:20AM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
> 
> On Wed, Nov 25, 2015 at 2:50 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Mon, Nov 23, 2015 at 02:55:58PM +0100, Geert Uytterhoeven wrote:
> >> This patch series add minimal L1 and L2 cache descriptions to DT for
> >> r8a7740 and sh73a0, and migrates the shmobile DT-based generic r8a7740
> >> platform from calling l2x0_of_init() to the generic l2c OF
> >> initialization.
> >>
> >> Note that the conversion to the generic l2c OF initialization is not
> >> done yet for sh73a0, as this initializes the L2 cache earlier, breaking
> >> the (fragile) sh73a0 secondary CPU bringup code.
> >>
> >> Also note that this conversion should be done on r8a7778, and r8a7779,
> >> too.
> >
> > Based on your work I have prepared a DT patch for the r8a7779.
> 
> Thanks for following up.
> 
> > I don't think that a C patch is necessary, please correct me if I am wrong.
> 
> Yes you do!
> Without machine_desc.l2x_aux_{val,mask}, the information in DT is not used.
> Cfr. arch/arm/mach-shmobile/setup-r8a7740.c

Thanks, I see "ARM: shmobile: r8a7740: Migrate to generic l2c OF
initialization" with new eyes.

> > Regarding the r8a7778: My reading of the documentation is that although a
> > pl310 L2 cache controller is present it is not available for use as there
> > is no L2 cache memory present. For this reason I do not think any patches
> > are required for the r8a7798.
> 
> I agree after consulting the datasheet.
> 
> >> Dependencies:
> >>   - This series applies to renesas-devel-20151123-v4.4-rc2,
> >>   - Patch 3 depends on patch 1,
> >>   - Patch 4 depends on patch 3.
> >>
> >> Given C code changesets depending on DT changesets in the same branch
> >> are frowned upon, you may want to postpone patches 3 and 4 to v4.6.
> >> Of course I'll sleep better if you just apply all 4 of them now ;-)
> >
> > I have queued up the DT changes for v4.5.
> > And tentatively queued up the C changes for v4.6.
> 
> Thank you!
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
>