From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tiffany Lin Subject: [PATCH v2 4/8] dt-bindings: Add a binding for Mediatek Video Encoder Date: Fri, 11 Dec 2015 17:55:39 +0800 Message-ID: <1449827743-22895-5-git-send-email-tiffany.lin@mediatek.com> References: <1449827743-22895-1-git-send-email-tiffany.lin@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1449827743-22895-1-git-send-email-tiffany.lin-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+glpam-linux-mediatek=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: daniel.thompson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Catalin Marinas , Will Deacon , Mauro Carvalho Chehab , Matthias Brugger , Daniel Kurtz , Hans Verkuil , Laurent Pinchart , Sakari Ailus , Mikhail Ulyanov , Fabien Dessenne , Arnd Bergmann , Darren Etheridge , Peter Griffin , Benoit Parrot Cc: James Liao , Eddie Huang , Daniel Hsiao , Andrew-CT Chen , Hongzhou Yang , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, PoChun.Lin-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, Yingjoe Chen , Tiffany Lin , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org Add a DT binding documentation of Video Encoder for the MT8173 SoC from Mediatek. Signed-off-by: Tiffany Lin --- .../devicetree/bindings/media/mediatek-vcodec.txt | 58 ++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-vcodec.txt diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt new file mode 100644 index 0000000..510cd81 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt @@ -0,0 +1,58 @@ +Mediatek Video Codec + +Mediatek Video Codec is the video codec hw present in Mediatek SoCs which +supports high resolution encoding functionalities. + +Required properties: +- compatible : "mediatek,mt8173-vcodec-enc" for encoder +- reg : Physical base address of the video codec registers and length of + memory mapped region. +- interrupts : interrupt number to the cpu. +- mediatek,larb : must contain the local arbiters in the current Socs. +- clocks : list of clock specifiers, corresponding to entries in + the clock-names property; +- clock-names: must contain "vencpll", "venc_lt_sel", "vcodecpll_370p5_ck" +- iommus : list of iommus specifiers should be enabled for hw encode. + There are 2 cells needed to enable/disable iommu. + The first one is local arbiter index(larbid), and the other is port + index(portid) within local arbiter. Specifies the larbid and portid + as defined in dt-binding/memory/mt8173-larb-port.h. +- mediatek,vpu : the node of video processor unit + +Example: +vcodec_enc: vcodec@0x18002000 { + compatible = "mediatek,mt8173-vcodec-enc"; + reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ + <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ + interrupts = , + ; + larb = <&larb3>, + <&larb5>; + iommus = <&iommu M4U_LARB3_ID M4U_PORT_VENC_RCPU>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REC>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_BSDMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_SV_COMV>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_RD_COMV>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_LUMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_CHROMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_LUMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_CHROMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_RDMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_WDMA>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_CHROMA_SET2>; + vpu = <&vpu>; + clocks = <&apmixedsys CLK_APMIXED_VENCPLL>, + <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_VCODECPLL_370P5>; + clock-names = "vencpll", + "venc_lt_sel", + "vcodecpll_370p5_ck"; + }; -- 1.7.9.5