From mboxrd@z Thu Jan 1 00:00:00 1970 From: Geert Uytterhoeven Subject: [PATCH v2 1/9] ARM: shmobile: alt dts: Enable SCIF_CLK frequency and pins Date: Mon, 14 Dec 2015 19:58:16 +0100 Message-ID: <1450119504-1517-2-git-send-email-geert+renesas@glider.be> References: <1450119504-1517-1-git-send-email-geert+renesas@glider.be> Return-path: In-Reply-To: <1450119504-1517-1-git-send-email-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org To: Simon Horman , Magnus Damm Cc: linux-sh@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven List-Id: devicetree@vger.kernel.org Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by: Geert Uytterhoeven --- Untested, based on schematics. v2: - New. --- arch/arm/boot/dts/r8a7794-alt.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 2394e4883786f13e..f376b9df1f107a47 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -103,6 +103,9 @@ }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + du_pins: du { renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0"; renesas,function = "du"; @@ -113,6 +116,11 @@ renesas,function = "scif2"; }; + scif_clk_pins: scif_clk { + renesas,groups = "scif_clk"; + renesas,function = "scif_clk"; + }; + ether_pins: ether { renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; renesas,function = "eth"; @@ -197,3 +205,8 @@ status = "okay"; }; + +&scif_clk { + clock-frequency = <14745600>; + status = "okay"; +}; -- 1.9.1