* [PATCH 1/5] clk: rockchip: rk3036: include downstream muxes into fractional dividers
2015-12-16 8:27 [PATCH 0/5] Kylin-board is based on RK3036 SOCs, add the initiation Caesar Wang
@ 2015-12-16 8:27 ` Caesar Wang
[not found] ` <1450254441-3243-2-git-send-email-wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2015-12-16 8:27 ` [PATCH 2/5] clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for aclk_vio Caesar Wang
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Caesar Wang @ 2015-12-16 8:27 UTC (permalink / raw)
To: heiko, mturquette, sboyd
Cc: leozwang, keescook, leecam, devicetree, linux-clk,
linux-arm-kernel, linux-kernel, Caesar Wang, Xing Zheng
Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported RK3036 SoCs.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 35 ++++++++++++++++++-----------------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 75553af..dc01a2a 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -227,21 +227,21 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 8, GFLAGS),
- COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
+ COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(17), 0,
- RK2928_CLKGATE_CON(1), 9, GFLAGS),
- COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
- RK2928_CLKSEL_CON(18), 0,
- RK2928_CLKGATE_CON(1), 11, GFLAGS),
- COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
- RK2928_CLKSEL_CON(19), 0,
- RK2928_CLKGATE_CON(1), 13, GFLAGS),
+ RK2928_CLKGATE_CON(1), 9, GFLAGS,
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
- RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
+ RK2928_CLKSEL_CON(13), 8, 2, MFLAGS)),
+ COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(18), 0,
+ RK2928_CLKGATE_CON(1), 11, GFLAGS,
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
- RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
+ RK2928_CLKSEL_CON(14), 8, 2, MFLAGS)),
+ COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(19), 0,
+ RK2928_CLKGATE_CON(1), 13, GFLAGS,
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
- RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
+ RK2928_CLKSEL_CON(15), 8, 2, MFLAGS)),
COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
@@ -289,11 +289,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 9, GFLAGS),
- COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
+ COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(7), 0,
- RK2928_CLKGATE_CON(0), 10, GFLAGS),
+ RK2928_CLKGATE_CON(0), 10, GFLAGS,
MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
- RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
+ RK2928_CLKSEL_CON(3), 8, 2, MFLAGS)),
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
RK2928_CLKGATE_CON(0), 13, GFLAGS),
@@ -303,11 +303,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 10, GFLAGS),
- COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0,
+ COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
RK2928_CLKSEL_CON(9), 0,
- RK2928_CLKGATE_CON(2), 12, GFLAGS),
+ RK2928_CLKGATE_CON(2), 12, GFLAGS,
MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
- RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
+ RK2928_CLKSEL_CON(5), 8, 2, MFLAGS)),
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
@@ -414,6 +414,7 @@ static const char *const rk3036_critical_clocks[] __initconst = {
"aclk_peri",
"hclk_peri",
"pclk_peri",
+ "uart_pll_clk",
};
static void __init rk3036_clk_init(struct device_node *np)
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/5] clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for aclk_vio
2015-12-16 8:27 [PATCH 0/5] Kylin-board is based on RK3036 SOCs, add the initiation Caesar Wang
2015-12-16 8:27 ` [PATCH 1/5] clk: rockchip: rk3036: include downstream muxes into fractional dividers Caesar Wang
@ 2015-12-16 8:27 ` Caesar Wang
2015-12-16 21:24 ` Heiko Stübner
2015-12-16 8:27 ` [PATCH 3/5] ARM: dts: rockchip: update the core dts for rk3036 Caesar Wang
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Caesar Wang @ 2015-12-16 8:27 UTC (permalink / raw)
To: heiko, mturquette, sboyd
Cc: leozwang, keescook, leecam, devicetree, linux-clk,
linux-arm-kernel, linux-kernel, Yakir Yang, Caesar Wang
From: Yakir Yang <ykk@rock-chips.com>
ACLK_VIO is the noc bus clock for display module, display cann't
read data from ddr without this clock enabled.
Due to it shouldn't belong to any driver, but we need it enabled,
so just mark it as the CLK_IGNORE_UNUSED flag.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index dc01a2a..b2cb5af 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -358,7 +358,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
/* aclk_vio gates */
- GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS),
+ GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 2/5] clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for aclk_vio
2015-12-16 8:27 ` [PATCH 2/5] clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for aclk_vio Caesar Wang
@ 2015-12-16 21:24 ` Heiko Stübner
0 siblings, 0 replies; 10+ messages in thread
From: Heiko Stübner @ 2015-12-16 21:24 UTC (permalink / raw)
To: Caesar Wang
Cc: mturquette, sboyd, leozwang, keescook, leecam, devicetree,
linux-clk, linux-arm-kernel, linux-kernel, Yakir Yang
Am Mittwoch, 16. Dezember 2015, 16:27:18 schrieb Caesar Wang:
> From: Yakir Yang <ykk@rock-chips.com>
>
> ACLK_VIO is the noc bus clock for display module, display cann't
> read data from ddr without this clock enabled.
>
> Due to it shouldn't belong to any driver, but we need it enabled,
> so just mark it as the CLK_IGNORE_UNUSED flag.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
applied to my clk-branch for 4.5
Thanks
Heiko
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/5] ARM: dts: rockchip: update the core dts for rk3036
2015-12-16 8:27 [PATCH 0/5] Kylin-board is based on RK3036 SOCs, add the initiation Caesar Wang
2015-12-16 8:27 ` [PATCH 1/5] clk: rockchip: rk3036: include downstream muxes into fractional dividers Caesar Wang
2015-12-16 8:27 ` [PATCH 2/5] clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for aclk_vio Caesar Wang
@ 2015-12-16 8:27 ` Caesar Wang
2015-12-16 13:51 ` Heiko Stübner
2015-12-16 8:27 ` [PATCH 4/5] ARM: dts: rockchip: add the kylin board " Caesar Wang
2015-12-16 8:27 ` [PATCH 5/5] ARM: config: Add the rk3036 configure for kylin board Caesar Wang
4 siblings, 1 reply; 10+ messages in thread
From: Caesar Wang @ 2015-12-16 8:27 UTC (permalink / raw)
To: heiko, mturquette, sboyd
Cc: leozwang, keescook, leecam, devicetree, linux-clk,
linux-arm-kernel, linux-kernel, Caesar Wang
Update the core dts for rk3036 SoCs.
1) Add the display (lcdc, hdmi, vop...) device node.
2) modify the i2s name to i2s0 and i2s1.
Although there is only one i2s IP inside the rk3036,
we need use all of the gpios of i2s0 and i2s1.
So, we add the i2s1 IP is the same with i2s0 to support the
different gpios.
3) Add sdio for wifi module, sdmmc for sd card.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
arch/arm/boot/dts/rk3036.dtsi | 225 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 221 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index f8758bf..574c56c 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -55,6 +55,7 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
mshc0 = &emmc;
+ mshc1 = &sdmmc;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -145,6 +146,63 @@
};
};
+ lcdc_mmu: iommu@10118300 {
+ compatible = "rockchip,iommu";
+ reg = <0x10118300 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lcdc_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ lcdc: lcdc@10118000 {
+ compatible = "rockchip,rk3036-lcdc";
+ reg = <0x10118000 0x19c>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
+ reset-names = "axi", "ahb", "dclk";
+ iommus = <&lcdc_mmu>;
+
+ status = "disabled";
+
+ lcdc_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ lcdc_out_hdmi: endpoint@0 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_lcdc>;
+ };
+ };
+ };
+
+ hdmi: hdmi@20034000 {
+ compatible = "rockchip,rk3036-inno-hdmi";
+ reg = <0x20034000 0x4000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI>;
+ clock-names = "pclk";
+ rockchip,grf = <&grf>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_ctl>;
+ status = "disabled";
+
+ hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ hdmi_in_lcdc: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&lcdc_out_hdmi>;
+ };
+ };
+ };
+
+ display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&lcdc_out>;
+ };
+
gic: interrupt-controller@10139000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -158,6 +216,21 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ usbphy: phy {
+ compatible = "rockchip,rk3036-usb-phy";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ usbphy0: usb-phy0 {
+ #phy-cells = <0>;
+ reg = <0x17c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ };
+ };
+
usb_otg: usb@10180000 {
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
"snps,dwc2";
@@ -184,6 +257,30 @@
status = "disabled";
};
+ sdmmc: dwmmc@10214000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ clock-frequency = <37500000>;
+ clock-freq-min-max = <400000 37500000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x10214000 0x4000>;
+ status = "disabled";
+ };
+
+ sdio: dwmmc@10218000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 37500000>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x10218000 0x4000>;
+ status = "disabled";
+ };
+
emmc: dwmmc@1021c000 {
compatible = "rockchip,rk3288-dw-mshc";
reg = <0x1021c000 0x4000>;
@@ -209,18 +306,33 @@
status = "disabled";
};
- i2s: i2s@10220000 {
+ i2s0: i2s0@10220000 {
compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
reg = <0x10220000 0x4000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&pdma 0>, <&pdma 1>;
+ dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_bus>;
+ status = "disabled";
+ };
+
+ i2s1: i2s1@10220000 {
+ compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
+ reg = <0x10220000 0x4000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
dmas = <&pdma 0>, <&pdma 1>;
dma-names = "tx", "rx";
+ clock-names = "i2s_hclk", "i2s_clk";
+ clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>;
pinctrl-names = "default";
- pinctrl-0 = <&i2s_bus>;
+ pinctrl-0 = <&i2s1_bus>;
status = "disabled";
};
@@ -378,6 +490,33 @@
clocks = <&cru PCLK_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
+ };
+
+ usb_otg: usb@10180000 {
+ compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x10180000 0x40000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG0>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <275>;
+ g-tx-fifo-size = <256 128 128 64 64 32>;
+ g-use-dma;
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host: usb@101c0000 {
+ compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x101c0000 0x40000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG1>;
+ clock-names = "otg";
+ dr_mode = "host";
status = "disabled";
};
@@ -463,6 +602,52 @@
};
};
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_cd: sdmcc-cd {
+ rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_bus1: sdmmc-bus1 {
+ rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_up>,
+ <1 19 RK_FUNC_1 &pcfg_pull_up>,
+ <1 20 RK_FUNC_1 &pcfg_pull_up>,
+ <1 21 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ sdio {
+ sdio_bus1: sdio-bus1 {
+ rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdio_bus4: sdio-bus4 {
+ rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_none>,
+ <0 12 RK_FUNC_1 &pcfg_pull_none>,
+ <0 13 RK_FUNC_1 &pcfg_pull_none>,
+ <0 14 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdio_cmd: sdio-cmd {
+ rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdio_clk: sdio-clk {
+ rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
emmc {
/*
* We run eMMC at max speed; bump up drive strength.
@@ -488,6 +673,15 @@
};
};
+ hdmi {
+ hdmi_ctl: hdmi-ctl {
+ rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
+ <1 9 RK_FUNC_1 &pcfg_pull_none>,
+ <1 10 RK_FUNC_1 &pcfg_pull_none>,
+ <1 11 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
@@ -509,8 +703,8 @@
};
};
- i2s {
- i2s_bus: i2s-bus {
+ i2s0 {
+ i2s0_bus: i2s0-bus {
rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_none>,
<1 1 RK_FUNC_1 &pcfg_pull_none>,
<1 2 RK_FUNC_1 &pcfg_pull_none>,
@@ -518,6 +712,29 @@
<1 4 RK_FUNC_1 &pcfg_pull_none>,
<1 5 RK_FUNC_1 &pcfg_pull_none>;
};
+
+ i2s0_bus8ch: i2s0-bus8ch {
+ rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_none>,
+ <1 1 RK_FUNC_1 &pcfg_pull_none>,
+ <1 2 RK_FUNC_1 &pcfg_pull_none>,
+ <1 3 RK_FUNC_1 &pcfg_pull_none>,
+ <1 4 RK_FUNC_1 &pcfg_pull_none>,
+ <1 5 RK_FUNC_1 &pcfg_pull_none>,
+ <2 28 RK_FUNC_1 &pcfg_pull_none>,
+ <2 29 RK_FUNC_1 &pcfg_pull_none>,
+ <2 30 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s1 {
+ i2s1_bus: i2s1-bus {
+ rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>,
+ <0 9 RK_FUNC_2 &pcfg_pull_none>,
+ <0 11 RK_FUNC_2 &pcfg_pull_none>,
+ <0 12 RK_FUNC_2 &pcfg_pull_none>,
+ <0 13 RK_FUNC_2 &pcfg_pull_none>,
+ <0 14 RK_FUNC_2 &pcfg_pull_none>;
+ };
};
uart0 {
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 3/5] ARM: dts: rockchip: update the core dts for rk3036
2015-12-16 8:27 ` [PATCH 3/5] ARM: dts: rockchip: update the core dts for rk3036 Caesar Wang
@ 2015-12-16 13:51 ` Heiko Stübner
0 siblings, 0 replies; 10+ messages in thread
From: Heiko Stübner @ 2015-12-16 13:51 UTC (permalink / raw)
To: Caesar Wang
Cc: mturquette, sboyd, leozwang, keescook, leecam, devicetree,
linux-clk, linux-arm-kernel, linux-kernel
Hi Caesar,
Am Mittwoch, 16. Dezember 2015, 16:27:19 schrieb Caesar Wang:
> Update the core dts for rk3036 SoCs.
>
> 1) Add the display (lcdc, hdmi, vop...) device node.
> 2) modify the i2s name to i2s0 and i2s1.
> Although there is only one i2s IP inside the rk3036,
> we need use all of the gpios of i2s0 and i2s1.
> So, we add the i2s1 IP is the same with i2s0 to support the
> different gpios.
> 3) Add sdio for wifi module, sdmmc for sd card.
if you need a list to describe changes, it is a good indication that this
needs to be split into separate patches.
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> ---
>
> arch/arm/boot/dts/rk3036.dtsi | 225
> +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 221
> insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
> index f8758bf..574c56c 100644
> --- a/arch/arm/boot/dts/rk3036.dtsi
> +++ b/arch/arm/boot/dts/rk3036.dtsi
> @@ -55,6 +55,7 @@
> i2c1 = &i2c1;
> i2c2 = &i2c2;
> mshc0 = &emmc;
> + mshc1 = &sdmmc;
> serial0 = &uart0;
> serial1 = &uart1;
> serial2 = &uart2;
> @@ -145,6 +146,63 @@
> };
> };
>
> + lcdc_mmu: iommu@10118300 {
> + compatible = "rockchip,iommu";
> + reg = <0x10118300 0x100>;
> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "lcdc_mmu";
> + #iommu-cells = <0>;
> + status = "disabled";
> + };
> +
> + lcdc: lcdc@10118000 {
> + compatible = "rockchip,rk3036-lcdc";
> + reg = <0x10118000 0x19c>;
> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
> + clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
> + resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
> + reset-names = "axi", "ahb", "dclk";
> + iommus = <&lcdc_mmu>;
> +
> + status = "disabled";
> +
> + lcdc_out: port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + lcdc_out_hdmi: endpoint@0 {
> + reg = <1>;
> + remote-endpoint = <&hdmi_in_lcdc>;
> + };
> + };
> + };
please only add nodes for things _after_ they are posted and applied by the
maintainer (Mark Yao in this case)
> + hdmi: hdmi@20034000 {
> + compatible = "rockchip,rk3036-inno-hdmi";
> + reg = <0x20034000 0x4000>;
> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_HDMI>;
> + clock-names = "pclk";
> + rockchip,grf = <&grf>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmi_ctl>;
> + status = "disabled";
> +
> + hdmi_in: port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + hdmi_in_lcdc: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&lcdc_out_hdmi>;
> + };
> + };
> + };
same as above
> +
> + display-subsystem {
> + compatible = "rockchip,display-subsystem";
> + ports = <&lcdc_out>;
> + };
> +
> gic: interrupt-controller@10139000 {
> compatible = "arm,gic-400";
> interrupt-controller;
> @@ -158,6 +216,21 @@
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
> };
>
> + usbphy: phy {
> + compatible = "rockchip,rk3036-usb-phy";
> + rockchip,grf = <&grf>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + usbphy0: usb-phy0 {
> + #phy-cells = <0>;
> + reg = <0x17c>;
> + clocks = <&cru SCLK_OTGPHY0>;
> + clock-names = "phyclk";
> + };
> + };
> +
same as above - no driver. With the addition, that the usbphy on rk3036,
rk3368 (and probably more) is a new IP (Innosilicon it seems instead of the
DWC picophy) and includes a whole additional set of function registers
(GRF_USBPHYx_CONy...) to control the phy block, so this should definitly also
be a separate driver.
Especially also as I'm not yet clear on the clock situation.
On rk3036 sclk_otgphy0 seems to be supplying the phyblock directly (and both
the HOST and OTG phys).
On rk3228 the phy block has two supplying clocks for 1 OTG and 3 HOSTs (and I
haven't been able to figure out which is supplying which usb block yet)
etc.
> usb_otg: usb@10180000 {
> compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
> "snps,dwc2";
you probably want something like
compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
"snps,dwc2";
> @@ -184,6 +257,30 @@
> status = "disabled";
> };
>
> + sdmmc: dwmmc@10214000 {
> + compatible = "rockchip,rk3288-dw-mshc";
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
It seems I overlooked that for the emmc
> + clock-frequency = <37500000>;
> + clock-freq-min-max = <400000 37500000>;
> + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x10214000 0x4000>;
> + status = "disabled";
> + };
> +
> + sdio: dwmmc@10218000 {
> + compatible = "rockchip,rk3288-dw-mshc";
> + clock-freq-min-max = <400000 37500000>;
> + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
> + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
> + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x10218000 0x4000>;
> + status = "disabled";
> + };
> +
> emmc: dwmmc@1021c000 {
> compatible = "rockchip,rk3288-dw-mshc";
> reg = <0x1021c000 0x4000>;
> @@ -209,18 +306,33 @@
> status = "disabled";
> };
>
> - i2s: i2s@10220000 {
> + i2s0: i2s0@10220000 {
> compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
> reg = <0x10220000 0x4000>;
> interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + dmas = <&pdma 0>, <&pdma 1>;
> + dma-names = "tx", "rx";
> clock-names = "i2s_hclk", "i2s_clk";
> clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2s0_bus>;
> + status = "disabled";
> + };
> +
> + i2s1: i2s1@10220000 {
> + compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
> + reg = <0x10220000 0x4000>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> dmas = <&pdma 0>, <&pdma 1>;
> dma-names = "tx", "rx";
> + clock-names = "i2s_hclk", "i2s_clk";
> + clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>;
> pinctrl-names = "default";
> - pinctrl-0 = <&i2s_bus>;
> + pinctrl-0 = <&i2s1_bus>;
> status = "disabled";
> };
That looks wrong. If I understand you correctly, there is one i2s block (which
I found in the manual) but you can decide which of two pingroups it should use
(either what you call is20 or i2s1), right?
In this case the soc-level dtsi should only declare the groups below, but not
assign any of them and leave that to the board-level dts file to select the
correct one (Instead of declaring a second i2s host, if there isn't any).
> @@ -378,6 +490,33 @@
> clocks = <&cru PCLK_I2C0>;
> pinctrl-names = "default";
> pinctrl-0 = <&i2c0_xfer>;
> + };
> +
> + usb_otg: usb@10180000 {
> + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
> + "snps,dwc2";
> + reg = <0x10180000 0x40000>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_OTG0>;
> + clock-names = "otg";
> + dr_mode = "otg";
> + g-np-tx-fifo-size = <16>;
> + g-rx-fifo-size = <275>;
> + g-tx-fifo-size = <256 128 128 64 64 32>;
> + g-use-dma;
> + phys = <&usbphy0>;
> + phy-names = "usb2-phy";
> + status = "disabled";
> + };
looks like a duplicate ... otg is also present above already
> +
> + usb_host: usb@101c0000 {
> + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
> + "snps,dwc2";
again probably
compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
"snps,dwc2";
> + reg = <0x101c0000 0x40000>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_OTG1>;
> + clock-names = "otg";
> + dr_mode = "host";
> status = "disabled";
> };
>
Heiko
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 4/5] ARM: dts: rockchip: add the kylin board for rk3036
2015-12-16 8:27 [PATCH 0/5] Kylin-board is based on RK3036 SOCs, add the initiation Caesar Wang
` (2 preceding siblings ...)
2015-12-16 8:27 ` [PATCH 3/5] ARM: dts: rockchip: update the core dts for rk3036 Caesar Wang
@ 2015-12-16 8:27 ` Caesar Wang
2015-12-16 8:27 ` [PATCH 5/5] ARM: config: Add the rk3036 configure for kylin board Caesar Wang
4 siblings, 0 replies; 10+ messages in thread
From: Caesar Wang @ 2015-12-16 8:27 UTC (permalink / raw)
To: heiko, mturquette, sboyd
Cc: leozwang, keescook, leecam, devicetree, linux-clk,
linux-arm-kernel, linux-kernel, Caesar Wang
This patchset is the initiation version to try work
for kylin board.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
Documentation/devicetree/bindings/arm/rockchip.txt | 4 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk3036-kylin.dts | 302 +++++++++++++++++++++
3 files changed, 307 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3036-kylin.dts
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index c40c091..56653c4 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -1,6 +1,10 @@
Rockchip platforms device tree bindings
---------------------------------------
+- Kylin RK3036 board:
+ Required root node properties:
+ - compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";
+
- MarsBoard RK3066 board:
Required root node properties:
- compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5e284dd..b911601 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -513,6 +513,7 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-evb.dtb \
+ rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
new file mode 100644
index 0000000..b6a9908
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -0,0 +1,302 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+ model = "Rockchip RK3036 KylinBoard";
+ compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&acodec {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &global_pwroff>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_18>;
+ vcc9-supply = <&vcc_io>;
+ vcc10-supply = <&vcc_io>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_io>;
+ vddio-supply = <&vccio_pmu>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_arm";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_io";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_pmu: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_tp: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_tp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_10";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc18_lcd: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_lcd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vout5: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vout5";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_18";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca_codec: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca_codec";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_wl: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_wl";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_lcd: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_lcd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&lcdc {
+ status = "okay";
+};
+
+&lcdc_mmu {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&pinctrl {
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <2 2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sleep {
+ global_pwroff: global-pwroff {
+ rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 5/5] ARM: config: Add the rk3036 configure for kylin board
2015-12-16 8:27 [PATCH 0/5] Kylin-board is based on RK3036 SOCs, add the initiation Caesar Wang
` (3 preceding siblings ...)
2015-12-16 8:27 ` [PATCH 4/5] ARM: dts: rockchip: add the kylin board " Caesar Wang
@ 2015-12-16 8:27 ` Caesar Wang
2015-12-16 13:54 ` Heiko Stübner
4 siblings, 1 reply; 10+ messages in thread
From: Caesar Wang @ 2015-12-16 8:27 UTC (permalink / raw)
To: heiko, mturquette, sboyd
Cc: leozwang, keescook, leecam, devicetree, linux-clk,
linux-arm-kernel, linux-kernel, Caesar Wang
Add RK3036-specific configuration for Kylin board.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
arch/arm/configs/rk3036_kylin_defconfig | 230 ++++++++++++++++++++++++++++++++
1 file changed, 230 insertions(+)
create mode 100644 arch/arm/configs/rk3036_kylin_defconfig
diff --git a/arch/arm/configs/rk3036_kylin_defconfig b/arch/arm/configs/rk3036_kylin_defconfig
new file mode 100644
index 0000000..692c393
--- /dev/null
+++ b/arch/arm/configs/rk3036_kylin_defconfig
@@ -0,0 +1,230 @@
+CONFIG_CROSS_COMPILE="arm-linux-gnueabi-"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_DEFAULT_HOSTNAME="radxarock"
+CONFIG_SYSVIPC=y
+# CONFIG_USELIB is not set
+CONFIG_AUDIT=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+# CONFIG_COMPACTION is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_CLEANCACHE=y
+CONFIG_FRONTSWAP=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_DEBUG=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_RFKILL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_SRAM=y
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=600
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_MISC=y
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_RK3X=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_SENSORS_IIO_HWMON=y
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_SOFT_WATCHDOG=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_TPS65910=y
+CONFIG_REGULATOR_DEBUG=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_ACT8865=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_DRM=y
+CONFIG_DRM_ROCKCHIP=y
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_ROCKCHIP=y
+CONFIG_SND_SOC_ROCKCHIP_I2S=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_OTG=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_PLATFORM=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_G_ANDROID=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_HYM8563=y
+CONFIG_RTC_DRV_RK808=y
+CONFIG_DMADEVICES=y
+CONFIG_DMADEVICES_DEBUG=y
+CONFIG_DMADEVICES_VDEBUG=y
+CONFIG_PL330_DMA=y
+CONFIG_ASYNC_TX_DMA=y
+CONFIG_STAGING=y
+CONFIG_R8188EU=y
+CONFIG_R8723AU=y
+CONFIG_ASHMEM=y
+CONFIG_ANDROID_TIMED_GPIO=y
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_SYNC=y
+CONFIG_SW_SYNC=y
+CONFIG_SW_SYNC_USER=y
+CONFIG_ION=y
+CONFIG_ION_DUMMY=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_IIO=y
+CONFIG_ROCKCHIP_SARADC=y
+CONFIG_INV_MPU6050_IIO=y
+CONFIG_AK8975=y
+CONFIG_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=2048
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_TIMER_STATS=y
+CONFIG_KGDB=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_RK29_UART2=y
+CONFIG_DEBUG_UART_8250_WORD=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_DISABLE=y
+# CONFIG_SECURITY_SELINUX_AVC_STATS is not set
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 5/5] ARM: config: Add the rk3036 configure for kylin board
2015-12-16 8:27 ` [PATCH 5/5] ARM: config: Add the rk3036 configure for kylin board Caesar Wang
@ 2015-12-16 13:54 ` Heiko Stübner
0 siblings, 0 replies; 10+ messages in thread
From: Heiko Stübner @ 2015-12-16 13:54 UTC (permalink / raw)
To: Caesar Wang
Cc: mturquette, sboyd, leozwang, keescook, leecam, devicetree,
linux-clk, linux-arm-kernel, linux-kernel
Hi Caesar,
Am Mittwoch, 16. Dezember 2015, 16:27:21 schrieb Caesar Wang:
> Add RK3036-specific configuration for Kylin board.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
I don't think we generally do per-board defconfigs in the mainline kernel
anymore. If you are missing specific functionality, please add them as patch
to the multi_v7_defconfig (ideally as module).
Heiko
>
> ---
>
> arch/arm/configs/rk3036_kylin_defconfig | 230
> ++++++++++++++++++++++++++++++++ 1 file changed, 230 insertions(+)
> create mode 100644 arch/arm/configs/rk3036_kylin_defconfig
>
> diff --git a/arch/arm/configs/rk3036_kylin_defconfig
> b/arch/arm/configs/rk3036_kylin_defconfig new file mode 100644
> index 0000000..692c393
> --- /dev/null
> +++ b/arch/arm/configs/rk3036_kylin_defconfig
> @@ -0,0 +1,230 @@
> +CONFIG_CROSS_COMPILE="arm-linux-gnueabi-"
> +# CONFIG_LOCALVERSION_AUTO is not set
> +CONFIG_DEFAULT_HOSTNAME="radxarock"
> +CONFIG_SYSVIPC=y
> +# CONFIG_USELIB is not set
> +CONFIG_AUDIT=y
> +CONFIG_IRQ_DOMAIN_DEBUG=y
> +CONFIG_BLK_DEV_INITRD=y
> +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> +CONFIG_PERF_EVENTS=y
> +# CONFIG_COMPAT_BRK is not set
> +CONFIG_SLAB=y
> +CONFIG_JUMP_LABEL=y
> +CONFIG_MODULES=y
> +CONFIG_MODULE_FORCE_LOAD=y
> +CONFIG_MODULE_UNLOAD=y
> +CONFIG_PARTITION_ADVANCED=y
> +# CONFIG_IOSCHED_CFQ is not set
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_PL310_ERRATA_588369=y
> +CONFIG_PL310_ERRATA_727915=y
> +CONFIG_ARM_ERRATA_720789=y
> +CONFIG_ARM_ERRATA_754322=y
> +CONFIG_SMP=y
> +CONFIG_NR_CPUS=2
> +CONFIG_PREEMPT_VOLUNTARY=y
> +CONFIG_AEABI=y
> +CONFIG_HIGHMEM=y
> +# CONFIG_COMPACTION is not set
> +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
> +CONFIG_CLEANCACHE=y
> +CONFIG_FRONTSWAP=y
> +CONFIG_ZBOOT_ROM_TEXT=0x0
> +CONFIG_ARM_APPENDED_DTB=y
> +CONFIG_ARM_ATAG_DTB_COMPAT=y
> +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y
> +CONFIG_CPU_FREQ=y
> +CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
> +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
> +CONFIG_CPUFREQ_DT=y
> +CONFIG_CPU_IDLE=y
> +CONFIG_VFP=y
> +CONFIG_NEON=y
> +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> +CONFIG_PM_WAKELOCKS=y
> +CONFIG_PM_DEBUG=y
> +CONFIG_NET=y
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_INET=y
> +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> +# CONFIG_INET_XFRM_MODE_BEET is not set
> +# CONFIG_INET_LRO is not set
> +# CONFIG_INET_DIAG is not set
> +# CONFIG_IPV6 is not set
> +CONFIG_CFG80211_WEXT=y
> +CONFIG_RFKILL=y
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
> +# CONFIG_FIRMWARE_IN_KERNEL is not set
> +CONFIG_BLK_DEV_LOOP=y
> +CONFIG_BLK_DEV_RAM=y
> +CONFIG_BLK_DEV_RAM_COUNT=1
> +CONFIG_BLK_DEV_RAM_SIZE=16384
> +CONFIG_SRAM=y
> +CONFIG_SCSI=y
> +# CONFIG_SCSI_PROC_FS is not set
> +CONFIG_BLK_DEV_SD=y
> +# CONFIG_SCSI_LOWLEVEL is not set
> +CONFIG_NETDEVICES=y
> +# CONFIG_NET_CADENCE is not set
> +# CONFIG_NET_VENDOR_BROADCOM is not set
> +# CONFIG_NET_VENDOR_CIRRUS is not set
> +# CONFIG_NET_VENDOR_FARADAY is not set
> +# CONFIG_NET_VENDOR_INTEL is not set
> +# CONFIG_NET_VENDOR_MARVELL is not set
> +# CONFIG_NET_VENDOR_MICREL is not set
> +# CONFIG_NET_VENDOR_NATSEMI is not set
> +# CONFIG_NET_VENDOR_SAMSUNG is not set
> +# CONFIG_NET_VENDOR_SEEQ is not set
> +# CONFIG_NET_VENDOR_SMSC is not set
> +CONFIG_STMMAC_ETH=y
> +# CONFIG_NET_VENDOR_VIA is not set
> +# CONFIG_NET_VENDOR_WIZNET is not set
> +CONFIG_SMSC_PHY=y
> +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> +CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
> +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=600
> +CONFIG_INPUT_EVDEV=y
> +# CONFIG_KEYBOARD_ATKBD is not set
> +CONFIG_KEYBOARD_GPIO=y
> +CONFIG_KEYBOARD_GPIO_POLLED=y
> +# CONFIG_INPUT_MOUSE is not set
> +CONFIG_INPUT_TOUCHSCREEN=y
> +CONFIG_INPUT_MISC=y
> +# CONFIG_SERIO is not set
> +# CONFIG_LEGACY_PTYS is not set
> +# CONFIG_DEVKMEM is not set
> +CONFIG_SERIAL_8250=y
> +CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_8250_DW=y
> +# CONFIG_HW_RANDOM is not set
> +CONFIG_I2C_CHARDEV=y
> +CONFIG_I2C_GPIO=y
> +CONFIG_I2C_RK3X=y
> +CONFIG_GPIO_DWAPB=y
> +CONFIG_POWER_SUPPLY=y
> +CONFIG_POWER_RESET=y
> +CONFIG_SENSORS_IIO_HWMON=y
> +CONFIG_THERMAL=y
> +CONFIG_CPU_THERMAL=y
> +CONFIG_WATCHDOG=y
> +CONFIG_SOFT_WATCHDOG=y
> +CONFIG_MFD_RK808=y
> +CONFIG_MFD_TPS65910=y
> +CONFIG_REGULATOR_DEBUG=y
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> +CONFIG_REGULATOR_ACT8865=y
> +CONFIG_REGULATOR_FAN53555=y
> +CONFIG_REGULATOR_RK808=y
> +CONFIG_DRM=y
> +CONFIG_DRM_ROCKCHIP=y
> +CONFIG_ROCKCHIP_DW_HDMI=y
> +CONFIG_ROCKCHIP_INNO_HDMI=y
> +CONFIG_DRM_PANEL_SIMPLE=y
> +CONFIG_FB_MODE_HELPERS=y
> +CONFIG_BACKLIGHT_LCD_SUPPORT=y
> +CONFIG_LCD_CLASS_DEVICE=y
> +CONFIG_BACKLIGHT_CLASS_DEVICE=y
> +# CONFIG_BACKLIGHT_GENERIC is not set
> +CONFIG_BACKLIGHT_PWM=y
> +CONFIG_SOUND=y
> +CONFIG_SND=y
> +CONFIG_SND_SOC=y
> +CONFIG_SND_SOC_ROCKCHIP=y
> +CONFIG_SND_SOC_ROCKCHIP_I2S=y
> +CONFIG_SND_SIMPLE_CARD=y
> +CONFIG_USB=y
> +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
> +CONFIG_USB_OTG=y
> +CONFIG_USB_MON=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_DWC2=y
> +CONFIG_USB_DWC2_PLATFORM=y
> +CONFIG_NOP_USB_XCEIV=y
> +CONFIG_USB_ULPI=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_G_ANDROID=y
> +CONFIG_MMC=y
> +CONFIG_MMC_BLOCK_MINORS=32
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_NEW_LEDS=y
> +CONFIG_LEDS_CLASS=y
> +CONFIG_LEDS_GPIO=y
> +CONFIG_LEDS_TRIGGERS=y
> +CONFIG_LEDS_TRIGGER_TIMER=y
> +CONFIG_LEDS_TRIGGER_ONESHOT=y
> +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> +CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_HYM8563=y
> +CONFIG_RTC_DRV_RK808=y
> +CONFIG_DMADEVICES=y
> +CONFIG_DMADEVICES_DEBUG=y
> +CONFIG_DMADEVICES_VDEBUG=y
> +CONFIG_PL330_DMA=y
> +CONFIG_ASYNC_TX_DMA=y
> +CONFIG_STAGING=y
> +CONFIG_R8188EU=y
> +CONFIG_R8723AU=y
> +CONFIG_ASHMEM=y
> +CONFIG_ANDROID_TIMED_GPIO=y
> +CONFIG_ANDROID_LOW_MEMORY_KILLER=y
> +CONFIG_SYNC=y
> +CONFIG_SW_SYNC=y
> +CONFIG_SW_SYNC_USER=y
> +CONFIG_ION=y
> +CONFIG_ION_DUMMY=y
> +CONFIG_COMMON_CLK_RK808=y
> +CONFIG_ROCKCHIP_IOMMU=y
> +CONFIG_IIO=y
> +CONFIG_ROCKCHIP_SARADC=y
> +CONFIG_INV_MPU6050_IIO=y
> +CONFIG_AK8975=y
> +CONFIG_PWM=y
> +CONFIG_PWM_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_USB=y
> +CONFIG_ANDROID=y
> +CONFIG_ANDROID_BINDER_IPC=y
> +CONFIG_EXT2_FS=y
> +CONFIG_EXT3_FS=y
> +# CONFIG_EXT3_FS_XATTR is not set
> +CONFIG_EXT4_FS=y
> +CONFIG_EXT4_FS_SECURITY=y
> +# CONFIG_DNOTIFY is not set
> +CONFIG_MSDOS_FS=y
> +CONFIG_VFAT_FS=y
> +CONFIG_TMPFS=y
> +# CONFIG_NETWORK_FILESYSTEMS is not set
> +CONFIG_NLS_CODEPAGE_437=y
> +CONFIG_NLS_CODEPAGE_850=y
> +CONFIG_NLS_CODEPAGE_852=y
> +CONFIG_NLS_ASCII=y
> +CONFIG_NLS_ISO8859_1=y
> +CONFIG_NLS_ISO8859_15=y
> +CONFIG_NLS_UTF8=y
> +CONFIG_PRINTK_TIME=y
> +CONFIG_DYNAMIC_DEBUG=y
> +CONFIG_DEBUG_INFO=y
> +# CONFIG_ENABLE_WARN_DEPRECATED is not set
> +# CONFIG_ENABLE_MUST_CHECK is not set
> +CONFIG_FRAME_WARN=2048
> +CONFIG_DEBUG_FS=y
> +CONFIG_DEBUG_KERNEL=y
> +# CONFIG_SCHED_DEBUG is not set
> +CONFIG_TIMER_STATS=y
> +CONFIG_KGDB=y
> +CONFIG_DEBUG_LL=y
> +CONFIG_DEBUG_RK29_UART2=y
> +CONFIG_DEBUG_UART_8250_WORD=y
> +CONFIG_EARLY_PRINTK=y
> +CONFIG_SECURITY=y
> +CONFIG_SECURITY_NETWORK=y
> +CONFIG_SECURITY_SELINUX=y
> +CONFIG_SECURITY_SELINUX_DISABLE=y
> +# CONFIG_SECURITY_SELINUX_AVC_STATS is not set
> +CONFIG_CRYPTO_ANSI_CPRNG=y
> +# CONFIG_CRYPTO_HW is not set
^ permalink raw reply [flat|nested] 10+ messages in thread