* [PATCH] arm64: dts: Add L2 cache node to msm8916
@ 2016-01-08 23:57 Stephen Boyd
2016-01-09 4:41 ` Andy Gross
0 siblings, 1 reply; 2+ messages in thread
From: Stephen Boyd @ 2016-01-08 23:57 UTC (permalink / raw)
To: Andy Gross; +Cc: linux-kernel, linux-arm-msm, linux-arm-kernel, devicetree
The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the
dtsi file so that the cache hierarchy can be probed.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index ba8184d0f948..42573a7d4a94 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -61,24 +61,33 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0>;
+ next-level-cache = <&L2_0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x1>;
+ next-level-cache = <&L2_0>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x2>;
+ next-level-cache = <&L2_0>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] arm64: dts: Add L2 cache node to msm8916
2016-01-08 23:57 [PATCH] arm64: dts: Add L2 cache node to msm8916 Stephen Boyd
@ 2016-01-09 4:41 ` Andy Gross
0 siblings, 0 replies; 2+ messages in thread
From: Andy Gross @ 2016-01-09 4:41 UTC (permalink / raw)
To: Stephen Boyd; +Cc: linux-kernel, linux-arm-msm, linux-arm-kernel, devicetree
On Fri, Jan 08, 2016 at 03:57:09PM -0800, Stephen Boyd wrote:
> The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the
> dtsi file so that the cache hierarchy can be probed.
>
> Cc: <devicetree@vger.kernel.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
Reviewed-by: Andy Gross <andy.gross@linaro.org>
^ permalink raw reply [flat|nested] 2+ messages in thread
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