[PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.

[PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.

[Subbaraya Sundeep Bhatta]

This patch adds the document describing dt bindings for ZynqMP
PHY. ZynqMP SOC has a High Speed Processing System Gigabit
Transceiver which provides PHY capabilties to USB, SATA,
PCIE, Display Port and Ehernet SGMII controllers.

Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
 v2:
	modified to use phy cells as 2.

 .../devicetree/bindings/phy/phy-zynqmp.txt         | 103 +++++++++++++++++++++
 1 file changed, 103 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-zynqmp.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
new file mode 100644
index 0000000..975cf21
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
@@ -0,0 +1,103 @@
+Xilinx ZynqMP PHY binding
+
+This binding describes a ZynqMP PHY device that is used to control ZynqMP
+High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides four lanes
+and are used by USB, SATA, PCIE, Display port and Ethernet SGMMI controllers.
+
+Required properties (controller (parent) node):
+- compatible    : Should be "xlnx,zynqmp-psgtr"
+
+- reg		: Address and length of register sets for each device in
+		  "reg-names"
+- reg-names     : The names of the register addresses corresponding to the
+		  registers filled in "reg":
+			- serdes: SERDES block register set
+			- siou: SIOU block register set
+			- lpd: Low power domain peripherals reset control
+			- fpd: Full power domain peripherals reset control
+
+-xlnx,tx_termination_fix: Include fix for a functional issue in the GT. The TX
+			  termination resistance can be out of spec due to a
+			  bug in the calibration logic. This issue will be fixed
+			  in silicon in future versions.
+
+Required nodes	:  A sub-node is required for each lane the controller
+		   provides.
+
+Required properties (port (child) nodes):
+lane0:
+- #phy-cells	: Should be 2
+		  Cell after port phandle is device type from:
+			- <PHY_TYPE_PCIE 0>
+			- <PHY_TYPE_SATA 0>
+			- <PHY_TYPE_USB3 0>
+			- <PHY_TYPE_DP 1>
+			- <PHY_TYPE_SGMII 0>
+lane1:
+- #phy-cells	: Should be 2
+		  Cell after port phandle is device type from:
+			- <PHY_TYPE_PCIE 1>
+			- <PHY_TYPE_SATA 1>
+			- <PHY_TYPE_USB3 0>
+			- <PHY_TYPE_DP 0>
+			- <PHY_TYPE_SGMII 1>
+lane2:
+- #phy-cells	: Should be 2
+		  Cell after port phandle is device type from:
+			- <PHY_TYPE_PCIE 2>
+			- <PHY_TYPE_SATA 0>
+			- <PHY_TYPE_USB3 0>
+			- <PHY_TYPE_DP 1>
+			- <PHY_TYPE_SGMII 2>
+lane3:
+- #phy-cells	: Should be 2
+		  Cell after port phandle is device type from:
+			- <PHY_TYPE_PCIE 3>
+			- <PHY_TYPE_SATA 1>
+			- <PHY_TYPE_USB3 1>
+			- <PHY_TYPE_DP 0>
+			- <PHY_TYPE_SGMII 3>
+
+Example:
+	zynqmp_phy@fd400000 {
+		compatible = "xlnx,zynqmp-psgtr";
+		status = "okay";
+		reg = <0x0 0xfd400000 0x40000>, <0x0 0xfd3d0000 0x1000>,
+			<0x0 0xfd1a0000 0x1000>, <0x0 0xff5e0000 0x1000>;
+		reg-names = "serdes", "siou", "fpd", "lpd";
+
+		lane0: lane@0 {
+			#phy-cells = <2>;
+		};
+		lane1: lane@1 {
+			#phy-cells = <2>;
+		};
+		lane2: lane@2 {
+			#phy-cells = <2>;
+		};
+		lane3: lane@3 {
+			#phy-cells = <2>;
+		};
+	};
+
+Specifying phy control of devices
+=================================
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the phy port node and a device type.
+
+Example:
+
+#include <dt-bindings/phy/phy.h>
+
+	usb@fe200000 {
+		...
+		phys	  = <&lane2 PHY_TYPE_USB3 0>;
+		...
+	};
+
+	ahci@fd0c0000 {
+		...
+		phys	  = <&lane3 PHY_TYPE_SATA 1>;
+		...
+	};
-- 
2.1.2

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Re: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.

[Sören Brinkmann]

On Wed, 2016-01-13 at 07:43PM +0530, Subbaraya Sundeep Bhatta wrote:
> This patch adds the document describing dt bindings for ZynqMP
> PHY. ZynqMP SOC has a High Speed Processing System Gigabit
> Transceiver which provides PHY capabilties to USB, SATA,
> PCIE, Display Port and Ehernet SGMII controllers.
> 
> Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>

I missed the v2 hence again.

> ---
>  v2:
> 	modified to use phy cells as 2.
> 
>  .../devicetree/bindings/phy/phy-zynqmp.txt         | 103 +++++++++++++++++++++
>  1 file changed, 103 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> new file mode 100644
> index 0000000..975cf21
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> @@ -0,0 +1,103 @@
> +Xilinx ZynqMP PHY binding
> +
> +This binding describes a ZynqMP PHY device that is used to control ZynqMP
> +High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides four lanes
> +and are used by USB, SATA, PCIE, Display port and Ethernet SGMMI controllers.
> +
> +Required properties (controller (parent) node):
> +- compatible    : Should be "xlnx,zynqmp-psgtr"
> +
> +- reg		: Address and length of register sets for each device in
> +		  "reg-names"
> +- reg-names     : The names of the register addresses corresponding to the
> +		  registers filled in "reg":
> +			- serdes: SERDES block register set
> +			- siou: SIOU block register set
> +			- lpd: Low power domain peripherals reset control
> +			- fpd: Full power domain peripherals reset control

The reset registers should not be directly modified by Linux. Any access
to resets is likely requiring a reset controller that uses platform FW
to modify the resets.
> +
> +-xlnx,tx_termination_fix: Include fix for a functional issue in the GT. The TX
> +			  termination resistance can be out of spec due to a
> +			  bug in the calibration logic. This issue will be fixed
> +			  in silicon in future versions.

The silicon version is run-time detectable. There should be a way to get
away without this property.

	Sören

Re: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.

[Rob Herring]

On Wed, Jan 13, 2016 at 07:43:24PM +0530, Subbaraya Sundeep Bhatta wrote:
> This patch adds the document describing dt bindings for ZynqMP
> PHY. ZynqMP SOC has a High Speed Processing System Gigabit
> Transceiver which provides PHY capabilties to USB, SATA,
> PCIE, Display Port and Ehernet SGMII controllers.
> 
> Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> ---
>  v2:
> 	modified to use phy cells as 2.
> 
>  .../devicetree/bindings/phy/phy-zynqmp.txt         | 103 +++++++++++++++++++++
>  1 file changed, 103 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> new file mode 100644
> index 0000000..975cf21
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> @@ -0,0 +1,103 @@
> +Xilinx ZynqMP PHY binding
> +
> +This binding describes a ZynqMP PHY device that is used to control ZynqMP
> +High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides four lanes
> +and are used by USB, SATA, PCIE, Display port and Ethernet SGMMI controllers.

s/SGMMI/SGMII/ 

> +
> +Required properties (controller (parent) node):
> +- compatible    : Should be "xlnx,zynqmp-psgtr"
> +
> +- reg		: Address and length of register sets for each device in
> +		  "reg-names"
> +- reg-names     : The names of the register addresses corresponding to the
> +		  registers filled in "reg":
> +			- serdes: SERDES block register set
> +			- siou: SIOU block register set
> +			- lpd: Low power domain peripherals reset control
> +			- fpd: Full power domain peripherals reset control
> +
> +-xlnx,tx_termination_fix: Include fix for a functional issue in the GT. The TX
> +			  termination resistance can be out of spec due to a
> +			  bug in the calibration logic. This issue will be fixed
> +			  in silicon in future versions.
> +
> +Required nodes	:  A sub-node is required for each lane the controller
> +		   provides.
> +
> +Required properties (port (child) nodes):
> +lane0:
> +- #phy-cells	: Should be 2
> +		  Cell after port phandle is device type from:
> +			- <PHY_TYPE_PCIE 0>
> +			- <PHY_TYPE_SATA 0>
> +			- <PHY_TYPE_USB3 0>
> +			- <PHY_TYPE_DP 1>
> +			- <PHY_TYPE_SGMII 0>

What is the 2nd cell for? The phandle doesn't count for the size.

However, I would simplify this to get rid of the sub nodes and set lane 
in the 1st cell and the type in the 2nd cell.

Rob
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RE: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.

[Subbaraya Sundeep Bhatta]

Hi Rob,

> -----Original Message-----
> From: Rob Herring [mailto:robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> Sent: Friday, January 15, 2016 7:40 AM
> To: Subbaraya Sundeep Bhatta
> Cc: kishon-l0cyMroinI0@public.gmane.org; balbi-l0cyMroinI0@public.gmane.org; gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org;
> devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Subbaraya Sundeep
> Bhatta
> Subject: Re: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.
> 
> On Wed, Jan 13, 2016 at 07:43:24PM +0530, Subbaraya Sundeep Bhatta wrote:
> > This patch adds the document describing dt bindings for ZynqMP PHY.
> > ZynqMP SOC has a High Speed Processing System Gigabit Transceiver
> > which provides PHY capabilties to USB, SATA, PCIE, Display Port and
> > Ehernet SGMII controllers.
> >
> > Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> > ---
> >  v2:
> > 	modified to use phy cells as 2.
> >
> >  .../devicetree/bindings/phy/phy-zynqmp.txt         | 103
> +++++++++++++++++++++
> >  1 file changed, 103 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> >
> > diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> > b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> > new file mode 100644
> > index 0000000..975cf21
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> > @@ -0,0 +1,103 @@
> > +Xilinx ZynqMP PHY binding
> > +
> > +This binding describes a ZynqMP PHY device that is used to control
> > +ZynqMP High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides
> > +four lanes and are used by USB, SATA, PCIE, Display port and Ethernet
> SGMMI controllers.
> 
> s/SGMMI/SGMII/

Yeah, I will change it.
> 
> > +
> > +Required properties (controller (parent) node):
> > +- compatible    : Should be "xlnx,zynqmp-psgtr"
> > +
> > +- reg		: Address and length of register sets for each device in
> > +		  "reg-names"
> > +- reg-names     : The names of the register addresses corresponding to the
> > +		  registers filled in "reg":
> > +			- serdes: SERDES block register set
> > +			- siou: SIOU block register set
> > +			- lpd: Low power domain peripherals reset control
> > +			- fpd: Full power domain peripherals reset control
> > +
> > +-xlnx,tx_termination_fix: Include fix for a functional issue in the GT. The TX
> > +			  termination resistance can be out of spec due to a
> > +			  bug in the calibration logic. This issue will be fixed
> > +			  in silicon in future versions.
> > +
> > +Required nodes	:  A sub-node is required for each lane the controller
> > +		   provides.
> > +
> > +Required properties (port (child) nodes):
> > +lane0:
> > +- #phy-cells	: Should be 2
> > +		  Cell after port phandle is device type from:
> > +			- <PHY_TYPE_PCIE 0>
> > +			- <PHY_TYPE_SATA 0>
> > +			- <PHY_TYPE_USB3 0>
> > +			- <PHY_TYPE_DP 1>
> > +			- <PHY_TYPE_SGMII 0>
> 
> What is the 2nd cell for? The phandle doesn't count for the size.

ZynMP SoC has 2 USB controllers, 1 SATA controller with 2 lanes,
1 PCIe controller with 4 lanes, 1 Display port with 2 lanes and
4 SGMII controllers. PHY provides 4 output lanes only for 14(PIPE) inputs 
(as mentioned above: 2 + 2 + 4 + 2+ 4 = 14). All the inputs are routed
to PHY output lanes with a Mux (Interconnect matrix). Only some combinations
are valid i.e, one cannot set mux to use USB1 on lane 0 as such. Here second
cell is input number.
 <PHY_TYPE_PCIE 0> derives to PCIe's lane 0 input in driver for which lane 0 of
PHY can be used.  The valid inputs of each PHY output lane are mentioned here.

> 
> However, I would simplify this to get rid of the sub nodes and set lane in the 1st
> cell and the type in the 2nd cell.

Sorry I did not get you on how to get rid of sub nodes. Could you please explain?

Thanks,
Sundeep
> 
> Rob
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RE: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.

[Subbaraya Sundeep Bhatta]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 3071 bytes --]

Hi Soren,

> -----Original Message-----
> From: Sören Brinkmann [mailto:soren.brinkmann@xilinx.com]
> Sent: Wednesday, January 13, 2016 9:01 PM
> To: Subbaraya Sundeep Bhatta
> Cc: kishon@ti.com; robh@kernel.org; balbi@ti.com;
> gregkh@linuxfoundation.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; Subbaraya Sundeep Bhatta
> Subject: Re: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.
> 
> On Wed, 2016-01-13 at 07:43PM +0530, Subbaraya Sundeep Bhatta wrote:
> > This patch adds the document describing dt bindings for ZynqMP PHY.
> > ZynqMP SOC has a High Speed Processing System Gigabit Transceiver
> > which provides PHY capabilties to USB, SATA, PCIE, Display Port and
> > Ehernet SGMII controllers.
> >
> > Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>
> 
> I missed the v2 hence again.
> 
> > ---
> >  v2:
> > 	modified to use phy cells as 2.
> >
> >  .../devicetree/bindings/phy/phy-zynqmp.txt         | 103
> +++++++++++++++++++++
> >  1 file changed, 103 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> >
> > diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> > b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> > new file mode 100644
> > index 0000000..975cf21
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> > @@ -0,0 +1,103 @@
> > +Xilinx ZynqMP PHY binding
> > +
> > +This binding describes a ZynqMP PHY device that is used to control
> > +ZynqMP High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides
> > +four lanes and are used by USB, SATA, PCIE, Display port and Ethernet
> SGMMI controllers.
> > +
> > +Required properties (controller (parent) node):
> > +- compatible    : Should be "xlnx,zynqmp-psgtr"
> > +
> > +- reg		: Address and length of register sets for each device in
> > +		  "reg-names"
> > +- reg-names     : The names of the register addresses corresponding to the
> > +		  registers filled in "reg":
> > +			- serdes: SERDES block register set
> > +			- siou: SIOU block register set
> > +			- lpd: Low power domain peripherals reset control
> > +			- fpd: Full power domain peripherals reset control
> 
> The reset registers should not be directly modified by Linux. Any access to
> resets is likely requiring a reset controller that uses platform FW to modify the
> resets.

Ok I will fix this and send next iteration.

> > +
> > +-xlnx,tx_termination_fix: Include fix for a functional issue in the GT. The TX
> > +			  termination resistance can be out of spec due to a
> > +			  bug in the calibration logic. This issue will be fixed
> > +			  in silicon in future versions.
> 
> The silicon version is run-time detectable. There should be a way to get away
> without this property.

Ok I will fix this and send next iteration.

Thanks,
Sundeep.
> 
> 	Sören
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