From mboxrd@z Thu Jan  1 00:00:00 1970
From: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
Subject: Re: [PATCH v2 05/26] clk: sunxi: Add display and TCON0
 clocks driver
Date: Sat, 16 Jan 2016 16:08:01 +0200
Message-ID: <1452953281.12419.2.camel@plaes.org>
References: <1452785109-6172-1-git-send-email-maxime.ripard@free-electrons.com>
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List-Id: devicetree@vger.kernel.org

On Thu, 2016-01-14 at 16:24 +0100, Maxime Ripard wrote:
> The A10 SoCs and its relatives has a special clock controller to drive th=
e
> display engines (both frontend and backend), that have a lot in common wi=
th
> the clock to drive the first TCON channel.
>=20
> Add a driver to support both.

...

> +static void __init sun4i_a10_display_init(struct device_node *node,
> +					=C2=A0=C2=A0struct sun4i_a10_display_clk_data *data)
> +{
> +	const char *parents[data->parents];
> +	const char *clk_name =3D node->name;
> +	struct reset_data *reset_data;
> +	struct clk_divider *div =3D NULL;
> +	struct clk_gate *gate;
> +	struct clk_mux *mux;
> +	void __iomem *reg;
> +	struct clk *clk;
> +	int i;

warning: unused variable 'i'

> +
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
> +	reg =3D of_io_request_and_map(node, 0, of_node_full_name(node));
> +	if (IS_ERR(reg)) {
> +		pr_err("%s: Could not map the clock registers\n", clk_name);
> +		return;
> +	}

...

Thanks for working on this feature ;)

P=C3=A4ikest,
Priit Laes

--=20
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