From: "jianqun.xu" <jay.xu@rock-chips.com>
To: heiko@sntech.de, robh+dt@kernel.org, pawel.moll@arm.com,
mark.rutland@arm.com, ijc+devicetree@hellion.org.uk,
galak@codeaurora.org, jwerner@chromium.org, broonie@kernel.org,
catalin.marinas@arm.com, will.deacon@arm.com,
sboyd@codeaurora.org, linus.walleij@linaro.org,
sjoerd.simons@collabora.co.uk
Cc: huangtao@rock-chips.com, jay.xu@rock-chips.com,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
Xing Zheng <zhengxing@rock-chips.com>
Subject: [PATCH v2 3/4] dt-bindings: add documentation of rk3399 clock controller
Date: Thu, 18 Feb 2016 10:36:22 +0800 [thread overview]
Message-ID: <1455762983-29980-4-git-send-email-jay.xu@rock-chips.com> (raw)
In-Reply-To: <1455762983-29980-1-git-send-email-jay.xu@rock-chips.com>
From: Xing Zheng <zhengxing@rock-chips.com>
Add the devicetree binding for the cru on the rk3399 which quite
similar structured as previous clock controllers.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
changes in v2:
- none
.../bindings/clock/rockchip,rk3399-cru.txt | 82 ++++++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
new file mode 100644
index 0000000..07bcc6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -0,0 +1,82 @@
+* Rockchip RK3399 Clock and Reset Unit
+
+The RK3399 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
+- compatible: CRU should be "rockchip,rk3399-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_isp" - external ISP clock - optional,
+ - "ext_jtag" - external JTAG clock - optional
+ - "ext_vip" - external VIP clock - optional,
+ - "usbotg_out" - output clock of the pll in the otg phy
+
+Example: General Register Files
+
+ pmugrf: syscon@ff320000 {
+ compatible = "rockchip,rk3399-pmugrf", "syscon";
+ reg = <0x0 0xff320000 0x0 0x1000>;
+ };
+
+ grf: syscon@ff770000 {
+ compatible = "rockchip,rk3399-grf", "syscon";
+ reg = <0x0 0xff770000 0x0 0x10000>;
+ };
+
+Example: Clock controller node:
+
+ pmucru: pmu-clock-controller@ff750000 {
+ compatible = "rockchip,rk3399-pmucru";
+ reg = <0x0 0xff750000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@ff760000 {
+ compatible = "rockchip,rk3399-cru";
+ reg = <0x0 0xff760000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart0: serial@ff1a0000 {
+ compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff180000 0x0 0x100>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
--
1.9.1
next prev parent reply other threads:[~2016-02-18 2:36 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-18 2:36 [PATCH v2 0/4] Add core dtsi for rk3399 from Rockchip jianqun.xu
2016-02-18 2:36 ` [PATCH v2 1/4] clk: rockchip: add dt-binding header for rk3399 jianqun.xu
[not found] ` <1455762983-29980-1-git-send-email-jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-02-18 2:36 ` [PATCH v2 2/4] spi: rockchip: add bindings for rk3399 spi jianqun.xu
[not found] ` <1455762983-29980-3-git-send-email-jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-02-18 9:41 ` Mark Brown
[not found] ` <20160218094108.GA7129-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2016-02-18 9:47 ` [PATCH v2.1 " Heiko Stuebner
2016-02-18 9:57 ` Jianqun Xu
[not found] ` <56C5959D.3030806-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-02-18 13:57 ` Mark Brown
[not found] ` <20160218135751.GE7129-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2016-02-19 2:44 ` Jianqun Xu
2016-02-18 2:36 ` jianqun.xu [this message]
2016-02-18 2:36 ` [PATCH v2 4/4] ARM64: dts: rockchip: add core dtsi file for rk3399 jianqun.xu
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