From: "jianqun.xu" <jay.xu@rock-chips.com>
To: heiko@sntech.de, robh+dt@kernel.org, pawel.moll@arm.com,
mark.rutland@arm.com, ijc+devicetree@hellion.org.uk,
galak@codeaurora.org, jwerner@chromium.org, broonie@kernel.org,
catalin.marinas@arm.com, will.deacon@arm.com,
sboyd@codeaurora.org, linus.walleij@linaro.org,
sjoerd.simons@collabora.co.uk
Cc: huangtao@rock-chips.com, jay.xu@rock-chips.com,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: [PATCH v4 2/6] soc: rockchip: add bindings for Rockchip grf
Date: Fri, 19 Feb 2016 09:56:14 +0800 [thread overview]
Message-ID: <1455846978-4272-3-git-send-email-jay.xu@rock-chips.com> (raw)
In-Reply-To: <1455846978-4272-1-git-send-email-jay.xu@rock-chips.com>
From: Jianqun Xu <jay.xu@rock-chips.com>
Add devicetree bindings for Rockchip grf which found on
Rockchip SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
changes in v4:
- new add
.../devicetree/bindings/soc/rockchip/grf.txt | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/rockchip/grf.txt
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
new file mode 100644
index 0000000..7fb0410
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
@@ -0,0 +1,35 @@
+* Rockchip General Register Files (GRF)
+
+The general register file will be used to do static set by software, which
+is composed of many registers for system control.
+
+From RK3368 SoCs, the GRF is divided into two sections,
+- GRF, used for general non-secure system,
+- PMUGRF, used for always on sysyem
+
+Required Properties:
+
+- compatible: GRF should be one of the followings
+ - "rockchip,rk3066-grf", "syscon": for rk3066
+ - "rockchip,rk3188-grf", "syscon": for rk3188
+ - "rockchip,rk3228-grf", "syscon": for rk3228
+ - "rockchip,rk3288-grf", "syscon": for rk3288
+ - "rockchip,rk3368-grf", "syscon": for rk3368
+ - "rockchip,rk3399-grf", "syscon": for rk3399
+- compatible: PMUGRF should be one of the followings
+ - "rockchip,rk3368-pmugrf", "syscon": for rk3368
+ - "rockchip,rk3399-pmugrf", "syscon": for rk3399
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+Example: GRF and PMUGRF of RK3399 SoCs
+
+ pmugrf: syscon@ff320000 {
+ compatible = "rockchip,rk3399-pmugrf", "syscon";
+ reg = <0x0 0xff320000 0x0 0x1000>;
+ };
+
+ grf: syscon@ff770000 {
+ compatible = "rockchip,rk3399-grf", "syscon";
+ reg = <0x0 0xff770000 0x0 0x10000>;
+ };
--
1.9.1
next prev parent reply other threads:[~2016-02-19 1:56 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-19 1:56 [PATCH v4 0/6] Add core dtsi for rk3399 from Rockchip jianqun.xu
2016-02-19 1:56 ` [PATCH v4 1/6] clk: rockchip: add dt-binding header for rk3399 jianqun.xu
2016-02-19 1:56 ` jianqun.xu [this message]
2016-02-19 1:56 ` [PATCH v4 3/6] spi: rockchip: add bindings for rk3399 spi jianqun.xu
[not found] ` <1455846978-4272-4-git-send-email-jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-02-19 6:31 ` Heiko Stuebner
2016-02-19 6:38 ` Jianqun Xu
2016-02-19 1:56 ` [PATCH v4 4/6] ASoC: rockchip: add bindings for rk3399 i2s jianqun.xu
[not found] ` <1455846978-4272-1-git-send-email-jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-02-19 1:59 ` [PATCH v4 5/6] dt-bindings: add documentation of rk3399 clock controller jianqun.xu
[not found] ` <1455847186-4423-1-git-send-email-jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-02-23 20:27 ` Rob Herring
2016-02-19 2:03 ` [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 jianqun.xu
2016-02-19 2:05 ` [PATCH v4 " jianqun.xu
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