* [PATCH] arm64: dts: Add L2 cache topology to Hi6220
@ 2016-02-26 5:28 Leo Yan
[not found] ` <1456464514-24380-1-git-send-email-leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Leo Yan @ 2016-02-26 5:28 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell,
Kumar Gala, Catalin Marinas, Will Deacon
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Leo Yan
This patch adds the L2 cache topology on Hi6220. Hi6220 has two
clusters, every cluster has 512KiB L2 cache (32KiB x 16 ways).
Signed-off-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index d8b963c..1746d50 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -82,6 +82,7 @@
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cooling-min-level = <4>;
@@ -96,6 +97,7 @@
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
@@ -105,6 +107,7 @@
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
@@ -114,6 +117,7 @@
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
@@ -123,6 +127,7 @@
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
@@ -132,6 +137,7 @@
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
@@ -141,6 +147,7 @@
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
@@ -150,9 +157,18 @@
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
+
+ CLUSTER0_L2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ CLUSTER1_L2: l2-cache1 {
+ compatible = "cache";
+ };
};
cpu_opp_table: cpu_opp_table {
--
1.9.1
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] arm64: dts: Add L2 cache topology to Hi6220
[not found] ` <1456464514-24380-1-git-send-email-leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
@ 2016-04-15 16:19 ` Wei Xu
0 siblings, 0 replies; 2+ messages in thread
From: Wei Xu @ 2016-04-15 16:19 UTC (permalink / raw)
To: Leo Yan, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell,
Kumar Gala, Catalin Marinas, Will Deacon
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Hi Leo,
On 26/02/2016 05:28, Leo Yan wrote:
> This patch adds the L2 cache topology on Hi6220. Hi6220 has two
> clusters, every cluster has 512KiB L2 cache (32KiB x 16 ways).
>
> Signed-off-by: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
Applied.
Thanks!
Best Regards,
Wei
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> index d8b963c..1746d50 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> @@ -82,6 +82,7 @@
> device_type = "cpu";
> reg = <0x0 0x0>;
> enable-method = "psci";
> + next-level-cache = <&CLUSTER0_L2>;
> clocks = <&stub_clock 0>;
> operating-points-v2 = <&cpu_opp_table>;
> cooling-min-level = <4>;
> @@ -96,6 +97,7 @@
> device_type = "cpu";
> reg = <0x0 0x1>;
> enable-method = "psci";
> + next-level-cache = <&CLUSTER0_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> };
> @@ -105,6 +107,7 @@
> device_type = "cpu";
> reg = <0x0 0x2>;
> enable-method = "psci";
> + next-level-cache = <&CLUSTER0_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> };
> @@ -114,6 +117,7 @@
> device_type = "cpu";
> reg = <0x0 0x3>;
> enable-method = "psci";
> + next-level-cache = <&CLUSTER0_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> };
> @@ -123,6 +127,7 @@
> device_type = "cpu";
> reg = <0x0 0x100>;
> enable-method = "psci";
> + next-level-cache = <&CLUSTER1_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> };
> @@ -132,6 +137,7 @@
> device_type = "cpu";
> reg = <0x0 0x101>;
> enable-method = "psci";
> + next-level-cache = <&CLUSTER1_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> };
> @@ -141,6 +147,7 @@
> device_type = "cpu";
> reg = <0x0 0x102>;
> enable-method = "psci";
> + next-level-cache = <&CLUSTER1_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> };
> @@ -150,9 +157,18 @@
> device_type = "cpu";
> reg = <0x0 0x103>;
> enable-method = "psci";
> + next-level-cache = <&CLUSTER1_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> };
> +
> + CLUSTER0_L2: l2-cache0 {
> + compatible = "cache";
> + };
> +
> + CLUSTER1_L2: l2-cache1 {
> + compatible = "cache";
> + };
> };
>
> cpu_opp_table: cpu_opp_table {
>
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2016-02-26 5:28 [PATCH] arm64: dts: Add L2 cache topology to Hi6220 Leo Yan
[not found] ` <1456464514-24380-1-git-send-email-leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-04-15 16:19 ` Wei Xu
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