From: <tthayer@opensource.altera.com>
To: bp@alien8.de, dougthompson@xmission.com, m.chehab@samsung.com,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linux@arm.linux.org.uk, dinguyen@opensource.altera.com,
grant.likely@linaro.org
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, tthayer.linux@gmail.com,
tthayer@opensource.altera.com
Subject: [PATCH 5/5] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry
Date: Tue, 1 Mar 2016 10:38:21 -0600 [thread overview]
Message-ID: <1456850301-22066-5-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1456850301-22066-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index cce9e50..e83e973 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -599,6 +599,20 @@
reg = <0xffe00000 0x40000>;
};
+ eccmgr: eccmgr@ffd06090 {
+ compatible = "altr,socfpga-ecc-manager";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ l2-ecc@ffd06000 {
+ compatible = "altr,socfpga-a10-l2-ecc";
+ reg = <0xffd06010 0x4>;
+ interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
rst: rstmgr@ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
--
1.7.9.5
prev parent reply other threads:[~2016-03-01 16:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-01 16:38 [PATCH 1/5] EDAC: Altera L2 Kconfig change from select to depends upon tthayer
2016-03-01 16:38 ` [PATCH 2/5] Documentation: dt: socfpga: Add Altera Arri10 L2 cache binding tthayer
2016-03-05 4:26 ` Rob Herring
2016-03-01 16:38 ` [PATCH 3/5] EDAC, altera: Addition of Arria10 L2 Cache ECC tthayer
2016-03-04 10:38 ` Borislav Petkov
2016-03-04 15:42 ` Thor Thayer
2016-03-01 16:38 ` [PATCH 4/5] ARM: socfpga: Enable Arria10 L2 cache ECC on startup tthayer
[not found] ` <1456850301-22066-4-git-send-email-tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2016-03-05 6:36 ` Dinh Nguyen
2016-03-01 16:38 ` tthayer [this message]
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