[PATCH v3 00/11] dmaengine: bcm2835: bugfix + enhancement of driver

[PATCH v3 00/11] dmaengine: bcm2835: bugfix + enhancement of driver

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

This patchset fixes several issues:
* missing residue_granularity to allow better support for I2S
* dma-channels are no longer artificially restricted (channel 0 and 2)
* added correct support for dma-channels 11-14 (changeable via
  the device tree) by using the correct shared irq line with index
  11 into the interrupts list (changeable via device tree)

With this now 11 DMA channels are available instead of 7 - the
additional HW-DMA-channels are:
* 0, 2 (masking of channels)
* 13, 14 (shared interrupts - see also note on channel 12)

It also adds several new features:
* slave_sg support
* dma_memcopy support

For these a consolidated method for creating standard control-block
chains was created to share common between cyclic, slave_sg and
memcopy.

Testing:
* slave_sg
  * spi-bcm2835:
    * fb_st7735r framebuffer
      * tested using mplayer
* cyclic
  * bcm2835-i2s
    * Audio output with a Hifiberry I2S card.
      * tested using mplayer and aplay
* memcopy
  * dmatest

Tests using both slave_sg and cyclic concurrently were also conducted
using mplayer to play BigBuckBunny.

Note that the bcm2835-i2s driver still requires the clock patch-set
enabling the pcm clock.

The last patches (expose registers via debugfs) is optional:
  dmaengine: bcm2835: expose dma registers via debugfs

Note: DMA channel 15 is still not supported because:
* it sits in a separate IO range
* it is used by the firmware
So unless the firmware no longer uses DMA 15, it is not worth
the effort.

Possibly future improvements:
* allow control over channel selection (Lite or normal)
  as well as AXI priorities via the device-tree
* support for memset, memset_sg and interleave
* using DREQ-names instead of magic numbers (via include/dt-binding/...)

Change-log:
  V1 -> V2: * rewrite of the original patch avoiding code duplication
            * splitting of changes into multiple patches
  V2 -> V3: * allow configuration to dma mapping va device tree.
            * adding names binging for DREQs to get used in device-trees
	    * move lite channel detection (via debug register) and using
	      limits of it into separate patch
	    * add debugfs support to see what is actually happening in
	      the dma registers.
	    * incorporated feedback from various people improving
	      code-readability (primarily Patch 7)

Martin Sperl (11):
  dmaengine: bcm2835: set residue_granularity field
  dmaengine: bcm2835: remove unnecessary masking of dma channels
  dmaengine: bcm2835: use shared interrupt for channel 11 to 14.
  ARM: bcm2835: dt: add bindings for shared interrupt properties
  dmaengine: bcm2835: add additional defines for DMA-registers
  dmaengine: bcm2835: move cyclic member from bcm2835_chan into
    bcm2835_desc
  dmaengine: bcm2835: move controlblock chain generation into separate
    method
  dmaengine: bcm2835: limit max length based on channel type
  dmaengine: bcm2835: add slave_sg support to bcm2835-dma
  dmaengine: bcm2835: add dma_memcopy support to bcm2835-dma
  dmaengine: bcm2835: expose dma registers via debugfs

 .../devicetree/bindings/dma/brcm,bcm2835-dma.txt   |   6 +
 drivers/dma/bcm2835-dma.c                          | 740 +++++++++++++++++----
 2 files changed, 623 insertions(+), 123 deletions(-)

--
2.1.4
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[PATCH v3 01/11] dmaengine: bcm2835: set residue_granularity field

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

bcm2835-dma supports residue reporting at burst level but didn't report
this via the residue_granularity field.

See also:
https://github.com/raspberrypi/linux/commit/b015555327afa402f70ddc86e3632f59df1cd9d7
for the downstream patch.

Signed-off-by: Matthias Reichl <hias-vtPv7MOkFPkAvxtiuMwx3w@public.gmane.org>
Signed-off-by: Noralf Trønnes <noralf-L59+Z2yzLopAfugRpC6u6w@public.gmane.org>
Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
Reviewed-by: Eric Anholt <eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org>
---
 drivers/dma/bcm2835-dma.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index 996c4b0..2d72fe8 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -625,6 +625,7 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
 	od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 	od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 	od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+	od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
 	od->ddev.dev = &pdev->dev;
 	INIT_LIST_HEAD(&od->ddev.channels);
 	spin_lock_init(&od->lock);
-- 
2.1.4

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[PATCH v3 02/11] dmaengine: bcm2835: remove unnecessary masking of dma channels

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

The original patch contained 3 dma channels that were masked out.

These - as far as research and discussions show - are a
artefacts remaining from the downstream legacy dma-api.

Right now down-stream still includes a legacy api used only
in a single (downstream only) driver (bcm2708_fb) that requires
2D DMA for speedup (DMA-channel 0).
Formerly the sd-card support driver also was using this legacy
api (DMA-channel 2), but since has been moved over to use
dmaengine directly.

The DMA-channel 3 is already masked out in the devicetree in
the default property "brcm,dma-channel-mask = <0x7f35>;"

So we can remove the whole masking of DMA channels.

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
Reviewed-by: Eric Anholt <eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org>
---
 drivers/dma/bcm2835-dma.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index 2d72fe8..e4ca980 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -123,9 +123,6 @@ struct bcm2835_desc {
 #define BCM2835_DMA_DATA_TYPE_S32	4
 #define BCM2835_DMA_DATA_TYPE_S128	16
 
-#define BCM2835_DMA_BULK_MASK	BIT(0)
-#define BCM2835_DMA_FIQ_MASK	(BIT(2) | BIT(3))
-
 /* Valid only for channels 0 - 14, 15 has its own base address */
 #define BCM2835_DMA_CHAN(n)	((n) << 8) /* Base address */
 #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
@@ -641,12 +638,6 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
 		goto err_no_dma;
 	}
 
-	/*
-	 * Do not use the FIQ and BULK channels,
-	 * because they are used by the GPU.
-	 */
-	chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK);
-
 	for (i = 0; i < pdev->num_resources; i++) {
 		irq = platform_get_irq(pdev, i);
 		if (irq < 0)
-- 
2.1.4

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[PATCH v3 03/11] dmaengine: bcm2835: use shared interrupt for channel 11 to 14.

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

The bcm2835 dma channel 11 to 14 only have a single shared irq line,
so this patch implements shared interrupts for these channels.

This patch also introduces 2 new device-tree properties
(optional for compatibility with older device-trees):
* brcm,dma-channel-shared-mask - default: 0x0780
* brcm,dma-shared-irq-index    - default: 11

With this patch applied we now have 11 dma channels available to
the ARM side of the SOC.

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
Reviewed-by: Eric Anholt <eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org>
---
 drivers/dma/bcm2835-dma.c | 64 ++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 58 insertions(+), 6 deletions(-)

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index e4ca980..fe7d5a6 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -81,7 +81,9 @@ struct bcm2835_chan {
 	struct dma_pool *cb_pool;
 
 	void __iomem *chan_base;
+
 	int irq_number;
+	unsigned long irq_flags;
 };
 
 struct bcm2835_desc {
@@ -127,6 +129,20 @@ struct bcm2835_desc {
 #define BCM2835_DMA_CHAN(n)	((n) << 8) /* Base address */
 #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
 
+/*
+ * number of dma channels we support
+ * we do not support DMA channel 15, as it is in a separate IO range,
+ * does not have a separate IRQ line except for the "catch all IRQ line"
+ * finally this channel is used by the firmware so is not available
+ */
+#define BCM2835_DMA_MAX_CHANNEL_NUMBER	14
+
+/* the DMA channels 11 to 14 share a common interrupt */
+#define BCM2835_DMA_IRQ_SHARED_MASK_DEFAULT \
+	(BIT(11) | BIT(12) | BIT(13) | BIT(14))
+#define BCM2835_DMA_IRQ_SHARED_DEFAULT	11
+#define BCM2835_DMA_IRQ_ALL_DEFAULT	12
+
 static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
 {
 	return container_of(d, struct bcm2835_dmadev, ddev);
@@ -215,6 +231,15 @@ static irqreturn_t bcm2835_dma_callback(int irq, void *data)
 	struct bcm2835_desc *d;
 	unsigned long flags;
 
+	/* check the shared interrupt */
+	if (c->irq_flags & IRQF_SHARED) {
+		/* check if the interrupt is enabled */
+		flags = readl(c->chan_base + BCM2835_DMA_CS);
+		/* if not set then we are not the reason for the irq */
+		if (!(flags & BCM2835_DMA_INT))
+			return IRQ_NONE;
+	}
+
 	spin_lock_irqsave(&c->vc.lock, flags);
 
 	/* Acknowledge interrupt */
@@ -250,7 +275,8 @@ static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
 	}
 
 	return request_irq(c->irq_number,
-			bcm2835_dma_callback, 0, "DMA IRQ", c);
+			   bcm2835_dma_callback,
+			   c->irq_flags, "DMA IRQ", c);
 }
 
 static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
@@ -526,7 +552,8 @@ static int bcm2835_dma_terminate_all(struct dma_chan *chan)
 	return 0;
 }
 
-static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
+static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id,
+				 int irq, unsigned long irq_flags)
 {
 	struct bcm2835_chan *c;
 
@@ -541,6 +568,7 @@ static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
 	c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
 	c->ch = chan_id;
 	c->irq_number = irq;
+	c->irq_flags = irq_flags;
 
 	return 0;
 }
@@ -586,7 +614,8 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
 	int rc;
 	int i;
 	int irq;
-	uint32_t chans_available;
+	unsigned long irq_flags;
+	u32 chans_available, chans_shared_irq_mask, shared_irq_index;
 
 	if (!pdev->dev.dma_mask)
 		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
@@ -637,14 +666,37 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
 		rc = -EINVAL;
 		goto err_no_dma;
 	}
+	/* we do not support more channels */
+	chans_available &= BIT(BCM2835_DMA_MAX_CHANNEL_NUMBER + 1) - 1;
+
+	/* get shared irq mask falling back to defaults */
+	chans_shared_irq_mask = BCM2835_DMA_IRQ_SHARED_MASK_DEFAULT;
+	of_property_read_u32(pdev->dev.of_node,
+			     "brcm,dma-channel-shared-mask",
+			     &chans_shared_irq_mask);
+
+	/* get shared irq index falling back to default */
+	shared_irq_index = BCM2835_DMA_IRQ_SHARED_DEFAULT;
+	of_property_read_u32(pdev->dev.of_node,
+			     "brcm,dma-shared-irq-index",
+			     &shared_irq_index);
+
+	/* loop over all channels */
+	for (i = 0; i <= fls(chans_available); i++) {
+		if (chans_shared_irq_mask & BIT(i)) {
+			irq = platform_get_irq(pdev,
+					       shared_irq_index);
+			irq_flags = IRQF_SHARED;
+		} else {
+			irq = platform_get_irq(pdev, i);
+			irq_flags = 0;
+		}
 
-	for (i = 0; i < pdev->num_resources; i++) {
-		irq = platform_get_irq(pdev, i);
 		if (irq < 0)
 			break;
 
 		if (chans_available & (1 << i)) {
-			rc = bcm2835_dma_chan_init(od, i, irq);
+			rc = bcm2835_dma_chan_init(od, i, irq, irq_flags);
 			if (rc)
 				goto err_no_dma;
 		}
-- 
2.1.4

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[PATCH v3 04/11] ARM: bcm2835: dt: add bindings for shared interrupt properties

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Add binding documentation for the new shared interrupt properties:
* brcm,dma-channel-shared-mask
* brcm,dma-shared-irq-index

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
---
 Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
index 1396078..f9e84ee 100644
--- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
+++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
@@ -17,6 +17,10 @@ Required properties:
 - brcm,dma-channel-mask: Bit mask representing the channels
 			 not used by the firmware in ascending order,
 			 i.e. first channel corresponds to LSB.
+- brcm,dma-channel-shared-mask: Bit mask representing the channels
+				that use a shared interrupt
+- brcm,dma-shared-irq-index: index of which of the interrupts mentioned
+			     above is the shared interrupt
 
 Example:
 
@@ -39,6 +43,8 @@ dma: dma@7e007000 {
 
 	#dma-cells = <1>;
 	brcm,dma-channel-mask = <0x7f35>;
+	brcm,dma-channel-shared-mask = <0x0780>;
+	brcm,dma-shared-irq-index = <11>;
 };
 
 DMA clients connected to the BCM2835 DMA controller must use the format
-- 
2.1.4

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Re: [PATCH v3 04/11] ARM: bcm2835: dt: add bindings for shared interrupt properties

[Eric Anholt]

[-- Attachment #1: Type: text/plain, Size: 1586 bytes --]

kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org writes:

> From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
>
> Add binding documentation for the new shared interrupt properties:
> * brcm,dma-channel-shared-mask
> * brcm,dma-shared-irq-index
>
> Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
> index 1396078..f9e84ee 100644
> --- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
> +++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
> @@ -17,6 +17,10 @@ Required properties:
>  - brcm,dma-channel-mask: Bit mask representing the channels
>  			 not used by the firmware in ascending order,
>  			 i.e. first channel corresponds to LSB.
> +- brcm,dma-channel-shared-mask: Bit mask representing the channels
> +				that use a shared interrupt
> +- brcm,dma-shared-irq-index: index of which of the interrupts mentioned
> +			     above is the shared interrupt

This should be under "Optional properties" since there are appropriate
defaults for the only compatible string listed.

I still don't think exposing this in the DT is necessary (it's hardware
block internals), but I'm not writing the code so I'm fine with it
either way, really.  Regardless, it would be really good to get the
slave_sg part of the series in, which is really important for the
platform.

[-- Attachment #2: signature.asc --]
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Re: [PATCH v3 04/11] ARM: bcm2835: dt: add bindings for shared interrupt properties

[Martin Sperl]

> On 08.03.2016, at 00:24, Eric Anholt <eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org> wrote:
> 
> kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org writes:
> 
>> From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
>> 
>> Add binding documentation for the new shared interrupt properties:
>> * brcm,dma-channel-shared-mask
>> * brcm,dma-shared-irq-index
>> 
>> Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
>> ---
>> Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt | 6 ++++++
>> 1 file changed, 6 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
>> index 1396078..f9e84ee 100644
>> --- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
>> +++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
>> @@ -17,6 +17,10 @@ Required properties:
>> - brcm,dma-channel-mask: Bit mask representing the channels
>> 			 not used by the firmware in ascending order,
>> 			 i.e. first channel corresponds to LSB.
>> +- brcm,dma-channel-shared-mask: Bit mask representing the channels
>> +				that use a shared interrupt
>> +- brcm,dma-shared-irq-index: index of which of the interrupts mentioned
>> +			     above is the shared interrupt
> 
> This should be under "Optional properties" since there are appropriate
> defaults for the only compatible string listed.

Well - IMO it is actually required and the defaults are only for backwards
compatibility with older device-trees, but that is easy to change…
> 
> I still don't think exposing this in the DT is necessary (it's hardware
> block internals), but I'm not writing the code so I'm fine with it
Actually this was a request by Vinod to make this configurable via the
device-tree.

> either way, really.  Regardless, it would be really good to get the
> slave_sg part of the series in, which is really important for the
> platform.
Yes, then we can bring the DMA implementations for mmc/sdhost forward.

Martin


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Re: [PATCH v3 04/11] ARM: bcm2835: dt: add bindings for shared interrupt properties

[Vinod Koul]

On Tue, Mar 08, 2016 at 12:23:51PM +0100, Martin Sperl wrote:
> 
> > On 08.03.2016, at 00:24, Eric Anholt <eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org> wrote:
> > 
> > kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org writes:
> > 
> >> From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
> >> 
> >> Add binding documentation for the new shared interrupt properties:
> >> * brcm,dma-channel-shared-mask
> >> * brcm,dma-shared-irq-index
> >> 
> >> Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
> >> ---
> >> Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt | 6 ++++++
> >> 1 file changed, 6 insertions(+)
> >> 
> >> diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
> >> index 1396078..f9e84ee 100644
> >> --- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
> >> +++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
> >> @@ -17,6 +17,10 @@ Required properties:
> >> - brcm,dma-channel-mask: Bit mask representing the channels
> >> 			 not used by the firmware in ascending order,
> >> 			 i.e. first channel corresponds to LSB.
> >> +- brcm,dma-channel-shared-mask: Bit mask representing the channels
> >> +				that use a shared interrupt
> >> +- brcm,dma-shared-irq-index: index of which of the interrupts mentioned
> >> +			     above is the shared interrupt
> > 
> > This should be under "Optional properties" since there are appropriate
> > defaults for the only compatible string listed.
> 
> Well - IMO it is actually required and the defaults are only for backwards
> compatibility with older device-trees, but that is easy to change…
> > 
> > I still don't think exposing this in the DT is necessary (it's hardware
> > block internals), but I'm not writing the code so I'm fine with it
> Actually this was a request by Vinod to make this configurable via the
> device-tree.

DT needs to provide the hardware details for driver to work across
generations. Driver needs to get information like this to make decisions and
not hard code and make driver not scale..

> 
> > either way, really.  Regardless, it would be really good to get the
> > slave_sg part of the series in, which is really important for the
> > platform.
> Yes, then we can bring the DMA implementations for mmc/sdhost forward.
> 
> Martin
> 
> 
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-- 
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Re: [PATCH v3 04/11] ARM: bcm2835: dt: add bindings for shared interrupt properties

[Mark Rutland]

Hi,

As a general note, please put DT bindings patches before any patches
implementing them, as per
Documentation/devicetree/bindings/submitting-patches.txt.

That makes it possible to review a series in-order.

On Sat, Mar 05, 2016 at 10:52:15AM +0000, kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org wrote:
> From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
> 
> Add binding documentation for the new shared interrupt properties:
> * brcm,dma-channel-shared-mask
> * brcm,dma-shared-irq-index
> 
> Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
> index 1396078..f9e84ee 100644
> --- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
> +++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
> @@ -17,6 +17,10 @@ Required properties:
>  - brcm,dma-channel-mask: Bit mask representing the channels
>  			 not used by the firmware in ascending order,
>  			 i.e. first channel corresponds to LSB.
> +- brcm,dma-channel-shared-mask: Bit mask representing the channels
> +				that use a shared interrupt

Generally we don't like masks in DT (though I see this is in keeping with
another property above). I won't push strongly here.

I take it that this is a fixed HW property rather than a software configuration
option?

> +- brcm,dma-shared-irq-index: index of which of the interrupts mentioned
> +			     above is the shared interrupt

What is the usual order of the interrupts? How are they expected to be parsed
if this is in the middle of the list, for example?

I think this needs a more thorough description.

Thanks,
Mark.
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Re: [PATCH v3 04/11] ARM: bcm2835: dt: add bindings for shared interrupt properties

[Martin Sperl]

> On 10.03.2016, at 09:57, Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> wrote:
> 
> Hi,
> 
> As a general note, please put DT bindings patches before any patches
> implementing them, as per
> Documentation/devicetree/bindings/submitting-patches.txt.
> 
> That makes it possible to review a series in-order.
> 
> On Sat, Mar 05, 2016 at 10:52:15AM +0000, kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org wrote:
>> From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
>> 
>> Add binding documentation for the new shared interrupt properties:
>> * brcm,dma-channel-shared-mask
>> * brcm,dma-shared-irq-index
>> 
>> Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
>> ---
>> Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt | 6 ++++++
>> 1 file changed, 6 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
>> index 1396078..f9e84ee 100644
>> --- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
>> +++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
>> @@ -17,6 +17,10 @@ Required properties:
>> - brcm,dma-channel-mask: Bit mask representing the channels
>> 			 not used by the firmware in ascending order,
>> 			 i.e. first channel corresponds to LSB.
>> +- brcm,dma-channel-shared-mask: Bit mask representing the channels
>> +				that use a shared interrupt
> 
> Generally we don't like masks in DT (though I see this is in keeping with
> another property above). I won't push strongly here.
> 
> I take it that this is a fixed HW property rather than a software configuration
> option?

This is fixed HW property - the mask/mapping was originally proposed
to be “hardcoded” inside the driver.

Maybe some background on the dma-channel-mask property:
it is changed during loading the dt by the firmware
to mask out the channels that the firmware is using.

> 
>> +- brcm,dma-shared-irq-index: index of which of the interrupts mentioned
>> +			     above is the shared interrupt
> 
> What is the usual order of the interrupts? How are they expected to be parsed
> if this is in the middle of the list, for example?
> 
> I think this needs a more thorough description.

The reason that it was done this way is mostly because of DT-backwards
compatibility the 11th irq is the shared interrupt -there were some
wrong assumptions by the original author on the interrupts
(i.e there is a dedicated interrupt per channel).

Just hardcoding it inside the driver was not what Vinod wanted - even
if the design stayed fixed for now 3 different chips:
bcm2835, bcm2836 and bcm2837

Alternative options that have been considered:
* there is unfortunately no “interrupt-names” property (like it exists for
  reg, dma), because then I would have preferred to used:
     interrupts = <...>, <...>, …;
     interrupt-name = “dma0”, “dma1”, ..., “dma10”, “dmashared”, “dmaall”;
  with something like this we could probably have avoided both properties
  and just added a legacy mapping
  This would require some changes to the irq framework (which I wanted
  to avoid)
* I could have also written a custom parser in the driver to allow:
     interrupt-shared = <&int X>;
   but I would guess something like this to be frowned upon...
* a total restructure of the DT to a more expressive format so that 
  each channel would need to be described separately (with the 
  corresponding custom dt parser).
  The big advantage here would be that we can define the reg and irq
  range for each channel separately.
  Could look something like:
     dma: dma@7e0070fe0 {
        reg = <0x7e0070fe0 0x20>;
        compatible = "brcm,bcm2835-dma”;
        interrupts = <irq-shared> <irq-all>;
        dma0: dma@7e007000 {
	  reg = <0x7e007000 0x24>;
          interrupts = <irq-dma0>;
        };
        dma1: dma@7e007100 {
	  reg = <0x7e007100 0x24>;
          interrupts = <irq-dma1>;
        };
   	...
        dma10: dma@7e007a00 {
	  reg = <0x7e007a00 0x24>;
          interrupts = <irq-dma10>;
        };
        /* channel with shared interrupts */
        dma11: dma@7e007b00 {
	  reg = <0x7e007b00 0x24>;
	  /* no irq - use shared */
        };
        dma14: dma@7e007b00 {
	  reg = <0x7e007b00 0x24>;
	  /* no irq - use shared */
        };
	/*
         * dma channel 15 is a different type:
	 * only triggers irq-all (with all its problems)
         * is in a different memory location
         */
	dma15: dma@7ee05000 {
	  reg = <0x7ee05000 0x24>;
	  /* potentially mark the use of the “all” irq */
        };
     };
  It would make the device tree a lot longer (at least 60 lines) for
  minimal gains.
  In addition it is a lot of effort for something that has been fixed
  for 3 chip designs (bcm2835, bcm2836 and bcm2837)

  Something like this has been proposed as an option end of
  January, but there was never a feedback if something like
  this was preferred.

Please give guidance on the preferred solution.

We really would like to get the slave-dma feature into the kernel
so that we can start using it with the mmc/sdhost implementation.

Thanks,
	Martin

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Re: [PATCH v3 04/11] ARM: bcm2835: dt: add bindings for shared interrupt properties

[Martin Sperl]

Hi Mark!

On 11.03.2016 09:51, Martin Sperl wrote:
>> On 10.03.2016, at 09:57, Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> wrote:
>>
>> Alternative options that have been considered:
>> * there is unfortunately no “interrupt-names” property (like it exists for
>>    reg, dma), because then I would have preferred to used:
>>       interrupts = <...>, <...>, …;
>>       interrupt-name = “dma0”, “dma1”, ..., “dma10”, “dmashared”, “dmaall”;
>>    with something like this we could probably have avoided both properties
>>    and just added a legacy mapping
>>    This would require some changes to the irq framework (which I wanted
>>    to avoid)

I have posted a patch based on this approach (after having found out 
that it is possible
with the current framework using platform_get_irq_byname).

Rob Herring has "Acked" the documentation patch:
   [PATCH 1/3] dt/bindings: bcm2835: add interrupt-names property

Is this approach acceptable for you as well, so that we can try to get 
it merged?

Thanks, Martin






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Re: [PATCH v3 04/11] ARM: bcm2835: dt: add bindings for shared interrupt properties

[Mark Rutland]

On Tue, Mar 22, 2016 at 10:23:45AM +0100, Martin Sperl wrote:
> Hi Mark!

Hi Martin,

Apologies for having gone silent on this.

> On 11.03.2016 09:51, Martin Sperl wrote:
> >>On 10.03.2016, at 09:57, Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> wrote:
> >>
> >>Alternative options that have been considered:
> >>* there is unfortunately no “interrupt-names” property (like it exists for
> >>   reg, dma), because then I would have preferred to used:
> >>      interrupts = <...>, <...>, …;
> >>      interrupt-name = “dma0”, “dma1”, ..., “dma10”, “dmashared”, “dmaall”;
> >>   with something like this we could probably have avoided both properties
> >>   and just added a legacy mapping
> >>   This would require some changes to the irq framework (which I wanted
> >>   to avoid)
> 
> I have posted a patch based on this approach (after having found out
> that it is possible
> with the current framework using platform_get_irq_byname).
> 
> Rob Herring has "Acked" the documentation patch:
>   [PATCH 1/3] dt/bindings: bcm2835: add interrupt-names property
> 
> Is this approach acceptable for you as well, so that we can try to
> get it merged?

That approach looks good to me too.

One minor nit: please explicitly describe the "dma-shared-all"
interrupt-name in the description of interrupt-names.

Otherwise, for the binding and the code (which I retains support for
existing DTs):

Acked-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>

Thanks,
Mark.
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[PATCH v3 05/11] dmaengine: bcm2835: add additional defines for DMA-registers

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Add additional defines describing the DMA registers
as well as adding some more documentation to those registers.

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
Reviewed-by: Eric Anholt <eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org>
---
 drivers/dma/bcm2835-dma.c | 57 ++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 49 insertions(+), 8 deletions(-)

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index fe7d5a6..2cdc256 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -99,26 +99,67 @@ struct bcm2835_desc {
 
 #define BCM2835_DMA_CS		0x00
 #define BCM2835_DMA_ADDR	0x04
+#define BCM2835_DMA_TI		0x08
 #define BCM2835_DMA_SOURCE_AD	0x0c
 #define BCM2835_DMA_DEST_AD	0x10
-#define BCM2835_DMA_NEXTCB	0x1C
+#define BCM2835_DMA_LEN		0x14
+#define BCM2835_DMA_STRIDE	0x18
+#define BCM2835_DMA_NEXTCB	0x1c
+#define BCM2835_DMA_DEBUG	0x20
 
 /* DMA CS Control and Status bits */
-#define BCM2835_DMA_ACTIVE	BIT(0)
-#define BCM2835_DMA_INT	BIT(2)
+#define BCM2835_DMA_ACTIVE	BIT(0)  /* activate the DMA */
+#define BCM2835_DMA_END		BIT(1)  /* current CB has ended */
+#define BCM2835_DMA_INT		BIT(2)  /* interrupt status */
+#define BCM2835_DMA_DREQ	BIT(3)  /* DREQ state */
 #define BCM2835_DMA_ISPAUSED	BIT(4)  /* Pause requested or not active */
 #define BCM2835_DMA_ISHELD	BIT(5)  /* Is held by DREQ flow control */
-#define BCM2835_DMA_ERR	BIT(8)
+#define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last
+					       * AXI-write to ack
+					       */
+#define BCM2835_DMA_ERR		BIT(8)
+#define BCM2835_DMA_PRIORITY(x) ((x & 15) << 16) /* AXI priority */
+#define BCM2835_DMA_PANIC_PRIORITY(x) ((x & 15) << 20) /* panic priority */
+/* current value of TI.BCM2835_DMA_WAIT_RESP */
+#define BCM2835_DMA_WAIT_FOR_WRITES BIT(28)
+#define BCM2835_DMA_DIS_DEBUG	BIT(29) /* disable debug pause signal */
 #define BCM2835_DMA_ABORT	BIT(30) /* Stop current CB, go to next, WO */
 #define BCM2835_DMA_RESET	BIT(31) /* WO, self clearing */
 
+/* Transfer information bits - also bcm2835_cb.info field */
 #define BCM2835_DMA_INT_EN	BIT(0)
+#define BCM2835_DMA_TDMODE	BIT(1) /* 2D-Mode */
+#define BCM2835_DMA_WAIT_RESP	BIT(3) /* wait for AXI-write to be acked */
 #define BCM2835_DMA_D_INC	BIT(4)
-#define BCM2835_DMA_D_DREQ	BIT(6)
+#define BCM2835_DMA_D_WIDTH	BIT(5) /* 128bit writes if set */
+#define BCM2835_DMA_D_DREQ	BIT(6) /* enable DREQ for destination */
+#define BCM2835_DMA_D_IGNORE	BIT(7) /* ignore destination writes */
 #define BCM2835_DMA_S_INC	BIT(8)
-#define BCM2835_DMA_S_DREQ	BIT(10)
-
-#define BCM2835_DMA_PER_MAP(x)	((x) << 16)
+#define BCM2835_DMA_S_WIDTH	BIT(9) /* 128bit writes if set */
+#define BCM2835_DMA_S_DREQ	BIT(10) /* enable SREQ for source */
+#define BCM2835_DMA_S_IGNORE	BIT(11) /* ignore source reads - read 0 */
+#define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12)
+#define BCM2835_DMA_PER_MAP(x)	((x & 31) << 16) /* REQ source */
+#define BCM2835_DMA_WAIT(x)	((x & 31) << 21) /* add DMA-wait cycles */
+#define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */
+
+/* debug register bits */
+#define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR	BIT(0)
+#define BCM2835_DMA_DEBUG_FIFO_ERR		BIT(1)
+#define BCM2835_DMA_DEBUG_READ_ERR		BIT(2)
+#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT 4
+#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS 4
+#define BCM2835_DMA_DEBUG_ID_SHIFT		16
+#define BCM2835_DMA_DEBUG_ID_BITS		9
+#define BCM2835_DMA_DEBUG_STATE_SHIFT		16
+#define BCM2835_DMA_DEBUG_STATE_BITS		9
+#define BCM2835_DMA_DEBUG_VERSION_SHIFT		25
+#define BCM2835_DMA_DEBUG_VERSION_BITS		3
+#define BCM2835_DMA_DEBUG_LITE			BIT(28)
+
+/* shared registers for all dma channels */
+#define BCM2835_DMA_INT_STATUS         0xfe0
+#define BCM2835_DMA_ENABLE             0xff0
 
 #define BCM2835_DMA_DATA_TYPE_S8	1
 #define BCM2835_DMA_DATA_TYPE_S16	2
-- 
2.1.4

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[PATCH v3 06/11] dmaengine: bcm2835: move cyclic member from bcm2835_chan into bcm2835_desc

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

In preparation to consolidating code we move the cyclic member
into the bcm_2835_desc structure.

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
Reviewed-by: Eric Anholt <eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org>
---
 drivers/dma/bcm2835-dma.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index 2cdc256..23b01c5 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -73,7 +73,6 @@ struct bcm2835_chan {
 	struct list_head node;
 
 	struct dma_slave_config	cfg;
-	bool cyclic;
 	unsigned int dreq;
 
 	int ch;
@@ -95,6 +94,8 @@ struct bcm2835_desc {
 
 	unsigned int frames;
 	size_t size;
+
+	bool cyclic;
 };
 
 #define BCM2835_DMA_CS		0x00
@@ -403,8 +404,6 @@ static void bcm2835_dma_issue_pending(struct dma_chan *chan)
 	struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
 	unsigned long flags;
 
-	c->cyclic = true; /* Nothing else is implemented */
-
 	spin_lock_irqsave(&c->vc.lock, flags);
 	if (vchan_issue_pending(&c->vc) && !c->desc)
 		bcm2835_dma_start_desc(c);
@@ -458,6 +457,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
 	d->c = c;
 	d->dir = direction;
 	d->frames = buf_len / period_len;
+	d->cyclic = true;
 
 	d->cb_list = kcalloc(d->frames, sizeof(*d->cb_list), GFP_KERNEL);
 	if (!d->cb_list) {
-- 
2.1.4

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[PATCH v3 07/11] dmaengine: bcm2835: move controlblock chain generation into separate method

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

In preparation of adding slave_sg functionality this patch moves the
generation/allocation of bcm2835_desc and the building of
the corresponding DMA-control-block chain from bcm2835_dma_prep_dma_cyclic
into the newly created method bcm2835_dma_create_cb_chain.

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
---
 drivers/dma/bcm2835-dma.c | 294 +++++++++++++++++++++++++++++++---------------
 1 file changed, 198 insertions(+), 96 deletions(-)

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index 23b01c5..1ae53b8 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -90,12 +90,12 @@ struct bcm2835_desc {
 	struct virt_dma_desc vd;
 	enum dma_transfer_direction dir;
 
-	struct bcm2835_cb_entry *cb_list;
-
 	unsigned int frames;
 	size_t size;
 
 	bool cyclic;
+
+	struct bcm2835_cb_entry cb_list[];
 };
 
 #define BCM2835_DMA_CS		0x00
@@ -185,6 +185,13 @@ struct bcm2835_desc {
 #define BCM2835_DMA_IRQ_SHARED_DEFAULT	11
 #define BCM2835_DMA_IRQ_ALL_DEFAULT	12
 
+/* how many frames of max_len size do we need to transfer len bytes */
+static inline size_t bcm2835_dma_frames_for_length(size_t len,
+						   size_t max_len)
+{
+	return DIV_ROUND_UP(len, max_len);
+}
+
 static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
 {
 	return container_of(d, struct bcm2835_dmadev, ddev);
@@ -201,19 +208,161 @@ static inline struct bcm2835_desc *to_bcm2835_dma_desc(
 	return container_of(t, struct bcm2835_desc, vd.tx);
 }
 
-static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
+static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc)
 {
-	struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
-	int i;
+	size_t i;
 
 	for (i = 0; i < desc->frames; i++)
 		dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb,
 			      desc->cb_list[i].paddr);
 
-	kfree(desc->cb_list);
 	kfree(desc);
 }
 
+static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
+{
+	bcm2835_dma_free_cb_chain(
+		container_of(vd, struct bcm2835_desc, vd));
+}
+
+static void bcm2835_dma_create_cb_set_length(
+	struct bcm2835_chan *chan,
+	struct bcm2835_dma_cb *control_block,
+	size_t len,
+	size_t period_len,
+	size_t *total_len,
+	u32 finalextrainfo)
+{
+	/* set the length */
+	control_block->length = len;
+
+	/* finished if we have no period_length */
+	if (!period_len)
+		return;
+
+	/*
+	 * period_len means: that we need to generate
+	 * transfers that are terminating at every
+	 * multiple of period_len - this is typically
+	 * used to set the interrupt flag in info
+	 * which is required during cyclic transfers
+	 */
+
+	/* have we filled in period_length yet? */
+	if (*total_len + control_block->length < period_len)
+		return;
+
+	/* calculate the length that remains to reach period_length */
+	control_block->length = period_len - *total_len;
+
+	/* reset total_length for next period */
+	*total_len = 0;
+
+	/* add extrainfo bits in info */
+	control_block->info |= finalextrainfo;
+}
+
+/**
+ * bcm2835_dma_create_cb_chain - create a control block and fills data in
+ *
+ * @chan:           the @dma_chan for which we run this
+ * @direction:      the direction in which we transfer
+ * @cyclic:         it is a cyclic transfer
+ * @info:           the default info bits to apply per controlblock
+ * @frames:         number of controlblocks to allocate
+ * @src:            the src address to assign (if the S_INC bit is set
+ *                  in @info, then it gets incremented)
+ * @dst:            the dst address to assign (if the D_INC bit is set
+ *                  in @info, then it gets incremented)
+ * @buf_len:        the full buffer length (may also be 0)
+ * @period_len:     the period length when to apply @finalextrainfo
+ *                  in addition to the last transfer
+ *                  this will also break some control-blocks early
+ * @finalextrainfo: additional bits in last controlblock
+ *                  (or when period_len is reached in case of cyclic)
+ * @gfp:            the GFP flag to use for allocation
+ */
+static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
+	struct dma_chan *chan, enum dma_transfer_direction direction,
+	bool cyclic, u32 info, u32 finalextrainfo, size_t frames,
+	dma_addr_t src, dma_addr_t dst, size_t buf_len,
+	size_t period_len, gfp_t gfp)
+{
+	struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+	size_t len = buf_len, total_len;
+	size_t frame;
+	struct bcm2835_desc *d;
+	struct bcm2835_cb_entry *cb_entry;
+	struct bcm2835_dma_cb *control_block;
+
+	/* allocate and setup the descriptor. */
+	d = kzalloc(sizeof(*d) + frames * sizeof(struct bcm2835_cb_entry),
+		    gfp);
+	if (!d)
+		return NULL;
+
+	d->c = c;
+	d->dir = direction;
+	d->cyclic = cyclic;
+
+	/*
+	 * Iterate over all frames, create a control block
+	 * for each frame and link them together.
+	 */
+	for (frame = 0, total_len = 0; frame < frames; d->frames++, frame++) {
+		cb_entry = &d->cb_list[frame];
+		cb_entry->cb = dma_pool_alloc(c->cb_pool, gfp,
+					      &cb_entry->paddr);
+		if (!cb_entry->cb)
+			goto error_cb;
+
+		/* fill in the control block */
+		control_block = cb_entry->cb;
+		control_block->info = info;
+		control_block->src = src;
+		control_block->dst = dst;
+		control_block->stride = 0;
+		control_block->next = 0;
+		/* set up length in control_block if requested */
+		if (buf_len) {
+			/* calculate length honoring period_length */
+			bcm2835_dma_create_cb_set_length(
+				c, control_block,
+				len, period_len, &total_len,
+				cyclic ? finalextrainfo : 0);
+
+			/* calculate new remaining length */
+			len -= control_block->length;
+		}
+
+		/* link this the last controlblock */
+		if (frame)
+			d->cb_list[frame - 1].cb->next = cb_entry->paddr;
+
+		/* update src and dst and length */
+		if (src && (info & BCM2835_DMA_S_INC))
+			src += control_block->length;
+		if (dst && (info & BCM2835_DMA_D_INC))
+			dst += control_block->length;
+
+		/* Length of total transfer */
+		d->size += control_block->length;
+	}
+
+	/* the last frame requires extra flags */
+	d->cb_list[d->frames - 1].cb->info |= finalextrainfo;
+
+	/* detect a size missmatch */
+	if (buf_len && (d->size != buf_len))
+		goto error_cb;
+
+	return d;
+error_cb:
+	bcm2835_dma_free_cb_chain(d);
+
+	return NULL;
+}
+
 static int bcm2835_dma_abort(void __iomem *chan_base)
 {
 	unsigned long cs;
@@ -417,12 +566,11 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
 	unsigned long flags)
 {
 	struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-	enum dma_slave_buswidth dev_width;
 	struct bcm2835_desc *d;
-	dma_addr_t dev_addr;
-	unsigned int es, sync_type;
-	unsigned int frame;
-	int i;
+	dma_addr_t src, dst;
+	u32 info = BCM2835_DMA_WAIT_RESP;
+	u32 extra = BCM2835_DMA_INT_EN;
+	size_t frames;
 
 	/* Grab configuration */
 	if (!is_slave_direction(direction)) {
@@ -430,104 +578,58 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
 		return NULL;
 	}
 
-	if (direction == DMA_DEV_TO_MEM) {
-		dev_addr = c->cfg.src_addr;
-		dev_width = c->cfg.src_addr_width;
-		sync_type = BCM2835_DMA_S_DREQ;
-	} else {
-		dev_addr = c->cfg.dst_addr;
-		dev_width = c->cfg.dst_addr_width;
-		sync_type = BCM2835_DMA_D_DREQ;
-	}
-
-	/* Bus width translates to the element size (ES) */
-	switch (dev_width) {
-	case DMA_SLAVE_BUSWIDTH_4_BYTES:
-		es = BCM2835_DMA_DATA_TYPE_S32;
-		break;
-	default:
+	if (!buf_len) {
+		dev_err(chan->device->dev,
+			"%s: bad buffer length (= 0)\n", __func__);
 		return NULL;
 	}
 
-	/* Now allocate and setup the descriptor. */
-	d = kzalloc(sizeof(*d), GFP_NOWAIT);
-	if (!d)
-		return NULL;
+	/*
+	 * warn if buf_len is not a multiple of period_len - this may leed
+	 * to unexpected latencies for interrupts and thus audiable clicks
+	 */
+	if (buf_len % period_len)
+		dev_warn_once(chan->device->dev,
+			      "%s: buffer_length (%zd) is not a multiple of period_len (%zd)\n",
+			      __func__, buf_len, period_len);
 
-	d->c = c;
-	d->dir = direction;
-	d->frames = buf_len / period_len;
-	d->cyclic = true;
+	/* Setup DREQ channel */
+	if (c->dreq != 0)
+		info |= BCM2835_DMA_PER_MAP(c->dreq);
 
-	d->cb_list = kcalloc(d->frames, sizeof(*d->cb_list), GFP_KERNEL);
-	if (!d->cb_list) {
-		kfree(d);
-		return NULL;
+	if (direction == DMA_DEV_TO_MEM) {
+		if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
+			return NULL;
+		src = c->cfg.src_addr;
+		dst = buf_addr;
+		info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
+	} else {
+		if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
+			return NULL;
+		dst = c->cfg.dst_addr;
+		src = buf_addr;
+		info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
 	}
-	/* Allocate memory for control blocks */
-	for (i = 0; i < d->frames; i++) {
-		struct bcm2835_cb_entry *cb_entry = &d->cb_list[i];
 
-		cb_entry->cb = dma_pool_zalloc(c->cb_pool, GFP_ATOMIC,
-					       &cb_entry->paddr);
-		if (!cb_entry->cb)
-			goto error_cb;
-	}
+	/* calculate number of frames */
+	frames = DIV_ROUND_UP(buf_len, period_len);
 
 	/*
-	 * Iterate over all frames, create a control block
-	 * for each frame and link them together.
+	 * allocate the CB chain
+	 * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine
+	 * implementation calls prep_dma_cyclic with interrupts disabled.
 	 */
-	for (frame = 0; frame < d->frames; frame++) {
-		struct bcm2835_dma_cb *control_block = d->cb_list[frame].cb;
-
-		/* Setup adresses */
-		if (d->dir == DMA_DEV_TO_MEM) {
-			control_block->info = BCM2835_DMA_D_INC;
-			control_block->src = dev_addr;
-			control_block->dst = buf_addr + frame * period_len;
-		} else {
-			control_block->info = BCM2835_DMA_S_INC;
-			control_block->src = buf_addr + frame * period_len;
-			control_block->dst = dev_addr;
-		}
-
-		/* Enable interrupt */
-		control_block->info |= BCM2835_DMA_INT_EN;
-
-		/* Setup synchronization */
-		if (sync_type != 0)
-			control_block->info |= sync_type;
-
-		/* Setup DREQ channel */
-		if (c->dreq != 0)
-			control_block->info |=
-				BCM2835_DMA_PER_MAP(c->dreq);
-
-		/* Length of a frame */
-		control_block->length = period_len;
-		d->size += control_block->length;
+	d = bcm2835_dma_create_cb_chain(chan, direction, true,
+					info, extra,
+					frames, src, dst, buf_len,
+					period_len, GFP_NOWAIT);
+	if (!d)
+		return NULL;
 
-		/*
-		 * Next block is the next frame.
-		 * This DMA engine driver currently only supports cyclic DMA.
-		 * Therefore, wrap around at number of frames.
-		 */
-		control_block->next = d->cb_list[((frame + 1) % d->frames)].paddr;
-	}
+	/* wrap around into a loop */
+	d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
 
 	return vchan_tx_prep(&c->vc, &d->vd, flags);
-error_cb:
-	i--;
-	for (; i >= 0; i--) {
-		struct bcm2835_cb_entry *cb_entry = &d->cb_list[i];
-
-		dma_pool_free(c->cb_pool, cb_entry->cb, cb_entry->paddr);
-	}
-
-	kfree(d->cb_list);
-	kfree(d);
-	return NULL;
 }
 
 static int bcm2835_dma_slave_config(struct dma_chan *chan,
-- 
2.1.4

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[PATCH v3 08/11] dmaengine: bcm2835: limit max length based on channel type

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

The bcm2835 dma system has 2 basic types of dma-channels:
* "normal" channels
* "light" channels

Lite channels are limited in several aspects:
* internal data-structure is 128 bit (not 256)
* does not support BCM2835_DMA_TDMODE (2D)
* DMA length register is limited to 16 bit.
  so 0-65535 (not 0-65536 as mentioned in the official datasheet)
* BCM2835_DMA_S/D_IGNORE are not supported

The detection of the type of mode is implemented by looking at
the LITE bit in the DEBUG register for each channel.
This allows automatic detection.

Based on this the maximum block size is set to (64K - 4) or to 1G
and this limit is honored during generation of control block
chains. The effect is that when a LITE channel is used more
control blocks are used to do the same transfer (compared
to a normal channel).

As there are several sources/target DREQS that are 32 bit wide
we need to have the transfer to be a multiple of 4 as this would
break he transfer otherwise.

This is why the limit of (64K - 4) was chosen over the
alternative of (64K - 4K).

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
---
 drivers/dma/bcm2835-dma.c | 29 ++++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index 1ae53b8..024c949 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -83,6 +83,8 @@ struct bcm2835_chan {
 
 	int irq_number;
 	unsigned long irq_flags;
+
+	bool is_lite_channel;
 };
 
 struct bcm2835_desc {
@@ -185,6 +187,16 @@ struct bcm2835_desc {
 #define BCM2835_DMA_IRQ_SHARED_DEFAULT	11
 #define BCM2835_DMA_IRQ_ALL_DEFAULT	12
 
+/* the max dma length for different channels */
+#define MAX_DMA_LEN SZ_1G
+#define MAX_LITE_DMA_LEN (SZ_64K - 4)
+
+static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c)
+{
+	/* lite and normal channels have different max frame length */
+	return c->is_lite_channel ? MAX_LITE_DMA_LEN : MAX_DMA_LEN;
+}
+
 /* how many frames of max_len size do we need to transfer len bytes */
 static inline size_t bcm2835_dma_frames_for_length(size_t len,
 						   size_t max_len)
@@ -233,8 +245,10 @@ static void bcm2835_dma_create_cb_set_length(
 	size_t *total_len,
 	u32 finalextrainfo)
 {
-	/* set the length */
-	control_block->length = len;
+	size_t max_len = bcm2835_dma_max_frame_length(chan);
+
+	/* set the length taking lite-channel limitations into account */
+	control_block->length = min_t(u32, len, max_len);
 
 	/* finished if we have no period_length */
 	if (!period_len)
@@ -570,6 +584,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
 	dma_addr_t src, dst;
 	u32 info = BCM2835_DMA_WAIT_RESP;
 	u32 extra = BCM2835_DMA_INT_EN;
+	size_t max_len = bcm2835_dma_max_frame_length(c);
 	size_t frames;
 
 	/* Grab configuration */
@@ -612,7 +627,10 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
 	}
 
 	/* calculate number of frames */
-	frames = DIV_ROUND_UP(buf_len, period_len);
+	frames = /* number of periods */
+		 DIV_ROUND_UP(buf_len, period_len) *
+		 /* number of frames per period */
+		 bcm2835_dma_frames_for_length(period_len, max_len);
 
 	/*
 	 * allocate the CB chain
@@ -713,6 +731,11 @@ static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id,
 	c->irq_number = irq;
 	c->irq_flags = irq_flags;
 
+	/* check in DEBUG register if this is a LITE channel */
+	if (readl(c->chan_base + BCM2835_DMA_DEBUG) &
+		BCM2835_DMA_DEBUG_LITE)
+		c->is_lite_channel = true;
+
 	return 0;
 }
 
-- 
2.1.4

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[PATCH v3 09/11] dmaengine: bcm2835: add slave_sg support to bcm2835-dma

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Add slave_sg support to bcm2835-dma using shared allocation
code for bcm2835_desc and DMA-control blocks already used by
dma_cyclic.

Note that bcm2835_dma_callback had to get modified to support
both modes of operation (cyclic and non-cyclic).

Tested using:
* Hifiberry I2S card (using cyclic DMA)
* fb_st7735r SPI-framebuffer (using slave_sg DMA via spi-bcm2835)
playing BigBuckBunny for audio and video.

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
Reviewed-by: Eric Anholt <eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org>
---
 drivers/dma/bcm2835-dma.c | 113 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 108 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index 024c949..6c4b4e2 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -276,6 +276,23 @@ static void bcm2835_dma_create_cb_set_length(
 	control_block->info |= finalextrainfo;
 }
 
+static inline size_t bcm2835_dma_count_frames_for_sg(
+	struct bcm2835_chan *c,
+	struct scatterlist *sgl,
+	unsigned int sg_len)
+{
+	size_t frames = 0;
+	struct scatterlist *sgent;
+	unsigned int i;
+	size_t plength = bcm2835_dma_max_frame_length(c);
+
+	for_each_sg(sgl, sgent, sg_len, i)
+		frames += bcm2835_dma_frames_for_length(
+			sg_dma_len(sgent), plength);
+
+	return frames;
+}
+
 /**
  * bcm2835_dma_create_cb_chain - create a control block and fills data in
  *
@@ -377,6 +394,32 @@ error_cb:
 	return NULL;
 }
 
+static void bcm2835_dma_fill_cb_chain_with_sg(
+	struct dma_chan *chan,
+	enum dma_transfer_direction direction,
+	struct bcm2835_cb_entry *cb,
+	struct scatterlist *sgl,
+	unsigned int sg_len)
+{
+	struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+	size_t max_len = bcm2835_dma_max_frame_length(c);
+	unsigned int i, len;
+	dma_addr_t addr;
+	struct scatterlist *sgent;
+
+	for_each_sg(sgl, sgent, sg_len, i) {
+		for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent);
+		     len > 0;
+		     addr += cb->cb->length, len -= cb->cb->length, cb++) {
+			if (direction == DMA_DEV_TO_MEM)
+				cb->cb->dst = addr;
+			else
+				cb->cb->src = addr;
+			cb->cb->length = min(len, max_len);
+		}
+	}
+}
+
 static int bcm2835_dma_abort(void __iomem *chan_base)
 {
 	unsigned long cs;
@@ -453,12 +496,18 @@ static irqreturn_t bcm2835_dma_callback(int irq, void *data)
 	d = c->desc;
 
 	if (d) {
-		/* TODO Only works for cyclic DMA */
-		vchan_cyclic_callback(&d->vd);
-	}
+		if (d->cyclic) {
+			/* call the cyclic callback */
+			vchan_cyclic_callback(&d->vd);
 
-	/* Keep the DMA engine running */
-	writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
+			/* Keep the DMA engine running */
+			writel(BCM2835_DMA_ACTIVE,
+			       c->chan_base + BCM2835_DMA_CS);
+		} else {
+			vchan_cookie_complete(&c->desc->vd);
+			bcm2835_dma_start_desc(c);
+		}
+	}
 
 	spin_unlock_irqrestore(&c->vc.lock, flags);
 
@@ -574,6 +623,58 @@ static void bcm2835_dma_issue_pending(struct dma_chan *chan)
 	spin_unlock_irqrestore(&c->vc.lock, flags);
 }
 
+static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
+	struct dma_chan *chan,
+	struct scatterlist *sgl, unsigned int sg_len,
+	enum dma_transfer_direction direction,
+	unsigned long flags, void *context)
+{
+	struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+	struct bcm2835_desc *d;
+	dma_addr_t src = 0, dst = 0;
+	u32 info = BCM2835_DMA_WAIT_RESP;
+	u32 extra = BCM2835_DMA_INT_EN;
+	size_t frames;
+
+	if (!is_slave_direction(direction)) {
+		dev_err(chan->device->dev,
+			"%s: bad direction?\n", __func__);
+		return NULL;
+	}
+
+	if (c->dreq != 0)
+		info |= BCM2835_DMA_PER_MAP(c->dreq);
+
+	if (direction == DMA_DEV_TO_MEM) {
+		if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
+			return NULL;
+		src = c->cfg.src_addr;
+		info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
+	} else {
+		if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
+			return NULL;
+		dst = c->cfg.dst_addr;
+		info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
+	}
+
+	/* count frames in sg list */
+	frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len);
+
+	/* allocate the CB chain */
+	d = bcm2835_dma_create_cb_chain(chan, direction, false,
+					info, extra,
+					frames, src, dst, 0, 0,
+					GFP_KERNEL);
+	if (!d)
+		return NULL;
+
+	/* fill in frames with scatterlist pointers */
+	bcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list,
+					  sgl, sg_len);
+
+	return vchan_tx_prep(&c->vc, &d->vd, flags);
+}
+
 static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
 	struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 	size_t period_len, enum dma_transfer_direction direction,
@@ -807,11 +908,13 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
 	dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 	dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
 	dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
+	dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 	od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
 	od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
 	od->ddev.device_tx_status = bcm2835_dma_tx_status;
 	od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
 	od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
+	od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
 	od->ddev.device_config = bcm2835_dma_slave_config;
 	od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
 	od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
-- 
2.1.4

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[PATCH v3 10/11] dmaengine: bcm2835: add dma_memcopy support to bcm2835-dma

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Add dma_memcopy support to bcm2835-dma.

Also added check for an error condition in bcm2835_dma_create_cb_chain
that showed up during development of this patch.

Tested using dmatest for all 11 available dma channels with the
following output:
[  476.543529] dmatest: Started 1 threads using dma0chan0
[  489.011154] dmatest: dma0chan0-copy0: summary 10000 tests, 0 failures 802 iops 6452 KB/s (0)
[  489.078379] dmatest: Started 1 threads using dma0chan1
[  501.494448] dmatest: dma0chan1-copy0: summary 10000 tests, 0 failures 806 iops 6376 KB/s (0)
[  501.562567] dmatest: Started 1 threads using dma0chan10
[  514.515164] dmatest: dma0chan10-copy: summary 10000 tests, 0 failures 772 iops 6169 KB/s (0)
[  514.582969] dmatest: Started 1 threads using dma0chan2
[  527.092284] dmatest: dma0chan2-copy0: summary 10000 tests, 0 failures 800 iops 6405 KB/s (0)
[  527.160290] dmatest: Started 1 threads using dma0chan3
[  539.541064] dmatest: dma0chan3-copy0: summary 10000 tests, 0 failures 808 iops 6424 KB/s (0)
[  539.608849] dmatest: Started 1 threads using dma0chan4
[  552.402978] dmatest: dma0chan4-copy0: summary 10000 tests, 0 failures 782 iops 6286 KB/s (0)
[  552.470852] dmatest: Started 1 threads using dma0chan5
[  565.184158] dmatest: dma0chan5-copy0: summary 10000 tests, 0 failures 787 iops 6231 KB/s (0)
[  565.251846] dmatest: Started 1 threads using dma0chan6
[  577.959385] dmatest: dma0chan6-copy0: summary 10000 tests, 0 failures 787 iops 6244 KB/s (0)
[  578.027259] dmatest: Started 1 threads using dma0chan7
[  590.834078] dmatest: dma0chan7-copy0: summary 10000 tests, 0 failures 781 iops 6295 KB/s (0)
[  590.901668] dmatest: Started 1 threads using dma0chan8
[  603.640192] dmatest: dma0chan8-copy0: summary 10000 tests, 0 failures 785 iops 6265 KB/s (0)
[  603.708531] dmatest: Started 1 threads using dma0chan9
[  616.420882] dmatest: dma0chan9-copy0: summary 10000 tests, 0 failures 787 iops 6285 KB/s (0)

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
Reviewed-by: Eric Anholt <eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org>
---
 drivers/dma/bcm2835-dma.c | 36 +++++++++++++++++++++++++++++++++++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index 6c4b4e2..2884285 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -326,6 +326,9 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
 	struct bcm2835_cb_entry *cb_entry;
 	struct bcm2835_dma_cb *control_block;
 
+	if (!frames)
+		return NULL;
+
 	/* allocate and setup the descriptor. */
 	d = kzalloc(sizeof(*d) + frames * sizeof(struct bcm2835_cb_entry),
 		    gfp);
@@ -623,6 +626,34 @@ static void bcm2835_dma_issue_pending(struct dma_chan *chan)
 	spin_unlock_irqrestore(&c->vc.lock, flags);
 }
 
+struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy(
+	struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
+	size_t len, unsigned long flags)
+{
+	struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+	struct bcm2835_desc *d;
+	u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC;
+	u32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP;
+	size_t max_len = bcm2835_dma_max_frame_length(c);
+	size_t frames;
+
+	/* if src, dst or len is not given return with an error */
+	if (!src || !dst || !len)
+		return NULL;
+
+	/* calculate number of frames */
+	frames = bcm2835_dma_frames_for_length(len, max_len);
+
+	/* allocate the CB chain - this also fills in the pointers */
+	d = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false,
+					info, extra, frames,
+					src, dst, len, 0, GFP_KERNEL);
+	if (!d)
+		return NULL;
+
+	return vchan_tx_prep(&c->vc, &d->vd, flags);
+}
+
 static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
 	struct dma_chan *chan,
 	struct scatterlist *sgl, unsigned int sg_len,
@@ -909,17 +940,20 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
 	dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
 	dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
 	dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
+	dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask);
 	od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
 	od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
 	od->ddev.device_tx_status = bcm2835_dma_tx_status;
 	od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
 	od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
 	od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
+	od->ddev.device_prep_dma_memcpy = bcm2835_dma_prep_dma_memcpy;
 	od->ddev.device_config = bcm2835_dma_slave_config;
 	od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
 	od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 	od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
-	od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+	od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
+			      BIT(DMA_MEM_TO_MEM);
 	od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
 	od->ddev.dev = &pdev->dev;
 	INIT_LIST_HEAD(&od->ddev.channels);
-- 
2.1.4

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[PATCH v3 11/11] dmaengine: bcm2835: expose dma registers via debugfs

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Expose all the dma registers via debugfs.
The mapping between linux channels and HW-dma channels is
also exposed via a softlink in debugfs.

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
---
 drivers/dma/bcm2835-dma.c | 147 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index 2884285..e2aea4a 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -29,6 +29,7 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
+#include <linux/debugfs.h>
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
 #include <linux/dmapool.h>
@@ -51,6 +52,7 @@ struct bcm2835_dmadev {
 	spinlock_t lock;
 	void __iomem *base;
 	struct device_dma_parameters dma_parms;
+	struct dentry *debugfs_node;
 };
 
 struct bcm2835_dma_cb {
@@ -904,6 +906,147 @@ static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
 	return chan;
 }
 
+#ifdef CONFIG_DEBUG_FS
+static struct debugfs_reg32 bcm2835_dma_debugfs_common_reg32[] = {
+	{
+		.name = "int_status",
+		.offset = BCM2835_DMA_INT_STATUS,
+	},
+	{
+		.name = "enable",
+		.offset = BCM2835_DMA_ENABLE,
+	},
+};
+
+static void bcm2835_dma_debugfs_register_common(struct bcm2835_dmadev *od)
+{
+	struct debugfs_regset32 *regset;
+
+	regset = devm_kzalloc(od->ddev.dev, sizeof(*regset), GFP_KERNEL);
+	if (!regset)
+		return;
+
+	regset->regs  = bcm2835_dma_debugfs_common_reg32;
+	regset->nregs = ARRAY_SIZE(bcm2835_dma_debugfs_common_reg32);
+	regset->base  = od->base;
+
+	debugfs_create_regset32("common", S_IRUGO, od->debugfs_node, regset);
+}
+
+static struct debugfs_reg32 bcm2835_dma_debugfs_channel_reg32[] = {
+	{
+		.name = "cs         ",
+		.offset = BCM2835_DMA_CS,
+	},
+	{
+		.name = "addr       ",
+		.offset = BCM2835_DMA_ADDR,
+	},
+	{
+		.name = "ti         ",
+		.offset = BCM2835_DMA_TI,
+	},
+	{
+		.name = "source     ",
+		.offset = BCM2835_DMA_SOURCE_AD,
+	},
+	{
+		.name = "destination",
+		.offset = BCM2835_DMA_DEST_AD,
+	},
+	{
+		.name = "length     ",
+		.offset = BCM2835_DMA_LEN,
+	},
+	{
+		.name = "stride     ",
+		.offset = BCM2835_DMA_STRIDE,
+	},
+	{
+		.name = "next       ",
+		.offset = BCM2835_DMA_NEXTCB,
+	},
+	{
+		.name = "debug      ",
+		.offset = BCM2835_DMA_DEBUG,
+	},
+};
+
+static void bcm2835_dma_debugfs_register_channel(struct bcm2835_dmadev *od,
+						 int channel)
+{
+	struct debugfs_regset32 *regset;
+	char *name;
+
+	regset = devm_kzalloc(od->ddev.dev, sizeof(*regset), GFP_KERNEL);
+	if (!regset)
+		return;
+
+	name = devm_kasprintf(od->ddev.dev, GFP_KERNEL, "%02d", channel);
+	if (!name)
+		return;
+
+	regset->regs  = bcm2835_dma_debugfs_channel_reg32;
+	regset->nregs = ARRAY_SIZE(bcm2835_dma_debugfs_channel_reg32);
+	regset->base  = BCM2835_DMA_CHANIO(od->base, channel);
+
+	/*
+	 * expose, but only for the owner (=root)
+	 * contains pointers that should not leak
+	 */
+	debugfs_create_regset32(name, S_IRUSR, od->debugfs_node, regset);
+}
+
+static void bcm2835_dma_debugfs_register_link(struct bcm2835_dmadev *od,
+					      struct dma_chan *chan)
+{
+	struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+	char *name;
+
+	name = devm_kasprintf(od->ddev.dev, GFP_KERNEL, "%02d", c->ch);
+	if (!name)
+		return;
+
+	debugfs_create_symlink(dev_name(&chan->dev->device),
+			       od->debugfs_node, name);
+}
+
+static void bcm2835_dma_debugfs_register(struct bcm2835_dmadev *od)
+{
+	struct dma_chan *chan;
+	int i;
+
+	od->debugfs_node = debugfs_create_dir(dev_name(od->ddev.dev), NULL);
+	if (!od->debugfs_node)
+		return;
+
+	/* expose the common registers */
+	bcm2835_dma_debugfs_register_common(od);
+
+	/* register all the real channels - not only the mapped ones */
+	for (i = 0; i <= BCM2835_DMA_MAX_CHANNEL_NUMBER; i++)
+		bcm2835_dma_debugfs_register_channel(od, i);
+
+	/* create the softlinks */
+	list_for_each_entry(chan, &od->ddev.channels, device_node) {
+		bcm2835_dma_debugfs_register_link(od, chan);
+	}
+}
+
+static void bcm2835_dma_debugfs_remove(struct bcm2835_dmadev *od)
+{
+	debugfs_remove_recursive(od->debugfs_node);
+
+	od->debugfs_node = NULL;
+}
+
+#else
+static void bcm2835_dma_debugfs_register(struct bcm2835_dmadev *od)
+{ }
+static void bcm2835_dma_debugfs_remove(struct bcm2835_dmadev *od)
+{ }
+#endif
+
 static int bcm2835_dma_probe(struct platform_device *pdev)
 {
 	struct bcm2835_dmadev *od;
@@ -1022,6 +1165,8 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
 		goto err_no_dma;
 	}
 
+	bcm2835_dma_debugfs_register(od);
+
 	dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");
 
 	return 0;
@@ -1035,6 +1180,8 @@ static int bcm2835_dma_remove(struct platform_device *pdev)
 {
 	struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
 
+	bcm2835_dma_debugfs_remove(od);
+
 	dma_async_device_unregister(&od->ddev);
 	bcm2835_dma_free(od);
 
-- 
2.1.4

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