From: <tthayer@opensource.altera.com>
To: bp@alien8.de, dougthompson@xmission.com, m.chehab@samsung.com,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linux@arm.linux.org.uk, dinguyen@opensource.altera.com,
grant.likely@linaro.org
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, tthayer.linux@gmail.com,
tthayer@opensource.altera.com,
linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org
Subject: [PATCHv2 04/11] EDAC, altera: Add register offset for ECC Error Inject
Date: Mon, 7 Mar 2016 13:43:00 -0600 [thread overview]
Message-ID: <1457379787-8327-5-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1457379787-8327-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
In preparation for the Arria10 peripheral ECCs, a register
offset from the ECC base was added to the private data
structure to index to the error injection register.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2: Split large patch into smaller patches. Add an ECC
error inject offset to support the different register
layout of Arria10 peripheral ECCs.
---
drivers/edac/altera_edac.c | 7 +++++--
drivers/edac/altera_edac.h | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 138446c..9e62a49 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -622,8 +622,9 @@ static ssize_t altr_edac_device_trig(struct file *file,
if (ACCESS_ONCE(ptemp[i]))
result = -1;
/* Toggle Error bit (it is latched), leave ECC enabled */
- writel(error_mask, drvdata->base);
- writel(priv->ecc_enable_mask, drvdata->base);
+ writel(error_mask, (drvdata->base + priv->set_err_ofst));
+ writel(priv->ecc_enable_mask, (drvdata->base +
+ priv->set_err_ofst));
ptemp[i] = i;
}
/* Ensure it has been written out */
@@ -881,6 +882,7 @@ const struct edac_device_prv_data ocramecc_data = {
.ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
.ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
.ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
+ .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
.trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
};
@@ -954,6 +956,7 @@ const struct edac_device_prv_data l2ecc_data = {
.ecc_en_ofst = ALTR_L2_ECC_REG_OFFSET,
.ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
.ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
+ .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
.trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
};
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index 54e2742..d4105b0 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -232,6 +232,7 @@ struct edac_device_prv_data {
int ecc_en_ofst;
int ce_set_mask;
int ue_set_mask;
+ int set_err_ofst;
int trig_alloc_sz;
};
--
1.7.9.5
next prev parent reply other threads:[~2016-03-07 19:43 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-07 19:42 [PATCHv2 0/11] Series adding Altera Arria10 L2 Cache EDAC tthayer
2016-03-07 19:42 ` [PATCHv2 01/11] EDAC: Altera L2 Kconfig change from select to depends upon tthayer
2016-03-07 19:42 ` [PATCHv2 02/11] EDAC, altera: Move Device structs and defines to header file tthayer
2016-03-07 19:42 ` [PATCHv2 03/11] EDAC, altera: Add register offset for ECC Enable tthayer
2016-03-07 19:43 ` tthayer [this message]
2016-03-07 19:43 ` [PATCHv2 05/11] EDAC, altera: Add register offset for ECC Error Clear tthayer
2016-03-07 19:43 ` [PATCHv2 06/11] EDAC, altera: Add IRQ flags to private data struct tthayer
2016-03-07 19:43 ` [PATCHv2 07/11] EDAC, altera: Add status offset & masks tthayer
2016-03-08 15:52 ` Thor Thayer
2016-03-07 19:43 ` [PATCHv2 08/11] Documentation: dt: socfpga: Add Altera Arria10 L2 cache binding tthayer
2016-03-07 19:43 ` [PATCHv2 09/11] EDAC, altera: Addition of Arria10 L2 Cache ECC tthayer
2016-03-07 19:43 ` [PATCHv2 10/11] ARM: socfpga: Enable Arria10 L2 cache ECC on startup tthayer
2016-03-08 14:45 ` Dinh Nguyen
2016-03-07 19:43 ` [PATCHv2 11/11] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry tthayer
2016-03-08 14:50 ` Dinh Nguyen
2016-03-08 15:59 ` Thor Thayer
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1457379787-8327-5-git-send-email-tthayer@opensource.altera.com \
--to=tthayer@opensource.altera.com \
--cc=bp@alien8.de \
--cc=devicetree@vger.kernel.org \
--cc=dinguyen@opensource.altera.com \
--cc=dougthompson@xmission.com \
--cc=galak@codeaurora.org \
--cc=grant.likely@linaro.org \
--cc=ijc+devicetree@hellion.org.uk \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-edac@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@arm.linux.org.uk \
--cc=m.chehab@samsung.com \
--cc=mark.rutland@arm.com \
--cc=pawel.moll@arm.com \
--cc=robh+dt@kernel.org \
--cc=tthayer.linux@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).