From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: [PATCH v3 05/19] dt-bindings: clk: sun5i: add DRAM gates compatible Date: Wed, 23 Mar 2016 17:38:28 +0100 Message-ID: <1458751122-23976-6-git-send-email-maxime.ripard@free-electrons.com> References: <1458751122-23976-1-git-send-email-maxime.ripard@free-electrons.com> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <1458751122-23976-1-git-send-email-maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Mike Turquette , Stephen Boyd , David Airlie , Thierry Reding , Rob Herring , Chen-Yu Tsai , Daniel Vetter Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Laurent Pinchart , Hans de Goede , Alexander Kaplan , Boris Brezillon , Thomas Petazzoni , Rob Clark , Maxime Ripard List-Id: devicetree@vger.kernel.org The Allwinner SoCs have a gate controller to gate the access to the DRAM clock to the some devices that need to access the DRAM directly (mostly display / image related IPs). Use a simple gates driver to support the one found in the A13 / R8 SoCs. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 54192c1a98dc..e194cda2f469 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -66,6 +66,7 @@ Required properties: "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80 "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10 "allwinner,sun4i-a10-display-clk" - for the display clocks on the A10 + "allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13 "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 "allwinner,sun4i-a10-mmc-clk" - for the MMC clock "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 -- 2.7.3