[PATCH 06/17] watchdog: qcom: update device tree bindings

[PATCH 06/17] watchdog: qcom: update device tree bindings

[Matthew McClintock]

Update the compatible string to align with driver

CC: linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Matthew McClintock <mmcclint-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
index 4726924..60bb2f98 100644
--- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
@@ -4,9 +4,8 @@ Qualcomm Krait Processor Sub-system (KPSS) Watchdog
 Required properties :
 - compatible : shall contain only one of the following:
 
-			"qcom,kpss-wdt-msm8960"
-			"qcom,kpss-wdt-apq8064"
-			"qcom,kpss-wdt-ipq8064"
+			"qcom,kpss-timer"
+			"qcom,scss-timer"
 
 - reg : shall contain base register location and length
 - clocks : shall contain the input clock
-- 
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a Linux Foundation Collaborative Project

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[PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Matthew McClintock]

Update the compatible string to add new device tree binding

CC: linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Matthew McClintock <mmcclint-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
index 60bb2f98..45b37cf 100644
--- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
@@ -6,6 +6,7 @@ Required properties :
 
 			"qcom,kpss-timer"
 			"qcom,scss-timer"
+			"qcom,kpss-standalone"
 
 - reg : shall contain base register location and length
 - clocks : shall contain the input clock
-- 
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a Linux Foundation Collaborative Project

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[PATCH 10/17] qcom: ipq4019: add watchdog node to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This will allow boards to enable watchdog support

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 4 ++++
 arch/arm/boot/dts/qcom-ipq4019.dtsi           | 8 ++++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index fe78f3f..223da1a 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -55,5 +55,9 @@
 			pinctrl-names = "default";
 			status = "ok";
 		};
+
+		watchdog@b017000 {
+			status = "ok";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index e44f5b6..00a5e9e 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -171,5 +171,13 @@
 				<&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "core", "iface";
 		};
+
+		watchdog@b017000 {
+			compatible = "qcom,kpss-standalone";
+			reg = <0xb017000 0x40>;
+			clocks = <&sleep_clk>;
+			timeout-sec = <10>;
+			status = "disabled";
+		};
 	};
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 11/17] qcom: ipq4019: add support for reset via qcom,ps-hold

[Matthew McClintock]

This will allow these types of boards to be rebooted.

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 00a5e9e..acb851d 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -179,5 +179,10 @@
 			timeout-sec = <10>;
 			status = "disabled";
 		};
+
+		restart@4ab000 {
+			compatible = "qcom,pshold";
+			reg = <0x4ab000 0x4>;
+		};
 	};
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 12/17] qcom: ipq4019: add spi node to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This will allow boards to enable the SPI bus

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 37 +++++++++++++++++++++++++++
 arch/arm/boot/dts/qcom-ipq4019.dtsi           | 18 +++++++++++++
 2 files changed, 55 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 223da1a..21032a8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -48,6 +48,43 @@
 					bias-disable;
 				};
 			};
+
+			spi_0_pins: spi_0_pinmux {
+				pinmux {
+					function = "blsp_spi0";
+					pins = "gpio55", "gpio56", "gpio57";
+				};
+				pinmux_cs {
+					function = "gpio";
+					pins = "gpio54";
+				};
+				pinconf {
+					pins = "gpio55", "gpio56", "gpio57";
+					drive-strength = <12>;
+					bias-disable;
+				};
+				pinconf_cs {
+					pins = "gpio54";
+					drive-strength = <2>;
+					bias-disable;
+					output-high;
+				};
+			};
+		};
+
+		spi_0: spi@78b5000 {
+			pinctrl-0 = <&spi_0_pins>;
+			pinctrl-names = "default";
+			status = "ok";
+			cs-gpios = <&tlmm 54 0>;
+
+			mx25l25635e@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0>;
+				compatible = "mx25l25635e";
+				spi-max-frequency = <24000000>;
+			};
 		};
 
 		serial@78af000 {
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index acb851d..99e64f4 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -15,12 +15,18 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. IPQ4019";
 	compatible = "qcom,ipq4019";
 	interrupt-parent = <&intc>;
 
+	aliases {
+		spi0 = &spi_0;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -108,6 +114,18 @@
 			interrupts = <0 208 0>;
 		};
 
+		spi_0: spi@78b5000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x78b5000 0x600>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
                 acc0: clock-controller@b088000 {
                         compatible = "qcom,kpss-acc-v1";
                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 13/17] qcom: ipq4019: add i2c node to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This will allow boards to enable the I2C bus

CC: Sricharan R <srichara@qti.qualcomm.com>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 99e64f4..1937edf 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,6 +25,7 @@
 
 	aliases {
 		spi0 = &spi_0;
+		i2c0 = &i2c_0;
 	};
 
 	cpus {
@@ -126,6 +127,18 @@
 			status = "disabled";
 		};
 
+		i2c_0: i2c@78b7000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x78b7000 0x6000>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+			clock-names = "iface", "core";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
                 acc0: clock-controller@b088000 {
                         compatible = "qcom,kpss-acc-v1";
                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 15/17] qcom: ipq4019: add cpu operating points for cpufreq support

[Matthew McClintock]

This adds some operating points for cpu frequeny scaling

Signed-off-by: Matthew McClintock <mmcclint-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 1937edf..db48fd3 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -40,6 +40,14 @@
 			reg = <0x0>;
 			clocks = <&gcc GCC_APPS_CLK_SRC>;
 			clock-frequency = <0>;
+			operating-points = <
+				/* kHz	uV (fixed) */
+				48000	1100000
+				200000	1100000
+				500000	1100000
+				666000	1100000
+			>;
+			clock-latency = <256000>;
 		};
 
 		cpu@1 {
-- 
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[PATCH 16/17] qcom: ipq4019: add crypto nodes to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This adds the crypto nodes to the ipq4019 device tree, it also adds the
BAM node used by crypto as well which the driver currently requires to
operate properly

The crypto driver itself depends on some other patches to qcom_bam_dma
to function properly:

https://lkml.org/lkml/2015/12/1/113

CC: Stanimir Varbanov <svarbanov@mm-sol.com>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |  8 ++++++++
 arch/arm/boot/dts/qcom-ipq4019.dtsi           | 25 +++++++++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 21032a8..2c347ad 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -93,6 +93,14 @@
 			status = "ok";
 		};
 
+		cryptobam: dma@8e04000 {
+			status = "ok";
+		};
+
+		crypto@8e3a000 {
+			status = "ok";
+		};
+
 		watchdog@b017000 {
 			status = "ok";
 		};
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index db48fd3..3cd42c0 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -147,6 +147,31 @@
 			status = "disabled";
 		};
 
+
+		cryptobam: dma@8e04000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x08e04000 0x20000>;
+			interrupts = <GIC_SPI 207 0>;
+			clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <1>;
+			qcom,controlled-remotely;
+			status = "disabled";
+		};
+
+		crypto@8e3a000 {
+			compatible = "qcom,crypto-v5.1";
+			reg = <0x08e3a000 0x6000>;
+			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
+				 <&gcc GCC_CRYPTO_AXI_CLK>,
+				 <&gcc GCC_CRYPTO_CLK>;
+			clock-names = "iface", "bus", "core";
+			dmas = <&cryptobam 2>, <&cryptobam 3>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
                 acc0: clock-controller@b088000 {
                         compatible = "qcom,kpss-acc-v1";
                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 17/17] qcom: ipq4019: add DMA nodes to ipq4019 SoC and DK01 device tree

[Matthew McClintock]

This adds the blsp_dma node to the device tree and the required
properties for using DMA with serial

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |  4 ++++
 arch/arm/boot/dts/qcom-ipq4019.dtsi           | 15 +++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 2c347ad..b9457dd2 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -72,6 +72,10 @@
 			};
 		};
 
+		blsp_dma: dma@7884000 {
+			status = "ok";
+		};
+
 		spi_0: spi@78b5000 {
 			pinctrl-0 = <&spi_0_pins>;
 			pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 3cd42c0..5c08d19 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -123,6 +123,17 @@
 			interrupts = <0 208 0>;
 		};
 
+		blsp_dma: dma@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x23000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			status = "disabled";
+		};
+
 		spi_0: spi@78b5000 {
 			compatible = "qcom,spi-qup-v2.2.1";
 			reg = <0x78b5000 0x600>;
@@ -224,6 +235,8 @@
 			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 				<&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "core", "iface";
+			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
+			dma-names = "rx", "tx";
 		};
 
 		serial@78b0000 {
@@ -234,6 +247,8 @@
 			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 				<&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "core", "iface";
+			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
+			dma-names = "rx", "tx";
 		};
 
 		watchdog@b017000 {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 06/17] watchdog: qcom: update device tree bindings

[Stephen Boyd]

On 03/23/2016 03:05 PM, Matthew McClintock wrote:
> Update the compatible string to align with driver
>
> CC: linux-watchdog@vger.kernel.org
> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>

I had a patch similar to this before
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325235.html


> ---
>  Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> index 4726924..60bb2f98 100644
> --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> @@ -4,9 +4,8 @@ Qualcomm Krait Processor Sub-system (KPSS) Watchdog
>  Required properties :
>  - compatible : shall contain only one of the following:
>  
> -			"qcom,kpss-wdt-msm8960"
> -			"qcom,kpss-wdt-apq8064"
> -			"qcom,kpss-wdt-ipq8064"
> +			"qcom,kpss-timer"
> +			"qcom,scss-timer"
>  
>  - reg : shall contain base register location and length
>  - clocks : shall contain the input clock

No example update?

-- 
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a Linux Foundation Collaborative Project

Re: [PATCH 15/17] qcom: ipq4019: add cpu operating points for cpufreq support

[Stephen Boyd]

On 03/23/2016 03:05 PM, Matthew McClintock wrote:
> This adds some operating points for cpu frequeny scaling
>
> Signed-off-by: Matthew McClintock <mmcclint-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---

Can you use the v2 OPP bindings instead? I imagine uV could be left out
then because there isn't any regulator control?

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Re: [PATCH 06/17] watchdog: qcom: update device tree bindings

[Matthew McClintock]

> On Mar 23, 2016, at 5:26 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> 
> On 03/23/2016 03:05 PM, Matthew McClintock wrote:
>> Update the compatible string to align with driver
>> 
>> CC: linux-watchdog@vger.kernel.org
>> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
> 
> I had a patch similar to this before
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325235.html

Whoops, your patch looks better. Will drop this one.

-M

Re: [PATCH 06/17] watchdog: qcom: update device tree bindings

[Rob Herring]

On Wed, Mar 23, 2016 at 05:05:01PM -0500, Matthew McClintock wrote:
> Update the compatible string to align with driver
> 
> CC: linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Matthew McClintock <mmcclint-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> index 4726924..60bb2f98 100644
> --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> @@ -4,9 +4,8 @@ Qualcomm Krait Processor Sub-system (KPSS) Watchdog
>  Required properties :
>  - compatible : shall contain only one of the following:
>  
> -			"qcom,kpss-wdt-msm8960"
> -			"qcom,kpss-wdt-apq8064"
> -			"qcom,kpss-wdt-ipq8064"
> +			"qcom,kpss-timer"
> +			"qcom,scss-timer"

Keep the SoC specific ones even if they are not used. The DTS should 
have both strings.

Rob
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Re: [PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Rob Herring]

On Wed, Mar 23, 2016 at 05:05:04PM -0500, Matthew McClintock wrote:
> Update the compatible string to add new device tree binding
> 
> CC: linux-watchdog@vger.kernel.org
> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> index 60bb2f98..45b37cf 100644
> --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> @@ -6,6 +6,7 @@ Required properties :
>  
>  			"qcom,kpss-timer"
>  			"qcom,scss-timer"
> +			"qcom,kpss-standalone"

What SoC(s) is this in. Use SoC specific compatible strings please.

Rob

Re: [PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Matthew McClintock]

On Mar 25, 2016, at 9:15 AM, Rob Herring <robh@kernel.org> wrote:
> 
> On Wed, Mar 23, 2016 at 05:05:04PM -0500, Matthew McClintock wrote:
>> Update the compatible string to add new device tree binding
>> 
>> CC: linux-watchdog@vger.kernel.org
>> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
>> ---
>> Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +
>> 1 file changed, 1 insertion(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>> index 60bb2f98..45b37cf 100644
>> --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>> +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>> @@ -6,6 +6,7 @@ Required properties :
>> 
>> 			"qcom,kpss-timer"
>> 			"qcom,scss-timer"
>> +			"qcom,kpss-standalone"
> 
> What SoC(s) is this in. Use SoC specific compatible strings please.

So ipq4019 wins the race because we are the first to try to enable watchdog for this block?

qcom,kpss-ipq4019 ?

-M

Re: [PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Rob Herring]

On Mon, Mar 28, 2016 at 12:02 PM, Matthew McClintock
<mmcclint@codeaurora.org> wrote:
> On Mar 25, 2016, at 9:15 AM, Rob Herring <robh@kernel.org> wrote:
>>
>> On Wed, Mar 23, 2016 at 05:05:04PM -0500, Matthew McClintock wrote:
>>> Update the compatible string to add new device tree binding
>>>
>>> CC: linux-watchdog@vger.kernel.org
>>> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
>>> ---
>>> Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>>> index 60bb2f98..45b37cf 100644
>>> --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>>> +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
>>> @@ -6,6 +6,7 @@ Required properties :
>>>
>>>                      "qcom,kpss-timer"
>>>                      "qcom,scss-timer"
>>> +                    "qcom,kpss-standalone"
>>
>> What SoC(s) is this in. Use SoC specific compatible strings please.
>
> So ipq4019 wins the race because we are the first to try to enable watchdog for this block?

Yep, that's how it is supposed to work. Newer chips claim
compatibility with older ones.

> qcom,kpss-ipq4019 ?

Yes, but generally <vendor>,<soc>-<block> is preferred order.

Rob

Re: [PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Guenter Roeck]

On Mon, Mar 28, 2016 at 12:02:47PM -0500, Matthew McClintock wrote:
> On Mar 25, 2016, at 9:15 AM, Rob Herring <robh@kernel.org> wrote:
> > 
> > On Wed, Mar 23, 2016 at 05:05:04PM -0500, Matthew McClintock wrote:
> >> Update the compatible string to add new device tree binding
> >> 
> >> CC: linux-watchdog@vger.kernel.org
> >> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
> >> ---
> >> Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +
> >> 1 file changed, 1 insertion(+)
> >> 
> >> diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> >> index 60bb2f98..45b37cf 100644
> >> --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> >> +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
> >> @@ -6,6 +6,7 @@ Required properties :
> >> 
> >> 			"qcom,kpss-timer"
> >> 			"qcom,scss-timer"
> >> +			"qcom,kpss-standalone"
> > 
> > What SoC(s) is this in. Use SoC specific compatible strings please.
> 
> So ipq4019 wins the race because we are the first to try to enable watchdog for this block?
> 
> qcom,kpss-ipq4019 ?
> 
It is a dedicated watchdog block, isn't it ? "qcom,kpss-ipq4019" would not
refer to a specific block. Devicetree maintainers may have a better idea,
but it seems to me that there should be 'wdt' or 'watchdog' in the property
name.

Guenter

Re: [PATCH 09/17] watchdog: qcom: add kpss-standalone to device tree binding

[Matthew McClintock]

On Mar 28, 2016, at 1:15 PM, Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org> wrote:
> 
>>> What SoC(s) is this in. Use SoC specific compatible strings please.
>> 
>> So ipq4019 wins the race because we are the first to try to enable watchdog for this block?
>> 
>> qcom,kpss-ipq4019 ?
>> 
> It is a dedicated watchdog block, isn't it ? "qcom,kpss-ipq4019" would not
> refer to a specific block. Devicetree maintainers may have a better idea,
> but it seems to me that there should be 'wdt' or 'watchdog' in the property
> name.

Sounds fine to me, if no one has any other comments I’ll use this one in the next spin of the patch.

-M--
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Re: [15/17] qcom: ipq4019: add cpu operating points for cpufreq support

[Sven Eckelmann]

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On Mittwoch, 23. März 2016 17:05:10 CET Matthew McClintock wrote:
> This adds some operating points for cpu frequeny scaling
> 
> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
[...]

I saw that you've created a new version of the patch and it was added to
different staging/testing [1] trees.

But I find it rather odd that Codeaurora uses different settings [3]. Here for 
easier comparison:

setting     | QSDK 1.1.3     | proposed patch
---------------------------------------------
clk-latency |         100000 |    256000
opp0        |     48000(000) |  48000000
opp1        |    200000(000) | 200000000
opp2        |    500000(000) | 500000000
opp3        |    710000(000) | 666000000

It looks to me like clk-latency and the opp3 (maximum frequency) are 
different. Is the reason for this difference known?

I've just noticed it because I got an DTB from an ODM which had even
716000(000) set for opp3.

Kind regards,
	Sven

[1] https://git.lede-project.org/?p=lede/blogic/staging.git;a=blob;f=target/linux/ipq806x/patches-4.9/0017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch;h=7cbd6a4551bfd968d013164f76897c603f4ae2ff;hb=627e9c2c36839634d987535658a287843a8a9fd6
[2] https://github.com/chunkeey/LEDE-IPQ40XX/blob/a04cf208fe317074502f7ea81dafa828c89b74bb/target/linux/ipq40xx/patches-4.9/120-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch
[3] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/tree/arch/arm/boot/dts/qcom-ipq40xx.dtsi?h=release/date_r1&id=461894f071b168c963795ebfa15d3458b102730a#n768

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