From: <tthayer@opensource.altera.com>
To: bp@alien8.de, dougthompson@xmission.com, m.chehab@samsung.com,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linux@arm.linux.org.uk, dinguyen@opensource.altera.com,
grant.likely@linaro.org
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
tthayer@opensource.altera.com
Subject: [PATCHv2 2/7] EDAC, altera: Add register offset for ECC Enable
Date: Thu, 31 Mar 2016 13:48:02 -0500 [thread overview]
Message-ID: <1459450087-24792-3-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1459450087-24792-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
In preparation for the Arria10 peripheral ECCs, a register
offset from the ECC base was added to the private data
structure to index to the ECC enable register.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2: No change
---
drivers/edac/altera_edac.c | 3 ++-
drivers/edac/altera_edac.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index fb6fe56..f0a6de7 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -866,7 +866,7 @@ static int altr_ocram_check_deps(struct altr_edac_device_dev *device)
void __iomem *base = device->base;
const struct edac_device_prv_data *prv = device->data;
- if (readl(base) & prv->ecc_enable_mask)
+ if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
return 0;
edac_printk(KERN_ERR, EDAC_DEVICE,
@@ -882,6 +882,7 @@ const struct edac_device_prv_data ocramecc_data = {
.alloc_mem = ocram_alloc_mem,
.free_mem = ocram_free_mem,
.ecc_enable_mask = ALTR_OCR_ECC_EN,
+ .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
.ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
.ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
.set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index c995388..cb6b2b9 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -256,6 +256,7 @@ struct edac_device_prv_data {
void * (*alloc_mem)(size_t size, void **other);
void (*free_mem)(void *p, size_t size, void *other);
int ecc_enable_mask;
+ int ecc_en_ofst;
int ce_set_mask;
int ue_set_mask;
int set_err_ofst;
--
1.7.9.5
next prev parent reply other threads:[~2016-03-31 18:48 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-31 18:48 [PATCHv2 0/7] Add Altera Arria10 OCRAM EDAC support tthayer
2016-03-31 18:48 ` [PATCHv2 1/7] EDAC, altera: New file operations for Arria10 ECC modules tthayer
2016-03-31 18:48 ` tthayer [this message]
2016-03-31 18:48 ` [PATCHv2 3/7] EDAC, altera: Make OCRAM ECC dependency check generic tthayer
2016-03-31 18:48 ` [PATCHv2 4/7] Documentation: dt: socfpga: Add Altera Arria10 OCRAM binding tthayer
2016-04-04 5:15 ` Rob Herring
[not found] ` <1459450087-24792-1-git-send-email-tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2016-03-31 18:48 ` [PATCHv2 5/7] EDAC, altera: Addition of Arria10 OCRAM ECC tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
2016-03-31 18:48 ` [PATCHv2 6/7] ARM: socfpga: Enable Arria10 OCRAM ECC on startup tthayer
2016-04-05 5:25 ` Thor Thayer
2016-04-05 5:31 ` Borislav Petkov
[not found] ` <20160405053110.GA17541-fF5Pk5pvG8Y@public.gmane.org>
2016-04-05 18:37 ` Dinh Nguyen
2016-04-05 20:15 ` Borislav Petkov
2016-04-07 0:36 ` Thor Thayer
[not found] ` <5705ABA1.4000308-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2016-04-07 11:10 ` Borislav Petkov
2016-03-31 18:48 ` [PATCHv2 7/7] ARM: dts: Add Altera Arria10 OCRAM EDAC devicetree entry tthayer
2016-04-05 18:44 ` Dinh Nguyen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1459450087-24792-3-git-send-email-tthayer@opensource.altera.com \
--to=tthayer@opensource.altera.com \
--cc=bp@alien8.de \
--cc=devicetree@vger.kernel.org \
--cc=dinguyen@opensource.altera.com \
--cc=dougthompson@xmission.com \
--cc=galak@codeaurora.org \
--cc=grant.likely@linaro.org \
--cc=ijc+devicetree@hellion.org.uk \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-edac@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@arm.linux.org.uk \
--cc=m.chehab@samsung.com \
--cc=mark.rutland@arm.com \
--cc=pawel.moll@arm.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).