[PATCH v4 0/7] da8xx USB PHY (was da8xx USB clocks)

[PATCH v4 0/7] da8xx USB PHY (was da8xx USB clocks)

[David Lechner]

The "da8xx USB clocks" patch series was growing a bit too big, so on the advice
of Sekhar Nori, I am splitting it into two parts. This part contains everything
in drivers/ and the other part will contain everything in arch/arm/mach-davinci.

This patch series will apply and build on its own. It just won't work at runtime
without the corresponding mach-davinci changes to provide clocks, etc.

This round just contains changes from feedback. See individual patches for
details.

Tested working on LEGO MINDSTORMS EV3 using linux-davinci/master branch.

David Lechner (7):
  mfd: da8xx-cfgchip: New header file for CFGCHIP registers.
  dt-bindings: Add bindings for phy-da8xx-usb
  phy: Add set_mode callback
  phy: da8xx-usb: new driver for DA8xx SoC USB PHY
  usb: ohci-da8xx: Remove code that references mach
  usb: musb: da8xx: Use devm in probe
  usb: musb: da8xx: Remove mach code

 .../devicetree/bindings/phy/phy-da8xx-usb.txt      |  40 ++++
 drivers/phy/Kconfig                                |  10 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-core.c                             |  15 ++
 drivers/phy/phy-da8xx-usb.c                        | 245 +++++++++++++++++++++
 drivers/usb/host/Kconfig                           |   1 +
 drivers/usb/host/ohci-da8xx.c                      | 102 +++++----
 drivers/usb/musb/Kconfig                           |   2 +-
 drivers/usb/musb/da8xx.c                           | 160 +++++---------
 include/linux/mfd/da8xx-cfgchip.h                  | 153 +++++++++++++
 include/linux/phy/phy.h                            |  15 ++
 include/linux/platform_data/usb-davinci.h          |  22 --
 12 files changed, 594 insertions(+), 172 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
 create mode 100644 drivers/phy/phy-da8xx-usb.c
 create mode 100644 include/linux/mfd/da8xx-cfgchip.h

-- 
1.9.1

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[PATCH v4 1/7] mfd: da8xx-cfgchip: New header file for CFGCHIP registers.

[David Lechner]

We will be using a generic syscon device for the TI DA8XX SoC CFGCHIPx
retisters. This will be used by a number of planned drivers including a
new USB PHY driver and common clock framework drivers.

The same defines are removed from the platform_data header file since they
are now redundant and they didn't really belong there anyway.

Signed-off-by: David Lechner <david@lechnology.com>
---

v4 changes:

* dropped individual CFGCHIPn_REG defines in favor of CFGCHIP(n)


 include/linux/mfd/da8xx-cfgchip.h         | 153 ++++++++++++++++++++++++++++++
 include/linux/platform_data/usb-davinci.h |  22 -----
 2 files changed, 153 insertions(+), 22 deletions(-)
 create mode 100644 include/linux/mfd/da8xx-cfgchip.h

diff --git a/include/linux/mfd/da8xx-cfgchip.h b/include/linux/mfd/da8xx-cfgchip.h
new file mode 100644
index 0000000..799e575
--- /dev/null
+++ b/include/linux/mfd/da8xx-cfgchip.h
@@ -0,0 +1,153 @@
+/*
+ * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
+ *
+ * Copyright (C) 2016 David Lechner <david@lechnology.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
+#define __LINUX_MFD_DA8XX_CFGCHIP_H
+
+#include <linux/bitops.h>
+
+/* register offset (32-bit registers) */
+#define CFGCHIP(n)				(n * 4)
+
+/* CFGCHIP0 (PLL0/EDMA3_0) register bits */
+#define CFGCHIP0_PLL_MASTER_LOCK		BIT(4)
+#define CFGCHIP0_EDMA30TC1DBS(n)		(n << 2)
+#define CFGCHIP0_EDMA30TC1DBS_MASK		CFGCHIP0_EDMA30TC1DBS(0x3)
+#define CFGCHIP0_EDMA30TC1DBS_16		CFGCHIP0_EDMA30TC1DBS(0x0)
+#define CFGCHIP0_EDMA30TC1DBS_32		CFGCHIP0_EDMA30TC1DBS(0x1)
+#define CFGCHIP0_EDMA30TC1DBS_64		CFGCHIP0_EDMA30TC1DBS(0x2)
+#define CFGCHIP0_EDMA30TC0DBS(n)		(n << 0)
+#define CFGCHIP0_EDMA30TC0DBS_MASK		CFGCHIP0_EDMA30TC0DBS(0x3)
+#define CFGCHIP0_EDMA30TC0DBS_16		CFGCHIP0_EDMA30TC0DBS(0x0)
+#define CFGCHIP0_EDMA30TC0DBS_32		CFGCHIP0_EDMA30TC0DBS(0x1)
+#define CFGCHIP0_EDMA30TC0DBS_64		CFGCHIP0_EDMA30TC0DBS(0x2)
+
+/* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
+#define CFGCHIP1_CAP2SRC(n)			(n << 27)
+#define CFGCHIP1_CAP2SRC_MASK			CFGCHIP1_CAP2SRC(0x1f)
+#define CFGCHIP1_CAP2SRC_ECAP_PIN		CFGCHIP1_CAP2SRC(0x0)
+#define CFGCHIP1_CAP2SRC_MCASP0_TX		CFGCHIP1_CAP2SRC(0x1)
+#define CFGCHIP1_CAP2SRC_MCASP0_RX		CFGCHIP1_CAP2SRC(0x2)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD	CFGCHIP1_CAP2SRC(0x7)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_RX		CFGCHIP1_CAP2SRC(0x8)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_TX		CFGCHIP1_CAP2SRC(0x9)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_MISC		CFGCHIP1_CAP2SRC(0xa)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD	CFGCHIP1_CAP2SRC(0xb)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_RX		CFGCHIP1_CAP2SRC(0xc)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_TX		CFGCHIP1_CAP2SRC(0xd)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_MISC		CFGCHIP1_CAP2SRC(0xe)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD	CFGCHIP1_CAP2SRC(0xf)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_RX		CFGCHIP1_CAP2SRC(0x10)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_TX		CFGCHIP1_CAP2SRC(0x11)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_MISC		CFGCHIP1_CAP2SRC(0x12)
+#define CFGCHIP1_CAP1SRC(n)			(n << 22)
+#define CFGCHIP1_CAP1SRC_MASK			CFGCHIP1_CAP1SRC(0x1f)
+#define CFGCHIP1_CAP1SRC_ECAP_PIN		CFGCHIP1_CAP1SRC(0x0)
+#define CFGCHIP1_CAP1SRC_MCASP0_TX		CFGCHIP1_CAP1SRC(0x1)
+#define CFGCHIP1_CAP1SRC_MCASP0_RX		CFGCHIP1_CAP1SRC(0x2)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD	CFGCHIP1_CAP1SRC(0x7)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_RX		CFGCHIP1_CAP1SRC(0x8)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_TX		CFGCHIP1_CAP1SRC(0x9)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_MISC		CFGCHIP1_CAP1SRC(0xa)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD	CFGCHIP1_CAP1SRC(0xb)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_RX		CFGCHIP1_CAP1SRC(0xc)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_TX		CFGCHIP1_CAP1SRC(0xd)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_MISC		CFGCHIP1_CAP1SRC(0xe)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD	CFGCHIP1_CAP1SRC(0xf)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_RX		CFGCHIP1_CAP1SRC(0x10)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_TX		CFGCHIP1_CAP1SRC(0x11)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_MISC		CFGCHIP1_CAP1SRC(0x12)
+#define CFGCHIP1_CAP0SRC(n)			(n << 17)
+#define CFGCHIP1_CAP0SRC_MASK			CFGCHIP1_CAP0SRC(0x1f)
+#define CFGCHIP1_CAP0SRC_ECAP_PIN		CFGCHIP1_CAP0SRC(0x0)
+#define CFGCHIP1_CAP0SRC_MCASP0_TX		CFGCHIP1_CAP0SRC(0x1)
+#define CFGCHIP1_CAP0SRC_MCASP0_RX		CFGCHIP1_CAP0SRC(0x2)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD	CFGCHIP1_CAP0SRC(0x7)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_RX		CFGCHIP1_CAP0SRC(0x8)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_TX		CFGCHIP1_CAP0SRC(0x9)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_MISC		CFGCHIP1_CAP0SRC(0xa)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD	CFGCHIP1_CAP0SRC(0xb)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_RX		CFGCHIP1_CAP0SRC(0xc)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_TX		CFGCHIP1_CAP0SRC(0xd)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_MISC		CFGCHIP1_CAP0SRC(0xe)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD	CFGCHIP1_CAP0SRC(0xf)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_RX		CFGCHIP1_CAP0SRC(0x10)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_TX		CFGCHIP1_CAP0SRC(0x11)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_MISC		CFGCHIP1_CAP0SRC(0x12)
+#define CFGCHIP1_HPIBYTEAD			BIT(16)
+#define CFGCHIP1_HPIENA				BIT(15)
+#define CFGCHIP0_EDMA31TC0DBS(n)		(n << 13)
+#define CFGCHIP0_EDMA31TC0DBS_MASK		CFGCHIP0_EDMA31TC0DBS(0x3)
+#define CFGCHIP0_EDMA31TC0DBS_16		CFGCHIP0_EDMA31TC0DBS(0x0)
+#define CFGCHIP0_EDMA31TC0DBS_32		CFGCHIP0_EDMA31TC0DBS(0x1)
+#define CFGCHIP0_EDMA31TC0DBS_64		CFGCHIP0_EDMA31TC0DBS(0x2)
+#define CFGCHIP1_TBCLKSYNC			BIT(12)
+#define CFGCHIP1_AMUTESEL0(n)			(n << 0)
+#define CFGCHIP1_AMUTESEL0_MASK			CFGCHIP1_AMUTESEL0(0xf)
+#define CFGCHIP1_AMUTESEL0_LOW			CFGCHIP1_AMUTESEL0(0x0)
+#define CFGCHIP1_AMUTESEL0_BANK_0		CFGCHIP1_AMUTESEL0(0x1)
+#define CFGCHIP1_AMUTESEL0_BANK_1		CFGCHIP1_AMUTESEL0(0x2)
+#define CFGCHIP1_AMUTESEL0_BANK_2		CFGCHIP1_AMUTESEL0(0x3)
+#define CFGCHIP1_AMUTESEL0_BANK_3		CFGCHIP1_AMUTESEL0(0x4)
+#define CFGCHIP1_AMUTESEL0_BANK_4		CFGCHIP1_AMUTESEL0(0x5)
+#define CFGCHIP1_AMUTESEL0_BANK_5		CFGCHIP1_AMUTESEL0(0x6)
+#define CFGCHIP1_AMUTESEL0_BANK_6		CFGCHIP1_AMUTESEL0(0x7)
+#define CFGCHIP1_AMUTESEL0_BANK_7		CFGCHIP1_AMUTESEL0(0x8)
+
+/* CFGCHIP2 (USB PHY) register bits */
+#define CFGCHIP2_PHYCLKGD			BIT(17)
+#define CFGCHIP2_VBUSSENSE			BIT(16)
+#define CFGCHIP2_RESET				BIT(15)
+#define CFGCHIP2_OTGMODE(n)			(n << 13)
+#define CFGCHIP2_OTGMODE_MASK			CFGCHIP2_OTGMODE(0x3)
+#define CFGCHIP2_OTGMODE_NO_OVERRIDE		CFGCHIP2_OTGMODE(0x0)
+#define CFGCHIP2_OTGMODE_FORCE_HOST		CFGCHIP2_OTGMODE(0x1)
+#define CFGCHIP2_OTGMODE_FORCE_DEVICE		CFGCHIP2_OTGMODE(0x2)
+#define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW	CFGCHIP2_OTGMODE(0x3)
+#define CFGCHIP2_USB1PHYCLKMUX			BIT(12)
+#define CFGCHIP2_USB2PHYCLKMUX			BIT(11)
+#define CFGCHIP2_PHYPWRDN			BIT(10)
+#define CFGCHIP2_OTGPWRDN			BIT(9)
+#define CFGCHIP2_DATPOL				BIT(8)
+#define CFGCHIP2_USB1SUSPENDM			BIT(7)
+#define CFGCHIP2_PHY_PLLON			BIT(6)
+#define CFGCHIP2_SESENDEN			BIT(5)
+#define CFGCHIP2_VBDTCTEN			BIT(4)
+#define CFGCHIP2_REFFREQ(n)			(n << 0)
+#define CFGCHIP2_REFFREQ_MASK			CFGCHIP2_REFFREQ(0xf)
+#define CFGCHIP2_REFFREQ_12MHZ			CFGCHIP2_REFFREQ(0x1)
+#define CFGCHIP2_REFFREQ_24MHZ			CFGCHIP2_REFFREQ(0x2)
+#define CFGCHIP2_REFFREQ_48MHZ			CFGCHIP2_REFFREQ(0x3)
+#define CFGCHIP2_REFFREQ_19_2MHZ		CFGCHIP2_REFFREQ(0x4)
+#define CFGCHIP2_REFFREQ_38_4MHZ		CFGCHIP2_REFFREQ(0x5)
+#define CFGCHIP2_REFFREQ_13MHZ			CFGCHIP2_REFFREQ(0x6)
+#define CFGCHIP2_REFFREQ_26MHZ			CFGCHIP2_REFFREQ(0x7)
+#define CFGCHIP2_REFFREQ_20MHZ			CFGCHIP2_REFFREQ(0x8)
+#define CFGCHIP2_REFFREQ_40MHZ			CFGCHIP2_REFFREQ(0x9)
+
+/* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
+#define CFGCHIP3_RMII_SEL			BIT(8)
+#define CFGCHIP3_UPP_TX_CLKSRC			BIT(6)
+#define CFGCHIP3_PLL1_MASTER_LOCK		BIT(5)
+#define CFGCHIP3_ASYNC3_CLKSRC			BIT(4)
+#define CFGCHIP3_PRUEVTSEL			BIT(3)
+#define CFGCHIP3_DIV45PENA			BIT(2)
+#define CFGCHIP3_EMA_CLKSRC			BIT(1)
+
+/* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
+#define CFGCHIP4_AMUTECLR0			BIT(0)
+
+#endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */
diff --git a/include/linux/platform_data/usb-davinci.h b/include/linux/platform_data/usb-davinci.h
index e0bc4ab..629b703 100644
--- a/include/linux/platform_data/usb-davinci.h
+++ b/include/linux/platform_data/usb-davinci.h
@@ -11,28 +11,6 @@
 #ifndef __ASM_ARCH_USB_H
 #define __ASM_ARCH_USB_H
 
-/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
-#define CFGCHIP2_PHYCLKGD	(1 << 17)
-#define CFGCHIP2_VBUSSENSE	(1 << 16)
-#define CFGCHIP2_RESET		(1 << 15)
-#define CFGCHIP2_OTGMODE	(3 << 13)
-#define CFGCHIP2_NO_OVERRIDE	(0 << 13)
-#define CFGCHIP2_FORCE_HOST	(1 << 13)
-#define CFGCHIP2_FORCE_DEVICE 	(2 << 13)
-#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
-#define CFGCHIP2_USB1PHYCLKMUX	(1 << 12)
-#define CFGCHIP2_USB2PHYCLKMUX	(1 << 11)
-#define CFGCHIP2_PHYPWRDN	(1 << 10)
-#define CFGCHIP2_OTGPWRDN	(1 << 9)
-#define CFGCHIP2_DATPOL 	(1 << 8)
-#define CFGCHIP2_USB1SUSPENDM	(1 << 7)
-#define CFGCHIP2_PHY_PLLON	(1 << 6)	/* override PLL suspend */
-#define CFGCHIP2_SESENDEN	(1 << 5)	/* Vsess_end comparator */
-#define CFGCHIP2_VBDTCTEN	(1 << 4)	/* Vbus comparator */
-#define CFGCHIP2_REFFREQ	(0xf << 0)
-#define CFGCHIP2_REFFREQ_12MHZ	(1 << 0)
-#define CFGCHIP2_REFFREQ_24MHZ	(2 << 0)
-#define CFGCHIP2_REFFREQ_48MHZ	(3 << 0)
 
 struct	da8xx_ohci_root_hub;
 
-- 
1.9.1

Re: [PATCH v4 1/7] mfd: da8xx-cfgchip: New header file for CFGCHIP registers.

[Lee Jones]

On Thu, 14 Apr 2016, David Lechner wrote:

> We will be using a generic syscon device for the TI DA8XX SoC CFGCHIPx
> retisters. This will be used by a number of planned drivers including a
> new USB PHY driver and common clock framework drivers.
> 
> The same defines are removed from the platform_data header file since they
> are now redundant and they didn't really belong there anyway.
> 
> Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
> ---
> 
> v4 changes:
> 
> * dropped individual CFGCHIPn_REG defines in favor of CFGCHIP(n)
> 
> 
>  include/linux/mfd/da8xx-cfgchip.h         | 153 ++++++++++++++++++++++++++++++
>  include/linux/platform_data/usb-davinci.h |  22 -----

Works for me.

Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Since this is a new file, I'm happy for it to be taken in via another
tree.

>  2 files changed, 153 insertions(+), 22 deletions(-)
>  create mode 100644 include/linux/mfd/da8xx-cfgchip.h
> 
> diff --git a/include/linux/mfd/da8xx-cfgchip.h b/include/linux/mfd/da8xx-cfgchip.h
> new file mode 100644
> index 0000000..799e575
> --- /dev/null
> +++ b/include/linux/mfd/da8xx-cfgchip.h
> @@ -0,0 +1,153 @@
> +/*
> + * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
> + *
> + * Copyright (C) 2016 David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
> +#define __LINUX_MFD_DA8XX_CFGCHIP_H
> +
> +#include <linux/bitops.h>
> +
> +/* register offset (32-bit registers) */
> +#define CFGCHIP(n)				(n * 4)
> +
> +/* CFGCHIP0 (PLL0/EDMA3_0) register bits */
> +#define CFGCHIP0_PLL_MASTER_LOCK		BIT(4)
> +#define CFGCHIP0_EDMA30TC1DBS(n)		(n << 2)
> +#define CFGCHIP0_EDMA30TC1DBS_MASK		CFGCHIP0_EDMA30TC1DBS(0x3)
> +#define CFGCHIP0_EDMA30TC1DBS_16		CFGCHIP0_EDMA30TC1DBS(0x0)
> +#define CFGCHIP0_EDMA30TC1DBS_32		CFGCHIP0_EDMA30TC1DBS(0x1)
> +#define CFGCHIP0_EDMA30TC1DBS_64		CFGCHIP0_EDMA30TC1DBS(0x2)
> +#define CFGCHIP0_EDMA30TC0DBS(n)		(n << 0)
> +#define CFGCHIP0_EDMA30TC0DBS_MASK		CFGCHIP0_EDMA30TC0DBS(0x3)
> +#define CFGCHIP0_EDMA30TC0DBS_16		CFGCHIP0_EDMA30TC0DBS(0x0)
> +#define CFGCHIP0_EDMA30TC0DBS_32		CFGCHIP0_EDMA30TC0DBS(0x1)
> +#define CFGCHIP0_EDMA30TC0DBS_64		CFGCHIP0_EDMA30TC0DBS(0x2)
> +
> +/* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
> +#define CFGCHIP1_CAP2SRC(n)			(n << 27)
> +#define CFGCHIP1_CAP2SRC_MASK			CFGCHIP1_CAP2SRC(0x1f)
> +#define CFGCHIP1_CAP2SRC_ECAP_PIN		CFGCHIP1_CAP2SRC(0x0)
> +#define CFGCHIP1_CAP2SRC_MCASP0_TX		CFGCHIP1_CAP2SRC(0x1)
> +#define CFGCHIP1_CAP2SRC_MCASP0_RX		CFGCHIP1_CAP2SRC(0x2)
> +#define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD	CFGCHIP1_CAP2SRC(0x7)
> +#define CFGCHIP1_CAP2SRC_EMAC_C0_RX		CFGCHIP1_CAP2SRC(0x8)
> +#define CFGCHIP1_CAP2SRC_EMAC_C0_TX		CFGCHIP1_CAP2SRC(0x9)
> +#define CFGCHIP1_CAP2SRC_EMAC_C0_MISC		CFGCHIP1_CAP2SRC(0xa)
> +#define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD	CFGCHIP1_CAP2SRC(0xb)
> +#define CFGCHIP1_CAP2SRC_EMAC_C1_RX		CFGCHIP1_CAP2SRC(0xc)
> +#define CFGCHIP1_CAP2SRC_EMAC_C1_TX		CFGCHIP1_CAP2SRC(0xd)
> +#define CFGCHIP1_CAP2SRC_EMAC_C1_MISC		CFGCHIP1_CAP2SRC(0xe)
> +#define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD	CFGCHIP1_CAP2SRC(0xf)
> +#define CFGCHIP1_CAP2SRC_EMAC_C2_RX		CFGCHIP1_CAP2SRC(0x10)
> +#define CFGCHIP1_CAP2SRC_EMAC_C2_TX		CFGCHIP1_CAP2SRC(0x11)
> +#define CFGCHIP1_CAP2SRC_EMAC_C2_MISC		CFGCHIP1_CAP2SRC(0x12)
> +#define CFGCHIP1_CAP1SRC(n)			(n << 22)
> +#define CFGCHIP1_CAP1SRC_MASK			CFGCHIP1_CAP1SRC(0x1f)
> +#define CFGCHIP1_CAP1SRC_ECAP_PIN		CFGCHIP1_CAP1SRC(0x0)
> +#define CFGCHIP1_CAP1SRC_MCASP0_TX		CFGCHIP1_CAP1SRC(0x1)
> +#define CFGCHIP1_CAP1SRC_MCASP0_RX		CFGCHIP1_CAP1SRC(0x2)
> +#define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD	CFGCHIP1_CAP1SRC(0x7)
> +#define CFGCHIP1_CAP1SRC_EMAC_C0_RX		CFGCHIP1_CAP1SRC(0x8)
> +#define CFGCHIP1_CAP1SRC_EMAC_C0_TX		CFGCHIP1_CAP1SRC(0x9)
> +#define CFGCHIP1_CAP1SRC_EMAC_C0_MISC		CFGCHIP1_CAP1SRC(0xa)
> +#define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD	CFGCHIP1_CAP1SRC(0xb)
> +#define CFGCHIP1_CAP1SRC_EMAC_C1_RX		CFGCHIP1_CAP1SRC(0xc)
> +#define CFGCHIP1_CAP1SRC_EMAC_C1_TX		CFGCHIP1_CAP1SRC(0xd)
> +#define CFGCHIP1_CAP1SRC_EMAC_C1_MISC		CFGCHIP1_CAP1SRC(0xe)
> +#define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD	CFGCHIP1_CAP1SRC(0xf)
> +#define CFGCHIP1_CAP1SRC_EMAC_C2_RX		CFGCHIP1_CAP1SRC(0x10)
> +#define CFGCHIP1_CAP1SRC_EMAC_C2_TX		CFGCHIP1_CAP1SRC(0x11)
> +#define CFGCHIP1_CAP1SRC_EMAC_C2_MISC		CFGCHIP1_CAP1SRC(0x12)
> +#define CFGCHIP1_CAP0SRC(n)			(n << 17)
> +#define CFGCHIP1_CAP0SRC_MASK			CFGCHIP1_CAP0SRC(0x1f)
> +#define CFGCHIP1_CAP0SRC_ECAP_PIN		CFGCHIP1_CAP0SRC(0x0)
> +#define CFGCHIP1_CAP0SRC_MCASP0_TX		CFGCHIP1_CAP0SRC(0x1)
> +#define CFGCHIP1_CAP0SRC_MCASP0_RX		CFGCHIP1_CAP0SRC(0x2)
> +#define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD	CFGCHIP1_CAP0SRC(0x7)
> +#define CFGCHIP1_CAP0SRC_EMAC_C0_RX		CFGCHIP1_CAP0SRC(0x8)
> +#define CFGCHIP1_CAP0SRC_EMAC_C0_TX		CFGCHIP1_CAP0SRC(0x9)
> +#define CFGCHIP1_CAP0SRC_EMAC_C0_MISC		CFGCHIP1_CAP0SRC(0xa)
> +#define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD	CFGCHIP1_CAP0SRC(0xb)
> +#define CFGCHIP1_CAP0SRC_EMAC_C1_RX		CFGCHIP1_CAP0SRC(0xc)
> +#define CFGCHIP1_CAP0SRC_EMAC_C1_TX		CFGCHIP1_CAP0SRC(0xd)
> +#define CFGCHIP1_CAP0SRC_EMAC_C1_MISC		CFGCHIP1_CAP0SRC(0xe)
> +#define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD	CFGCHIP1_CAP0SRC(0xf)
> +#define CFGCHIP1_CAP0SRC_EMAC_C2_RX		CFGCHIP1_CAP0SRC(0x10)
> +#define CFGCHIP1_CAP0SRC_EMAC_C2_TX		CFGCHIP1_CAP0SRC(0x11)
> +#define CFGCHIP1_CAP0SRC_EMAC_C2_MISC		CFGCHIP1_CAP0SRC(0x12)
> +#define CFGCHIP1_HPIBYTEAD			BIT(16)
> +#define CFGCHIP1_HPIENA				BIT(15)
> +#define CFGCHIP0_EDMA31TC0DBS(n)		(n << 13)
> +#define CFGCHIP0_EDMA31TC0DBS_MASK		CFGCHIP0_EDMA31TC0DBS(0x3)
> +#define CFGCHIP0_EDMA31TC0DBS_16		CFGCHIP0_EDMA31TC0DBS(0x0)
> +#define CFGCHIP0_EDMA31TC0DBS_32		CFGCHIP0_EDMA31TC0DBS(0x1)
> +#define CFGCHIP0_EDMA31TC0DBS_64		CFGCHIP0_EDMA31TC0DBS(0x2)
> +#define CFGCHIP1_TBCLKSYNC			BIT(12)
> +#define CFGCHIP1_AMUTESEL0(n)			(n << 0)
> +#define CFGCHIP1_AMUTESEL0_MASK			CFGCHIP1_AMUTESEL0(0xf)
> +#define CFGCHIP1_AMUTESEL0_LOW			CFGCHIP1_AMUTESEL0(0x0)
> +#define CFGCHIP1_AMUTESEL0_BANK_0		CFGCHIP1_AMUTESEL0(0x1)
> +#define CFGCHIP1_AMUTESEL0_BANK_1		CFGCHIP1_AMUTESEL0(0x2)
> +#define CFGCHIP1_AMUTESEL0_BANK_2		CFGCHIP1_AMUTESEL0(0x3)
> +#define CFGCHIP1_AMUTESEL0_BANK_3		CFGCHIP1_AMUTESEL0(0x4)
> +#define CFGCHIP1_AMUTESEL0_BANK_4		CFGCHIP1_AMUTESEL0(0x5)
> +#define CFGCHIP1_AMUTESEL0_BANK_5		CFGCHIP1_AMUTESEL0(0x6)
> +#define CFGCHIP1_AMUTESEL0_BANK_6		CFGCHIP1_AMUTESEL0(0x7)
> +#define CFGCHIP1_AMUTESEL0_BANK_7		CFGCHIP1_AMUTESEL0(0x8)
> +
> +/* CFGCHIP2 (USB PHY) register bits */
> +#define CFGCHIP2_PHYCLKGD			BIT(17)
> +#define CFGCHIP2_VBUSSENSE			BIT(16)
> +#define CFGCHIP2_RESET				BIT(15)
> +#define CFGCHIP2_OTGMODE(n)			(n << 13)
> +#define CFGCHIP2_OTGMODE_MASK			CFGCHIP2_OTGMODE(0x3)
> +#define CFGCHIP2_OTGMODE_NO_OVERRIDE		CFGCHIP2_OTGMODE(0x0)
> +#define CFGCHIP2_OTGMODE_FORCE_HOST		CFGCHIP2_OTGMODE(0x1)
> +#define CFGCHIP2_OTGMODE_FORCE_DEVICE		CFGCHIP2_OTGMODE(0x2)
> +#define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW	CFGCHIP2_OTGMODE(0x3)
> +#define CFGCHIP2_USB1PHYCLKMUX			BIT(12)
> +#define CFGCHIP2_USB2PHYCLKMUX			BIT(11)
> +#define CFGCHIP2_PHYPWRDN			BIT(10)
> +#define CFGCHIP2_OTGPWRDN			BIT(9)
> +#define CFGCHIP2_DATPOL				BIT(8)
> +#define CFGCHIP2_USB1SUSPENDM			BIT(7)
> +#define CFGCHIP2_PHY_PLLON			BIT(6)
> +#define CFGCHIP2_SESENDEN			BIT(5)
> +#define CFGCHIP2_VBDTCTEN			BIT(4)
> +#define CFGCHIP2_REFFREQ(n)			(n << 0)
> +#define CFGCHIP2_REFFREQ_MASK			CFGCHIP2_REFFREQ(0xf)
> +#define CFGCHIP2_REFFREQ_12MHZ			CFGCHIP2_REFFREQ(0x1)
> +#define CFGCHIP2_REFFREQ_24MHZ			CFGCHIP2_REFFREQ(0x2)
> +#define CFGCHIP2_REFFREQ_48MHZ			CFGCHIP2_REFFREQ(0x3)
> +#define CFGCHIP2_REFFREQ_19_2MHZ		CFGCHIP2_REFFREQ(0x4)
> +#define CFGCHIP2_REFFREQ_38_4MHZ		CFGCHIP2_REFFREQ(0x5)
> +#define CFGCHIP2_REFFREQ_13MHZ			CFGCHIP2_REFFREQ(0x6)
> +#define CFGCHIP2_REFFREQ_26MHZ			CFGCHIP2_REFFREQ(0x7)
> +#define CFGCHIP2_REFFREQ_20MHZ			CFGCHIP2_REFFREQ(0x8)
> +#define CFGCHIP2_REFFREQ_40MHZ			CFGCHIP2_REFFREQ(0x9)
> +
> +/* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
> +#define CFGCHIP3_RMII_SEL			BIT(8)
> +#define CFGCHIP3_UPP_TX_CLKSRC			BIT(6)
> +#define CFGCHIP3_PLL1_MASTER_LOCK		BIT(5)
> +#define CFGCHIP3_ASYNC3_CLKSRC			BIT(4)
> +#define CFGCHIP3_PRUEVTSEL			BIT(3)
> +#define CFGCHIP3_DIV45PENA			BIT(2)
> +#define CFGCHIP3_EMA_CLKSRC			BIT(1)
> +
> +/* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
> +#define CFGCHIP4_AMUTECLR0			BIT(0)
> +
> +#endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */
> diff --git a/include/linux/platform_data/usb-davinci.h b/include/linux/platform_data/usb-davinci.h
> index e0bc4ab..629b703 100644
> --- a/include/linux/platform_data/usb-davinci.h
> +++ b/include/linux/platform_data/usb-davinci.h
> @@ -11,28 +11,6 @@
>  #ifndef __ASM_ARCH_USB_H
>  #define __ASM_ARCH_USB_H
>  
> -/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
> -#define CFGCHIP2_PHYCLKGD	(1 << 17)
> -#define CFGCHIP2_VBUSSENSE	(1 << 16)
> -#define CFGCHIP2_RESET		(1 << 15)
> -#define CFGCHIP2_OTGMODE	(3 << 13)
> -#define CFGCHIP2_NO_OVERRIDE	(0 << 13)
> -#define CFGCHIP2_FORCE_HOST	(1 << 13)
> -#define CFGCHIP2_FORCE_DEVICE 	(2 << 13)
> -#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
> -#define CFGCHIP2_USB1PHYCLKMUX	(1 << 12)
> -#define CFGCHIP2_USB2PHYCLKMUX	(1 << 11)
> -#define CFGCHIP2_PHYPWRDN	(1 << 10)
> -#define CFGCHIP2_OTGPWRDN	(1 << 9)
> -#define CFGCHIP2_DATPOL 	(1 << 8)
> -#define CFGCHIP2_USB1SUSPENDM	(1 << 7)
> -#define CFGCHIP2_PHY_PLLON	(1 << 6)	/* override PLL suspend */
> -#define CFGCHIP2_SESENDEN	(1 << 5)	/* Vsess_end comparator */
> -#define CFGCHIP2_VBDTCTEN	(1 << 4)	/* Vbus comparator */
> -#define CFGCHIP2_REFFREQ	(0xf << 0)
> -#define CFGCHIP2_REFFREQ_12MHZ	(1 << 0)
> -#define CFGCHIP2_REFFREQ_24MHZ	(2 << 0)
> -#define CFGCHIP2_REFFREQ_48MHZ	(3 << 0)
>  
>  struct	da8xx_ohci_root_hub;
>  

-- 
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Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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[PATCH v4 2/7] dt-bindings: Add bindings for phy-da8xx-usb

[David Lechner]

Device tree binding for new phy-da8xx-usb driver.

Signed-off-by: David Lechner <david@lechnology.com>
Acked-by: Rob Herring <robh@kernel.org>
---

v4 changes:

* swapped order of usb20 and usb11 to be in logical order of reg address.

 .../devicetree/bindings/phy/phy-da8xx-usb.txt      | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
new file mode 100644
index 0000000..bead185
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
@@ -0,0 +1,40 @@
+TI DaVinci DA8xx USB PHY
+
+Required properties:
+ - compatible: must be "ti,da830-usbphy".
+ - #phy-cells: must be 1.
+
+This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
+controllers on DA8xx SoCs. Consumers of this device should use index 0 for
+the USB 2.0 phy device and index 1 for the USB 1.1 phy device.
+
+It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
+to access the CFGCHIP2 register.
+
+Example:
+
+	cfgchip: cfgchip@1417c {
+		compatible = "ti,da830-cfgchip", "syscon";
+		reg = <0x1417c 0x14>;
+	};
+
+	usbphy: usbphy {
+		compatible = "ti,da830-usbphy";
+		#phy-cells = <1>;
+	};
+
+	usb20: usb@200000 {
+		compatible = "ti,da830-musb";
+		reg = <0x200000 0x1000>;
+		interrupts = <58>;
+		phys = <&usbphy 0>;
+		phy-names = "usbphy";
+	};
+
+	usb11: usb@225000 {
+		compatible = "ti,da830-ohci";
+		reg = <0x225000 0x1000>;
+		interrupts = <59>;
+		phys = <&usbphy 1>;
+		phy-names = "usbphy";
+	};
-- 
1.9.1

Re: [PATCH v4 2/7] dt-bindings: Add bindings for phy-da8xx-usb

[Sergei Shtylyov]

Hello.

On 4/14/2016 9:35 PM, David Lechner wrote:

> Device tree binding for new phy-da8xx-usb driver.
>
> Signed-off-by: David Lechner <david@lechnology.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>
> v4 changes:
>
> * swapped order of usb20 and usb11 to be in logical order of reg address.
>
>   .../devicetree/bindings/phy/phy-da8xx-usb.txt      | 40 ++++++++++++++++++++++
>   1 file changed, 40 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
> new file mode 100644
> index 0000000..bead185
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
> @@ -0,0 +1,40 @@
> +TI DaVinci DA8xx USB PHY

    DA8xx is not DaVinci, please omit this.

> +
> +Required properties:
> + - compatible: must be "ti,da830-usbphy".
> + - #phy-cells: must be 1.
> +
> +This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
> +controllers on DA8xx SoCs. Consumers of this device should use index 0 for
> +the USB 2.0 phy device and index 1 for the USB 1.1 phy device.

    Not indices 2 and 1 already?

> +It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
> +to access the CFGCHIP2 register.
> +
> +Example:
> +
> +	cfgchip: cfgchip@1417c {
> +		compatible = "ti,da830-cfgchip", "syscon";
> +		reg = <0x1417c 0x14>;
> +	};
> +
> +	usbphy: usbphy {

    Name it "usb-phy" please, consistent to what ePAPR has mandated for 
Ethernet PHYs.

[...]

MBR, Sergei

Re: [PATCH v4 2/7] dt-bindings: Add bindings for phy-da8xx-usb

[David Lechner]

On 04/15/2016 05:48 AM, Sergei Shtylyov wrote:
> On 4/14/2016 9:35 PM, David Lechner wrote:
>
>> Device tree binding for new phy-da8xx-usb driver.
>>
>> Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
>> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> ---
>>
>> v4 changes:
>>
>> * swapped order of usb20 and usb11 to be in logical order of reg address.
>>
>>   .../devicetree/bindings/phy/phy-da8xx-usb.txt      | 40
>> ++++++++++++++++++++++
>>   1 file changed, 40 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
>> b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
>> new file mode 100644
>> index 0000000..bead185
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
>> @@ -0,0 +1,40 @@
>> +TI DaVinci DA8xx USB PHY
>
>     DA8xx is not DaVinci, please omit this.

Just to be sure, you mean omit "DaVinci"?

>
>> +
>> +Required properties:
>> + - compatible: must be "ti,da830-usbphy".
>> + - #phy-cells: must be 1.
>> +
>> +This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
>> +controllers on DA8xx SoCs. Consumers of this device should use index
>> 0 for
>> +the USB 2.0 phy device and index 1 for the USB 1.1 phy device.
>
>     Not indices 2 and 1 already?

I changed this to reflect the TRM. USB0PHY = USB 2.0 and USB1PHY = USB 1.1

>
>> +    usbphy: usbphy {
>
>     Name it "usb-phy" please, consistent to what ePAPR has mandated for
> Ethernet PHYs.

Ack.

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Re: [PATCH v4 2/7] dt-bindings: Add bindings for phy-da8xx-usb

[Sergei Shtylyov]

On 04/15/2016 07:13 PM, David Lechner wrote:

>>> Device tree binding for new phy-da8xx-usb driver.
>>>
>>> Signed-off-by: David Lechner <david@lechnology.com>
>>> Acked-by: Rob Herring <robh@kernel.org>
>>> ---
>>>
>>> v4 changes:
>>>
>>> * swapped order of usb20 and usb11 to be in logical order of reg address.
>>>
>>>   .../devicetree/bindings/phy/phy-da8xx-usb.txt      | 40
>>> ++++++++++++++++++++++
>>>   1 file changed, 40 insertions(+)
>>>   create mode 100644
>>> Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
>>> b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
>>> new file mode 100644
>>> index 0000000..bead185
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
>>> @@ -0,0 +1,40 @@
>>> +TI DaVinci DA8xx USB PHY
>>
>>     DA8xx is not DaVinci, please omit this.
>
> Just to be sure, you mean omit "DaVinci"?

    Exactly. It would be better to mention OMAP-L1x instead.

MBR, Sergei

[PATCH v4 3/7] phy: Add set_mode callback

[David Lechner]

The initial use for this is for PHYs that have a mode related to USB OTG.
There are several SoCs (e.g. TI OMAP and DA8xx) that have a mode setting
in the USB PHY to override OTG VBUS and ID signals.

Of course, the enum can be expaned in the future to include modes for
other types of PHYs as well.

Suggested-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: David Lechner <david@lechnology.com>
---

v4 changes:

* This is a new patch to avoid exporting a symbol from the phy-da8xx-usb driver.


 drivers/phy/phy-core.c  | 15 +++++++++++++++
 include/linux/phy/phy.h | 15 +++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index e7e574d..fe0344c 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -342,6 +342,21 @@ int phy_power_off(struct phy *phy)
 }
 EXPORT_SYMBOL_GPL(phy_power_off);
 
+int phy_set_mode(struct phy *phy, enum phy_mode mode)
+{
+	int ret;
+
+	if (!phy || !phy->ops->set_mode)
+		return 0;
+
+	mutex_lock(&phy->mutex);
+	ret = phy->ops->set_mode(phy, mode);
+	mutex_unlock(&phy->mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(phy_set_mode);
+
 /**
  * _of_phy_get() - lookup and obtain a reference to a phy by phandle
  * @np: device_node for which to get the phy
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 8cf05e3..d66f4d9 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -22,12 +22,20 @@
 
 struct phy;
 
+enum phy_mode {
+	PHY_MODE_INVALID,
+	PHY_MODE_USB_HOST,
+	PHY_MODE_USB_DEVICE,
+	PHY_MODE_USB_OTG,
+};
+
 /**
  * struct phy_ops - set of function pointers for performing phy operations
  * @init: operation to be performed for initializing phy
  * @exit: operation to be performed while exiting
  * @power_on: powering on the phy
  * @power_off: powering off the phy
+ * @set_mode: set the mode of the phy
  * @owner: the module owner containing the ops
  */
 struct phy_ops {
@@ -35,6 +43,7 @@ struct phy_ops {
 	int	(*exit)(struct phy *phy);
 	int	(*power_on)(struct phy *phy);
 	int	(*power_off)(struct phy *phy);
+	int	(*set_mode)(struct phy *phy, enum phy_mode mode);
 	struct module *owner;
 };
 
@@ -119,6 +128,7 @@ int phy_init(struct phy *phy);
 int phy_exit(struct phy *phy);
 int phy_power_on(struct phy *phy);
 int phy_power_off(struct phy *phy);
+int phy_set_mode(struct phy *phy, enum phy_mode mode);
 static inline int phy_get_bus_width(struct phy *phy)
 {
 	return phy->attrs.bus_width;
@@ -224,6 +234,13 @@ static inline int phy_power_off(struct phy *phy)
    return -ENOSYS;
 }
 
+static inline int phy_set_mode(struct phy *phy, enum phy_mode mode)
+{
+	if (!phy)
+		return 0;
+	return -ENOSYS;
+}
+
 static inline int phy_get_bus_width(struct phy *phy)
 {
    return -ENOSYS;
-- 
1.9.1

Re: [PATCH v4 3/7] phy: Add set_mode callback

[Bin Liu]

Hi,

On Thu, Apr 14, 2016 at 01:35:14PM -0500, David Lechner wrote:
> The initial use for this is for PHYs that have a mode related to USB OTG.
> There are several SoCs (e.g. TI OMAP and DA8xx) that have a mode setting
> in the USB PHY to override OTG VBUS and ID signals.
> 
> Of course, the enum can be expaned in the future to include modes for
> other types of PHYs as well.
> 
> Suggested-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
> Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
> ---
> 
> v4 changes:
> 
> * This is a new patch to avoid exporting a symbol from the phy-da8xx-usb driver.
> 
> 
>  drivers/phy/phy-core.c  | 15 +++++++++++++++
>  include/linux/phy/phy.h | 15 +++++++++++++++
>  2 files changed, 30 insertions(+)
> 
> diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> index e7e574d..fe0344c 100644
> --- a/drivers/phy/phy-core.c
> +++ b/drivers/phy/phy-core.c
> @@ -342,6 +342,21 @@ int phy_power_off(struct phy *phy)
>  }
>  EXPORT_SYMBOL_GPL(phy_power_off);
>  
> +int phy_set_mode(struct phy *phy, enum phy_mode mode)
> +{
> +	int ret;
> +
> +	if (!phy || !phy->ops->set_mode)
> +		return 0;
> +
> +	mutex_lock(&phy->mutex);
> +	ret = phy->ops->set_mode(phy, mode);
> +	mutex_unlock(&phy->mutex);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(phy_set_mode);

Sorry for my late comments, have been busy on other things.

As I commented in v2, isn't it a better idea to not adding this callback
and let the da8xx phy driver set the mode register in _probe() based on
DT dr_mode?

musb core only calls the *optional* _set_mode() during init, so I don't
see any problem if the phy set the mode in its probe. 

Regards,
-Bin.

> +
>  /**
>   * _of_phy_get() - lookup and obtain a reference to a phy by phandle
>   * @np: device_node for which to get the phy
> diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> index 8cf05e3..d66f4d9 100644
> --- a/include/linux/phy/phy.h
> +++ b/include/linux/phy/phy.h
> @@ -22,12 +22,20 @@
>  
>  struct phy;
>  
> +enum phy_mode {
> +	PHY_MODE_INVALID,
> +	PHY_MODE_USB_HOST,
> +	PHY_MODE_USB_DEVICE,
> +	PHY_MODE_USB_OTG,
> +};
> +
>  /**
>   * struct phy_ops - set of function pointers for performing phy operations
>   * @init: operation to be performed for initializing phy
>   * @exit: operation to be performed while exiting
>   * @power_on: powering on the phy
>   * @power_off: powering off the phy
> + * @set_mode: set the mode of the phy
>   * @owner: the module owner containing the ops
>   */
>  struct phy_ops {
> @@ -35,6 +43,7 @@ struct phy_ops {
>  	int	(*exit)(struct phy *phy);
>  	int	(*power_on)(struct phy *phy);
>  	int	(*power_off)(struct phy *phy);
> +	int	(*set_mode)(struct phy *phy, enum phy_mode mode);
>  	struct module *owner;
>  };
>  
> @@ -119,6 +128,7 @@ int phy_init(struct phy *phy);
>  int phy_exit(struct phy *phy);
>  int phy_power_on(struct phy *phy);
>  int phy_power_off(struct phy *phy);
> +int phy_set_mode(struct phy *phy, enum phy_mode mode);
>  static inline int phy_get_bus_width(struct phy *phy)
>  {
>  	return phy->attrs.bus_width;
> @@ -224,6 +234,13 @@ static inline int phy_power_off(struct phy *phy)
>     return -ENOSYS;
>  }
>  
> +static inline int phy_set_mode(struct phy *phy, enum phy_mode mode)
> +{
> +	if (!phy)
> +		return 0;
> +	return -ENOSYS;
> +}
> +
>  static inline int phy_get_bus_width(struct phy *phy)
>  {
>     return -ENOSYS;
> -- 
> 1.9.1
> 
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Re: [PATCH v4 3/7] phy: Add set_mode callback

[David Lechner]

On 05/04/2016 01:10 PM, Bin Liu wrote:
> Hi,
>
> On Thu, Apr 14, 2016 at 01:35:14PM -0500, David Lechner wrote:
>> The initial use for this is for PHYs that have a mode related to USB OTG.
>> There are several SoCs (e.g. TI OMAP and DA8xx) that have a mode setting
>> in the USB PHY to override OTG VBUS and ID signals.
>>
>> Of course, the enum can be expaned in the future to include modes for
>> other types of PHYs as well.
>>
>> Suggested-by: Kishon Vijay Abraham I <kishon@ti.com>
>> Signed-off-by: David Lechner <david@lechnology.com>
>> ---
>>
>> v4 changes:
>>
>> * This is a new patch to avoid exporting a symbol from the phy-da8xx-usb driver.
>>
>>
>>   drivers/phy/phy-core.c  | 15 +++++++++++++++
>>   include/linux/phy/phy.h | 15 +++++++++++++++
>>   2 files changed, 30 insertions(+)
>>
>> diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
>> index e7e574d..fe0344c 100644
>> --- a/drivers/phy/phy-core.c
>> +++ b/drivers/phy/phy-core.c
>> @@ -342,6 +342,21 @@ int phy_power_off(struct phy *phy)
>>   }
>>   EXPORT_SYMBOL_GPL(phy_power_off);
>>
>> +int phy_set_mode(struct phy *phy, enum phy_mode mode)
>> +{
>> +	int ret;
>> +
>> +	if (!phy || !phy->ops->set_mode)
>> +		return 0;
>> +
>> +	mutex_lock(&phy->mutex);
>> +	ret = phy->ops->set_mode(phy, mode);
>> +	mutex_unlock(&phy->mutex);
>> +
>> +	return ret;
>> +}
>> +EXPORT_SYMBOL_GPL(phy_set_mode);
>
> Sorry for my late comments, have been busy on other things.
>
> As I commented in v2, isn't it a better idea to not adding this callback
> and let the da8xx phy driver set the mode register in _probe() based on
> DT dr_mode?
>
> musb core only calls the *optional* _set_mode() during init, so I don't
> see any problem if the phy set the mode in its probe.
>
> Regards,
> -Bin.
>

As was already discussed, the mode can be changed via sysfs as well as 
during probe, so this callback is needed for that case.

This is something I actually plan on using because the device I am using 
(LEGO MINDSTORMS EV3) is not wired for OTG, so the callback is needed to 
override the ID and VBUS signals when switching between host and 
peripheral mode.

Re: [PATCH v4 3/7] phy: Add set_mode callback

[Bin Liu]

On Wed, May 04, 2016 at 01:20:36PM -0500, David Lechner wrote:
> On 05/04/2016 01:10 PM, Bin Liu wrote:
> >Hi,
> >
> >On Thu, Apr 14, 2016 at 01:35:14PM -0500, David Lechner wrote:
> >>The initial use for this is for PHYs that have a mode related to USB OTG.
> >>There are several SoCs (e.g. TI OMAP and DA8xx) that have a mode setting
> >>in the USB PHY to override OTG VBUS and ID signals.
> >>
> >>Of course, the enum can be expaned in the future to include modes for
> >>other types of PHYs as well.
> >>
> >>Suggested-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
> >>Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
> >>---
> >>
> >>v4 changes:
> >>
> >>* This is a new patch to avoid exporting a symbol from the phy-da8xx-usb driver.
> >>
> >>
> >>  drivers/phy/phy-core.c  | 15 +++++++++++++++
> >>  include/linux/phy/phy.h | 15 +++++++++++++++
> >>  2 files changed, 30 insertions(+)
> >>
> >>diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> >>index e7e574d..fe0344c 100644
> >>--- a/drivers/phy/phy-core.c
> >>+++ b/drivers/phy/phy-core.c
> >>@@ -342,6 +342,21 @@ int phy_power_off(struct phy *phy)
> >>  }
> >>  EXPORT_SYMBOL_GPL(phy_power_off);
> >>
> >>+int phy_set_mode(struct phy *phy, enum phy_mode mode)
> >>+{
> >>+	int ret;
> >>+
> >>+	if (!phy || !phy->ops->set_mode)
> >>+		return 0;
> >>+
> >>+	mutex_lock(&phy->mutex);
> >>+	ret = phy->ops->set_mode(phy, mode);
> >>+	mutex_unlock(&phy->mutex);
> >>+
> >>+	return ret;
> >>+}
> >>+EXPORT_SYMBOL_GPL(phy_set_mode);
> >
> >Sorry for my late comments, have been busy on other things.
> >
> >As I commented in v2, isn't it a better idea to not adding this callback
> >and let the da8xx phy driver set the mode register in _probe() based on
> >DT dr_mode?
> >
> >musb core only calls the *optional* _set_mode() during init, so I don't
> >see any problem if the phy set the mode in its probe.
> >
> >Regards,
> >-Bin.
> >
> 
> As was already discussed, the mode can be changed via sysfs as well
> as during probe, so this callback is needed for that case.

Ahh, it seems we have discussed this... I keep forgetting things...

> 
> This is something I actually plan on using because the device I am
> using (LEGO MINDSTORMS EV3) is not wired for OTG, so the callback is
> needed to override the ID and VBUS signals when switching between
> host and peripheral mode.

Have you already tested this? I never tried changing mode via sysfs, but
by quickly reviewing the code, I am wondering how it works. the core
only calls ops->set_mode() but nothing else. To really switch the mode,
the driver has to talk to the root hub, and manipulate the SESSION
bit...

Regards,
-Bin.

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Re: [PATCH v4 3/7] phy: Add set_mode callback

[David Lechner]

On 05/04/2016 01:39 PM, Bin Liu wrote:
>
> Have you already tested this? I never tried changing mode via sysfs, but
> by quickly reviewing the code, I am wondering how it works. the core
> only calls ops->set_mode() but nothing else. To really switch the mode,
> the driver has to talk to the root hub, and manipulate the SESSION
> bit...
>
> Regards,
> -Bin.
>


I haven't actually tried this. I need to hack together a USB cable to 
test it in host mode (Mini-B to Mini-B w/ powered hub).
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Re: [PATCH v4 3/7] phy: Add set_mode callback

[David Lechner]

On 05/04/2016 01:39 PM, Bin Liu wrote:
> On Wed, May 04, 2016 at 01:20:36PM -0500, David Lechner wrote:
>> This is something I actually plan on using because the device I am
>> using (LEGO MINDSTORMS EV3) is not wired for OTG, so the callback is
>> needed to override the ID and VBUS signals when switching between
>> host and peripheral mode.
>
> Have you already tested this? I never tried changing mode via sysfs, but
> by quickly reviewing the code, I am wondering how it works. the core
> only calls ops->set_mode() but nothing else. To really switch the mode,
> the driver has to talk to the root hub, and manipulate the SESSION
> bit...
>

I have tested this now and it works. It works because by setting the 
mode, we are overriding the VBUS and ID signals, which in turn triggers 
interrupts. I have tested switching to both peripheral mode and host 
mode via sysfs. Host mode has some issues if you are using a 
self-powered device, but that is a bug in the da8xx glue layer and 
shouldn't hold up this patch series. Aside from that, it works exactly 
as expected.
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[PATCH v4 4/7] phy: da8xx-usb: new driver for DA8xx SoC USB PHY

[David Lechner]

This is a new phy driver for the SoC USB controllers on the TI DA8xx
family of microcontrollers. The USB 1.1 PHY is just a simple on/off.
The USB 2.0 PHY also allows overriding the VBUS and ID pins.

Signed-off-by: David Lechner <david@lechnology.com>
---

v4 changes:

* Using phy->ops->get_mode() instead of exporting symbol.
* Using CFGCHIP(2) instead of CFGCHIP2_REG
* Fixed da8xx_usb20_phy_* not matching ops.*


 drivers/phy/Kconfig         |  10 ++
 drivers/phy/Makefile        |   1 +
 drivers/phy/phy-da8xx-usb.c | 245 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 256 insertions(+)
 create mode 100644 drivers/phy/phy-da8xx-usb.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 26566db..c1d315f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -35,6 +35,16 @@ config ARMADA375_USBCLUSTER_PHY
 	depends on OF && HAS_IOMEM
 	select GENERIC_PHY
 
+config PHY_DA8XX_USB
+	tristate "TI DA8xx USB PHY Driver"
+	depends on ARCH_DAVINCI_DA8XX
+	select GENERIC_PHY
+	select MFD_SYSCON
+	help
+	  Enable this to support the USB PHY on DA8xx SoCs.
+
+	  This driver controls both the USB 1.1 PHY and the USB 2.0 PHY.
+
 config PHY_DM816X_USB
 	tristate "TI dm816x USB PHY driver"
 	depends on ARCH_OMAP2PLUS
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 24596a9..722e01c 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
 obj-$(CONFIG_PHY_BERLIN_USB)		+= phy-berlin-usb.o
 obj-$(CONFIG_PHY_BERLIN_SATA)		+= phy-berlin-sata.o
+obj-$(CONFIG_PHY_DA8XX_USB)		+= phy-da8xx-usb.o
 obj-$(CONFIG_PHY_DM816X_USB)		+= phy-dm816x-usb.o
 obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)	+= phy-armada375-usb2.o
 obj-$(CONFIG_BCM_KONA_USB2_PHY)		+= phy-bcm-kona-usb2.o
diff --git a/drivers/phy/phy-da8xx-usb.c b/drivers/phy/phy-da8xx-usb.c
new file mode 100644
index 0000000..25847e6
--- /dev/null
+++ b/drivers/phy/phy-da8xx-usb.c
@@ -0,0 +1,245 @@
+/*
+ * phy-da8xx-usb - TI DaVinci DA8xx USB PHY driver
+ *
+ * Copyright (C) 2016 David Lechner <david@lechnology.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/mfd/da8xx-cfgchip.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+struct da8xx_usbphy {
+	struct phy_provider	*phy_provider;
+	struct phy		*usb11_phy;
+	struct phy		*usb20_phy;
+	struct clk		*usb11_clk;
+	struct clk		*usb20_clk;
+	struct regmap		*regmap;
+};
+
+static int da8xx_usb11_phy_power_on(struct phy *phy)
+{
+	struct da8xx_usbphy *d_phy = phy_get_drvdata(phy);
+	int ret;
+
+	ret = clk_prepare_enable(d_phy->usb11_clk);
+	if (ret)
+		return ret;
+
+	regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_USB1SUSPENDM,
+			  CFGCHIP2_USB1SUSPENDM);
+
+	return 0;
+}
+
+static int da8xx_usb11_phy_power_off(struct phy *phy)
+{
+	struct da8xx_usbphy *d_phy = phy_get_drvdata(phy);
+
+	regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_USB1SUSPENDM, 0);
+
+	clk_disable_unprepare(d_phy->usb11_clk);
+
+	return 0;
+}
+
+static const struct phy_ops da8xx_usb11_phy_ops = {
+	.power_on	= da8xx_usb11_phy_power_on,
+	.power_off	= da8xx_usb11_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int da8xx_usb20_phy_power_on(struct phy *phy)
+{
+	struct da8xx_usbphy *d_phy = phy_get_drvdata(phy);
+	int ret;
+
+	ret = clk_prepare_enable(d_phy->usb20_clk);
+	if (ret)
+		return ret;
+
+	regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGPWRDN, 0);
+
+	return 0;
+}
+
+static int da8xx_usb20_phy_power_off(struct phy *phy)
+{
+	struct da8xx_usbphy *d_phy = phy_get_drvdata(phy);
+
+	regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGPWRDN,
+			  CFGCHIP2_OTGPWRDN);
+
+	clk_disable_unprepare(d_phy->usb20_clk);
+
+	return 0;
+}
+
+int da8xx_usb20_phy_set_mode(struct phy *phy, enum phy_mode mode)
+{
+	struct da8xx_usbphy *d_phy = phy_get_drvdata(phy);
+	u32 val;
+
+	switch (mode) {
+	case PHY_MODE_USB_HOST:		/* Force VBUS valid, ID = 0 */
+		val = CFGCHIP2_OTGMODE_FORCE_HOST;
+		break;
+	case PHY_MODE_USB_DEVICE:	/* Force VBUS valid, ID = 1 */
+		val = CFGCHIP2_OTGMODE_FORCE_DEVICE;
+		break;
+	case PHY_MODE_USB_OTG:	/* Don't override the VBUS/ID comparators */
+		val = CFGCHIP2_OTGMODE_NO_OVERRIDE;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGMODE_MASK, val);
+
+	return 0;
+}
+
+static const struct phy_ops da8xx_usb20_phy_ops = {
+	.power_on	= da8xx_usb20_phy_power_on,
+	.power_off	= da8xx_usb20_phy_power_off,
+	.set_mode	= da8xx_usb20_phy_set_mode,
+	.owner		= THIS_MODULE,
+};
+
+static struct phy *da8xx_usbphy_of_xlate(struct device *dev,
+					 struct of_phandle_args *args)
+{
+	struct da8xx_usbphy *d_phy = dev_get_drvdata(dev);
+
+	if (!d_phy)
+		return ERR_PTR(-ENODEV);
+
+	switch (args->args[0]) {
+	case 0:
+		return d_phy->usb20_phy;
+	case 1:
+		return d_phy->usb11_phy;
+	default:
+		return ERR_PTR(-EINVAL);
+	}
+}
+
+static int da8xx_usbphy_probe(struct platform_device *pdev)
+{
+	struct device		*dev = &pdev->dev;
+	struct device_node	*node = dev->of_node;
+	struct da8xx_usbphy	*d_phy;
+
+	d_phy = devm_kzalloc(dev, sizeof(*d_phy), GFP_KERNEL);
+	if (!d_phy)
+		return -ENOMEM;
+
+	if (node)
+		d_phy->regmap = syscon_regmap_lookup_by_compatible(
+							"ti,da830-cfgchip");
+	else
+		d_phy->regmap = syscon_regmap_lookup_by_pdevname("syscon.0");
+	if (IS_ERR(d_phy->regmap)) {
+		dev_err(dev, "Failed to get syscon\n");
+		return PTR_ERR(d_phy->regmap);
+	}
+
+	d_phy->usb11_clk = devm_clk_get(dev, "usb11_phy");
+	if (IS_ERR(d_phy->usb11_clk)) {
+		dev_err(dev, "Failed to get usb11_phy clock\n");
+		return PTR_ERR(d_phy->usb11_clk);
+	}
+
+	d_phy->usb20_clk = devm_clk_get(dev, "usb20_phy");
+	if (IS_ERR(d_phy->usb20_clk)) {
+		dev_err(dev, "Failed to get usb20_phy clock\n");
+		return PTR_ERR(d_phy->usb20_clk);
+	}
+
+	d_phy->usb11_phy = devm_phy_create(dev, node, &da8xx_usb11_phy_ops);
+	if (IS_ERR(d_phy->usb11_phy)) {
+		dev_err(dev, "Failed to create usb11 phy\n");
+		return PTR_ERR(d_phy->usb11_phy);
+	}
+
+	d_phy->usb20_phy = devm_phy_create(dev, node, &da8xx_usb20_phy_ops);
+	if (IS_ERR(d_phy->usb20_phy)) {
+		dev_err(dev, "Failed to create usb20 phy\n");
+		return PTR_ERR(d_phy->usb20_phy);
+	}
+
+	platform_set_drvdata(pdev, d_phy);
+	phy_set_drvdata(d_phy->usb11_phy, d_phy);
+	phy_set_drvdata(d_phy->usb20_phy, d_phy);
+
+	if (node) {
+		d_phy->phy_provider = devm_of_phy_provider_register(dev,
+							da8xx_usbphy_of_xlate);
+		if (IS_ERR(d_phy->phy_provider)) {
+			dev_err(dev, "Failed to create phy provider\n");
+			return PTR_ERR(d_phy->phy_provider);
+		}
+	} else {
+		int ret;
+
+		ret = phy_create_lookup(d_phy->usb11_phy, "usbphy", "ohci.0");
+		if (ret)
+			dev_warn(dev, "Failed to create usb11 phy lookup\n");
+		ret = phy_create_lookup(d_phy->usb20_phy, "usbphy", "musb-da8xx");
+		if (ret)
+			dev_warn(dev, "Failed to create usb20 phy lookup\n");
+	}
+
+	return 0;
+}
+
+static int da8xx_usbphy_remove(struct platform_device *pdev)
+{
+	struct da8xx_usbphy *d_phy = platform_get_drvdata(pdev);
+
+	if (!pdev->dev.of_node) {
+		phy_remove_lookup(d_phy->usb20_phy, "usbphy", "musb-da8xx");
+		phy_remove_lookup(d_phy->usb11_phy, "usbphy", "ohci.0");
+	}
+
+	return 0;
+}
+
+static const struct of_device_id da8xx_usbphy_ids[] = {
+	{ .compatible = "ti,da830-usbphy" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, da8xx_usbphy_ids);
+
+static struct platform_driver da8xx_usbphy_driver = {
+	.probe	= da8xx_usbphy_probe,
+	.remove	= da8xx_usbphy_remove,
+	.driver	= {
+		.name	= "da8xx-usbphy",
+		.of_match_table = da8xx_usbphy_ids,
+	},
+};
+
+module_platform_driver(da8xx_usbphy_driver);
+
+MODULE_ALIAS("platform:da8xx-usbphy");
+MODULE_AUTHOR("David Lechner <david@lechnology.com>");
+MODULE_DESCRIPTION("TI DA8xx USB PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

Re: [PATCH v4 4/7] phy: da8xx-usb: new driver for DA8xx SoC USB PHY

[Kishon Vijay Abraham I]

Hi,

On Friday 15 April 2016 12:05 AM, David Lechner wrote:
> This is a new phy driver for the SoC USB controllers on the TI DA8xx
> family of microcontrollers. The USB 1.1 PHY is just a simple on/off.
> The USB 2.0 PHY also allows overriding the VBUS and ID pins.
> 
> Signed-off-by: David Lechner <david@lechnology.com>
> ---
> 
> v4 changes:
> 
> * Using phy->ops->get_mode() instead of exporting symbol.
> * Using CFGCHIP(2) instead of CFGCHIP2_REG
> * Fixed da8xx_usb20_phy_* not matching ops.*
> 
> 
>  drivers/phy/Kconfig         |  10 ++
>  drivers/phy/Makefile        |   1 +
>  drivers/phy/phy-da8xx-usb.c | 245 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 256 insertions(+)
>  create mode 100644 drivers/phy/phy-da8xx-usb.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 26566db..c1d315f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -35,6 +35,16 @@ config ARMADA375_USBCLUSTER_PHY
>  	depends on OF && HAS_IOMEM
>  	select GENERIC_PHY
>  
> +config PHY_DA8XX_USB
> +	tristate "TI DA8xx USB PHY Driver"
> +	depends on ARCH_DAVINCI_DA8XX
> +	select GENERIC_PHY
> +	select MFD_SYSCON
> +	help
> +	  Enable this to support the USB PHY on DA8xx SoCs.
> +
> +	  This driver controls both the USB 1.1 PHY and the USB 2.0 PHY.
> +
>  config PHY_DM816X_USB
>  	tristate "TI dm816x USB PHY driver"
>  	depends on ARCH_OMAP2PLUS
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 24596a9..722e01c 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -5,6 +5,7 @@
>  obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
>  obj-$(CONFIG_PHY_BERLIN_USB)		+= phy-berlin-usb.o
>  obj-$(CONFIG_PHY_BERLIN_SATA)		+= phy-berlin-sata.o
> +obj-$(CONFIG_PHY_DA8XX_USB)		+= phy-da8xx-usb.o
>  obj-$(CONFIG_PHY_DM816X_USB)		+= phy-dm816x-usb.o
>  obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)	+= phy-armada375-usb2.o
>  obj-$(CONFIG_BCM_KONA_USB2_PHY)		+= phy-bcm-kona-usb2.o
> diff --git a/drivers/phy/phy-da8xx-usb.c b/drivers/phy/phy-da8xx-usb.c
> new file mode 100644
> index 0000000..25847e6
> --- /dev/null
> +++ b/drivers/phy/phy-da8xx-usb.c
> @@ -0,0 +1,245 @@
> +/*
> + * phy-da8xx-usb - TI DaVinci DA8xx USB PHY driver
> + *
> + * Copyright (C) 2016 David Lechner <david@lechnology.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.

If it's GPL v2 or later, MODULE_LICENSE below should be GPL.
See include/linux/module.h
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/mfd/da8xx-cfgchip.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +struct da8xx_usbphy {
> +	struct phy_provider	*phy_provider;
> +	struct phy		*usb11_phy;
> +	struct phy		*usb20_phy;
> +	struct clk		*usb11_clk;
> +	struct clk		*usb20_clk;
> +	struct regmap		*regmap;
> +};
> +
> +static int da8xx_usb11_phy_power_on(struct phy *phy)
> +{
> +	struct da8xx_usbphy *d_phy = phy_get_drvdata(phy);
> +	int ret;
> +
> +	ret = clk_prepare_enable(d_phy->usb11_clk);
> +	if (ret)
> +		return ret;
> +
> +	regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_USB1SUSPENDM,
> +			  CFGCHIP2_USB1SUSPENDM);
> +
> +	return 0;
> +}
> +
> +static int da8xx_usb11_phy_power_off(struct phy *phy)
> +{
> +	struct da8xx_usbphy *d_phy = phy_get_drvdata(phy);
> +
> +	regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_USB1SUSPENDM, 0);
> +
> +	clk_disable_unprepare(d_phy->usb11_clk);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops da8xx_usb11_phy_ops = {
> +	.power_on	= da8xx_usb11_phy_power_on,
> +	.power_off	= da8xx_usb11_phy_power_off,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int da8xx_usb20_phy_power_on(struct phy *phy)
> +{
> +	struct da8xx_usbphy *d_phy = phy_get_drvdata(phy);
> +	int ret;
> +
> +	ret = clk_prepare_enable(d_phy->usb20_clk);
> +	if (ret)
> +		return ret;
> +
> +	regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGPWRDN, 0);
> +
> +	return 0;
> +}
> +
> +static int da8xx_usb20_phy_power_off(struct phy *phy)
> +{
> +	struct da8xx_usbphy *d_phy = phy_get_drvdata(phy);
> +
> +	regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGPWRDN,
> +			  CFGCHIP2_OTGPWRDN);
> +
> +	clk_disable_unprepare(d_phy->usb20_clk);
> +
> +	return 0;
> +}
> +
> +int da8xx_usb20_phy_set_mode(struct phy *phy, enum phy_mode mode)
> +{

this should be static.
> +	struct da8xx_usbphy *d_phy = phy_get_drvdata(phy);
> +	u32 val;
> +
> +	switch (mode) {
> +	case PHY_MODE_USB_HOST:		/* Force VBUS valid, ID = 0 */
> +		val = CFGCHIP2_OTGMODE_FORCE_HOST;
> +		break;
> +	case PHY_MODE_USB_DEVICE:	/* Force VBUS valid, ID = 1 */
> +		val = CFGCHIP2_OTGMODE_FORCE_DEVICE;
> +		break;
> +	case PHY_MODE_USB_OTG:	/* Don't override the VBUS/ID comparators */
> +		val = CFGCHIP2_OTGMODE_NO_OVERRIDE;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGMODE_MASK, val);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops da8xx_usb20_phy_ops = {
> +	.power_on	= da8xx_usb20_phy_power_on,
> +	.power_off	= da8xx_usb20_phy_power_off,
> +	.set_mode	= da8xx_usb20_phy_set_mode,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static struct phy *da8xx_usbphy_of_xlate(struct device *dev,
> +					 struct of_phandle_args *args)
> +{
> +	struct da8xx_usbphy *d_phy = dev_get_drvdata(dev);
> +
> +	if (!d_phy)
> +		return ERR_PTR(-ENODEV);
> +
> +	switch (args->args[0]) {
> +	case 0:
> +		return d_phy->usb20_phy;
> +	case 1:
> +		return d_phy->usb11_phy;
> +	default:
> +		return ERR_PTR(-EINVAL);
> +	}
> +}
> +
> +static int da8xx_usbphy_probe(struct platform_device *pdev)
> +{
> +	struct device		*dev = &pdev->dev;
> +	struct device_node	*node = dev->of_node;
> +	struct da8xx_usbphy	*d_phy;
> +
> +	d_phy = devm_kzalloc(dev, sizeof(*d_phy), GFP_KERNEL);
> +	if (!d_phy)
> +		return -ENOMEM;
> +
> +	if (node)
> +		d_phy->regmap = syscon_regmap_lookup_by_compatible(
> +							"ti,da830-cfgchip");
> +	else
> +		d_phy->regmap = syscon_regmap_lookup_by_pdevname("syscon.0");
> +	if (IS_ERR(d_phy->regmap)) {
> +		dev_err(dev, "Failed to get syscon\n");
> +		return PTR_ERR(d_phy->regmap);
> +	}
> +
> +	d_phy->usb11_clk = devm_clk_get(dev, "usb11_phy");
> +	if (IS_ERR(d_phy->usb11_clk)) {
> +		dev_err(dev, "Failed to get usb11_phy clock\n");
> +		return PTR_ERR(d_phy->usb11_clk);
> +	}
> +
> +	d_phy->usb20_clk = devm_clk_get(dev, "usb20_phy");
> +	if (IS_ERR(d_phy->usb20_clk)) {
> +		dev_err(dev, "Failed to get usb20_phy clock\n");
> +		return PTR_ERR(d_phy->usb20_clk);
> +	}
> +
> +	d_phy->usb11_phy = devm_phy_create(dev, node, &da8xx_usb11_phy_ops);
> +	if (IS_ERR(d_phy->usb11_phy)) {
> +		dev_err(dev, "Failed to create usb11 phy\n");
> +		return PTR_ERR(d_phy->usb11_phy);
> +	}
> +
> +	d_phy->usb20_phy = devm_phy_create(dev, node, &da8xx_usb20_phy_ops);
> +	if (IS_ERR(d_phy->usb20_phy)) {
> +		dev_err(dev, "Failed to create usb20 phy\n");
> +		return PTR_ERR(d_phy->usb20_phy);
> +	}
> +
> +	platform_set_drvdata(pdev, d_phy);
> +	phy_set_drvdata(d_phy->usb11_phy, d_phy);
> +	phy_set_drvdata(d_phy->usb20_phy, d_phy);
> +
> +	if (node) {
> +		d_phy->phy_provider = devm_of_phy_provider_register(dev,
> +							da8xx_usbphy_of_xlate);
> +		if (IS_ERR(d_phy->phy_provider)) {
> +			dev_err(dev, "Failed to create phy provider\n");
> +			return PTR_ERR(d_phy->phy_provider);
> +		}
> +	} else {
> +		int ret;
> +
> +		ret = phy_create_lookup(d_phy->usb11_phy, "usbphy", "ohci.0");
> +		if (ret)
> +			dev_warn(dev, "Failed to create usb11 phy lookup\n");
> +		ret = phy_create_lookup(d_phy->usb20_phy, "usbphy", "musb-da8xx");
> +		if (ret)
> +			dev_warn(dev, "Failed to create usb20 phy lookup\n");
> +	}
> +
> +	return 0;
> +}
> +
> +static int da8xx_usbphy_remove(struct platform_device *pdev)
> +{
> +	struct da8xx_usbphy *d_phy = platform_get_drvdata(pdev);
> +
> +	if (!pdev->dev.of_node) {
> +		phy_remove_lookup(d_phy->usb20_phy, "usbphy", "musb-da8xx");
> +		phy_remove_lookup(d_phy->usb11_phy, "usbphy", "ohci.0");
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id da8xx_usbphy_ids[] = {
> +	{ .compatible = "ti,da830-usbphy" },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, da8xx_usbphy_ids);
> +
> +static struct platform_driver da8xx_usbphy_driver = {
> +	.probe	= da8xx_usbphy_probe,
> +	.remove	= da8xx_usbphy_remove,
> +	.driver	= {
> +		.name	= "da8xx-usbphy",
> +		.of_match_table = da8xx_usbphy_ids,
> +	},
> +};
> +
> +module_platform_driver(da8xx_usbphy_driver);
> +
> +MODULE_ALIAS("platform:da8xx-usbphy");
> +MODULE_AUTHOR("David Lechner <david@lechnology.com>");
> +MODULE_DESCRIPTION("TI DA8xx USB PHY driver");
> +MODULE_LICENSE("GPL v2");

Either this or the file header should be fixed.

Thanks
Kishon

[PATCH v4 5/7] usb: ohci-da8xx: Remove code that references mach

[David Lechner]

Including mach/* is frowned upon in device drivers, so get rid of it.

This replaces usb20_clk and code that pokes CFGCHIP2 with a proper phy
driver.

Signed-off-by: David Lechner <david@lechnology.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
---

v4 changes: no change


 drivers/usb/host/Kconfig      |   1 +
 drivers/usb/host/ohci-da8xx.c | 102 +++++++++++++++++++++++-------------------
 2 files changed, 56 insertions(+), 47 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 3050b18..e4432c6 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -472,6 +472,7 @@ config USB_OHCI_HCD_DAVINCI
 	bool "OHCI support for TI DaVinci DA8xx"
 	depends on ARCH_DAVINCI_DA8XX
 	depends on USB_OHCI_HCD=y
+	select PHY_DA8XX_USB
 	default y
 	help
 	  Enables support for the DaVinci DA8xx integrated OHCI
diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c
index e5c33bc..9d093ac 100644
--- a/drivers/usb/host/ohci-da8xx.c
+++ b/drivers/usb/host/ohci-da8xx.c
@@ -15,58 +15,50 @@
 #include <linux/jiffies.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
-
-#include <mach/da8xx.h>
+#include <linux/phy/phy.h>
 #include <linux/platform_data/usb-davinci.h>
 
 #ifndef CONFIG_ARCH_DAVINCI_DA8XX
 #error "This file is DA8xx bus glue.  Define CONFIG_ARCH_DAVINCI_DA8XX."
 #endif
 
-#define CFGCHIP2	DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)
-
 static struct clk *usb11_clk;
-static struct clk *usb20_clk;
+static struct phy *usb11_phy;
 
 /* Over-current indicator change bitmask */
 static volatile u16 ocic_mask;
 
-static void ohci_da8xx_clock(int on)
+static int ohci_da8xx_enable(void)
 {
-	u32 cfgchip2;
-
-	cfgchip2 = __raw_readl(CFGCHIP2);
-	if (on) {
-		clk_enable(usb11_clk);
-
-		/*
-		 * If USB 1.1 reference clock is sourced from USB 2.0 PHY, we
-		 * need to enable the USB 2.0 module clocking, start its PHY,
-		 * and not allow it to stop the clock during USB 2.0 suspend.
-		 */
-		if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX)) {
-			clk_enable(usb20_clk);
-
-			cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN);
-			cfgchip2 |= CFGCHIP2_PHY_PLLON;
-			__raw_writel(cfgchip2, CFGCHIP2);
-
-			pr_info("Waiting for USB PHY clock good...\n");
-			while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
-				cpu_relax();
-		}
+	int ret;
 
-		/* Enable USB 1.1 PHY */
-		cfgchip2 |= CFGCHIP2_USB1SUSPENDM;
-	} else {
-		clk_disable(usb11_clk);
-		if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX))
-			clk_disable(usb20_clk);
+	ret = clk_prepare_enable(usb11_clk);
+	if (ret)
+		return ret;
 
-		/* Disable USB 1.1 PHY */
-		cfgchip2 &= ~CFGCHIP2_USB1SUSPENDM;
-	}
-	__raw_writel(cfgchip2, CFGCHIP2);
+	ret = phy_init(usb11_phy);
+	if (ret)
+		goto err_phy_init;
+
+	ret = phy_power_on(usb11_phy);
+	if (ret)
+		goto err_phy_power_on;
+
+	return 0;
+
+err_phy_power_on:
+	phy_exit(usb11_phy);
+err_phy_init:
+	clk_disable_unprepare(usb11_clk);
+
+	return ret;
+}
+
+static void ohci_da8xx_disable(void)
+{
+	phy_power_off(usb11_phy);
+	phy_exit(usb11_phy);
+	clk_disable_unprepare(usb11_clk);
 }
 
 /*
@@ -92,7 +84,9 @@ static int ohci_da8xx_init(struct usb_hcd *hcd)
 
 	dev_dbg(dev, "starting USB controller\n");
 
-	ohci_da8xx_clock(1);
+	result = ohci_da8xx_enable();
+	if (result < 0)
+		return result;
 
 	/*
 	 * DA8xx only have 1 port connected to the pins but the HC root hub
@@ -101,8 +95,10 @@ static int ohci_da8xx_init(struct usb_hcd *hcd)
 	ohci->num_ports = 1;
 
 	result = ohci_init(ohci);
-	if (result < 0)
+	if (result < 0) {
+		ohci_da8xx_disable();
 		return result;
+	}
 
 	/*
 	 * Since we're providing a board-specific root hub port power control
@@ -129,7 +125,7 @@ static int ohci_da8xx_init(struct usb_hcd *hcd)
 static void ohci_da8xx_stop(struct usb_hcd *hcd)
 {
 	ohci_stop(hcd);
-	ohci_da8xx_clock(0);
+	ohci_da8xx_disable();
 }
 
 static int ohci_da8xx_start(struct usb_hcd *hcd)
@@ -301,12 +297,18 @@ static int usb_hcd_da8xx_probe(const struct hc_driver *driver,
 		return -ENODEV;
 
 	usb11_clk = devm_clk_get(&pdev->dev, "usb11");
-	if (IS_ERR(usb11_clk))
+	if (IS_ERR(usb11_clk)) {
+		if (PTR_ERR(usb11_clk) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "Failed to get clock.\n");
 		return PTR_ERR(usb11_clk);
+	}
 
-	usb20_clk = devm_clk_get(&pdev->dev, "usb20");
-	if (IS_ERR(usb20_clk))
-		return PTR_ERR(usb20_clk);
+	usb11_phy = devm_phy_get(&pdev->dev, "usbphy");
+	if (IS_ERR(usb11_phy)) {
+		if (PTR_ERR(usb11_phy) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "Failed to get phy.\n");
+		return PTR_ERR(usb11_phy);
+	}
 
 	hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
 	if (!hcd)
@@ -316,6 +318,7 @@ static int usb_hcd_da8xx_probe(const struct hc_driver *driver,
 	hcd->regs = devm_ioremap_resource(&pdev->dev, mem);
 	if (IS_ERR(hcd->regs)) {
 		error = PTR_ERR(hcd->regs);
+		dev_err(&pdev->dev, "failed to map ohci.\n");
 		goto err;
 	}
 	hcd->rsrc_start = mem->start;
@@ -397,7 +400,7 @@ static int ohci_da8xx_suspend(struct platform_device *pdev,
 	if (ret)
 		return ret;
 
-	ohci_da8xx_clock(0);
+	ohci_da8xx_disable();
 	hcd->state = HC_STATE_SUSPENDED;
 
 	return ret;
@@ -407,14 +410,19 @@ static int ohci_da8xx_resume(struct platform_device *dev)
 {
 	struct usb_hcd	*hcd	= platform_get_drvdata(dev);
 	struct ohci_hcd	*ohci	= hcd_to_ohci(hcd);
+	int ret;
 
 	if (time_before(jiffies, ohci->next_statechange))
 		msleep(5);
 	ohci->next_statechange = jiffies;
 
-	ohci_da8xx_clock(1);
+	ret = ohci_da8xx_enable();
+	if (ret)
+		return ret;
+
 	dev->dev.power.power_state = PMSG_ON;
 	usb_hcd_resume_root_hub(hcd);
+
 	return 0;
 }
 #endif
-- 
1.9.1

[PATCH v4 6/7] usb: musb: da8xx: Use devm in probe

[David Lechner]

Simplify things a bit by using devm functions where possible.

Signed-off-by: David Lechner <david@lechnology.com>
---

v4 changes: no change


 drivers/usb/musb/da8xx.c | 19 +++++--------------
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
index b03d3b8..0c1997c 100644
--- a/drivers/usb/musb/da8xx.c
+++ b/drivers/usb/musb/da8xx.c
@@ -490,20 +490,18 @@ static int da8xx_probe(struct platform_device *pdev)
 	struct da8xx_glue		*glue;
 	struct platform_device_info	pinfo;
 	struct clk			*clk;
+	int				ret;
 
-	int				ret = -ENOMEM;
-
-	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
+	glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
 	if (!glue) {
 		dev_err(&pdev->dev, "failed to allocate glue context\n");
-		goto err0;
+		return -ENOMEM;
 	}
 
-	clk = clk_get(&pdev->dev, "usb20");
+	clk = devm_clk_get(&pdev->dev, "usb20");
 	if (IS_ERR(clk)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
-		ret = PTR_ERR(clk);
-		goto err3;
+		return PTR_ERR(clk);
 	}
 
 	ret = clk_enable(clk);
@@ -560,12 +558,7 @@ err5:
 	clk_disable(clk);
 
 err4:
-	clk_put(clk);
-
-err3:
-	kfree(glue);
 
-err0:
 	return ret;
 }
 
@@ -576,8 +569,6 @@ static int da8xx_remove(struct platform_device *pdev)
 	platform_device_unregister(glue->musb);
 	usb_phy_generic_unregister(glue->phy);
 	clk_disable(glue->clk);
-	clk_put(glue->clk);
-	kfree(glue);
 
 	return 0;
 }
-- 
1.9.1

[PATCH v4 7/7] usb: musb: da8xx: Remove mach code

[David Lechner]

Use the new phy-da8xx-usb driver to take the place of the mach code that
pokes CFGCHIP2 in the da8xx musb glue driver. This unbreaks the driver.

Signed-off-by: David Lechner <david@lechnology.com>
---

v4 changes:

* using new phy->ops->get_mode()


 drivers/usb/musb/Kconfig |   2 +-
 drivers/usb/musb/da8xx.c | 141 ++++++++++++++++++-----------------------------
 2 files changed, 54 insertions(+), 89 deletions(-)

diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 886526b..c73221a 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -82,7 +82,7 @@ config USB_MUSB_DA8XX
 	tristate "DA8xx/OMAP-L1x"
 	depends on ARCH_DAVINCI_DA8XX
 	depends on NOP_USB_XCEIV
-	depends on BROKEN
+	select PHY_DA8XX_USB
 
 config USB_MUSB_TUSB6010
 	tristate "TUSB6010"
diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
index 0c1997c..cea2216 100644
--- a/drivers/usb/musb/da8xx.c
+++ b/drivers/usb/musb/da8xx.c
@@ -30,13 +30,11 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/usb/usb_phy_generic.h>
 
-#include <mach/da8xx.h>
-#include <linux/platform_data/usb-davinci.h>
-
 #include "musb_core.h"
 
 /*
@@ -80,61 +78,15 @@
 
 #define DA8XX_MENTOR_CORE_OFFSET 0x400
 
-#define CFGCHIP2	IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
-
 struct da8xx_glue {
 	struct device		*dev;
 	struct platform_device	*musb;
-	struct platform_device	*phy;
+	struct platform_device	*usb_phy;
 	struct clk		*clk;
+	struct phy		*phy;
 };
 
 /*
- * REVISIT (PM): we should be able to keep the PHY in low power mode most
- * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
- * and, when in host mode, autosuspending idle root ports... PHY_PLLON
- * (overriding SUSPENDM?) then likely needs to stay off.
- */
-
-static inline void phy_on(void)
-{
-	u32 cfgchip2 = __raw_readl(CFGCHIP2);
-
-	/*
-	 * Start the on-chip PHY and its PLL.
-	 */
-	cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
-	cfgchip2 |= CFGCHIP2_PHY_PLLON;
-	__raw_writel(cfgchip2, CFGCHIP2);
-
-	pr_info("Waiting for USB PHY clock good...\n");
-	while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
-		cpu_relax();
-}
-
-static inline void phy_off(void)
-{
-	u32 cfgchip2 = __raw_readl(CFGCHIP2);
-
-	/*
-	 * Ensure that USB 1.1 reference clock is not being sourced from
-	 * USB 2.0 PHY.  Otherwise do not power down the PHY.
-	 */
-	if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
-	     (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
-		pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
-			   "can't power it down\n");
-		return;
-	}
-
-	/*
-	 * Power down the on-chip PHY.
-	 */
-	cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
-	__raw_writel(cfgchip2, CFGCHIP2);
-}
-
-/*
  * Because we don't set CTRL.UINT, it's "important" to:
  *	- not read/write INTRUSB/INTRUSBE (except during
  *	  initial setup, as a workaround);
@@ -385,29 +337,29 @@ static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
 
 static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
 {
-	u32 cfgchip2 = __raw_readl(CFGCHIP2);
+	struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
+	enum phy_mode phy_mode;
 
-	cfgchip2 &= ~CFGCHIP2_OTGMODE;
 	switch (musb_mode) {
-	case MUSB_HOST:		/* Force VBUS valid, ID = 0 */
-		cfgchip2 |= CFGCHIP2_FORCE_HOST;
+	case MUSB_HOST:
+		phy_mode = PHY_MODE_USB_HOST;
 		break;
-	case MUSB_PERIPHERAL:	/* Force VBUS valid, ID = 1 */
-		cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
+	case MUSB_PERIPHERAL:
+		phy_mode = PHY_MODE_USB_DEVICE;
 		break;
-	case MUSB_OTG:		/* Don't override the VBUS/ID comparators */
-		cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
+	case MUSB_OTG:
+		phy_mode = PHY_MODE_USB_OTG;
 		break;
 	default:
-		dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
+		return -EINVAL;
 	}
 
-	__raw_writel(cfgchip2, CFGCHIP2);
-	return 0;
+	return phy_set_mode(glue->phy, phy_mode);
 }
 
 static int da8xx_musb_init(struct musb *musb)
 {
+	struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
 	void __iomem *reg_base = musb->ctrl_base;
 	u32 rev;
 	int ret = -ENODEV;
@@ -425,32 +377,56 @@ static int da8xx_musb_init(struct musb *musb)
 		goto fail;
 	}
 
+	ret = clk_prepare_enable(glue->clk);
+	if (ret) {
+		dev_err(glue->dev, "failed to enable clock\n");
+		goto fail;
+	}
+
 	setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
 
 	/* Reset the controller */
 	musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
 
 	/* Start the on-chip PHY and its PLL. */
-	phy_on();
+	ret = phy_init(glue->phy);
+	if (ret) {
+		dev_err(glue->dev, "Failed to init phy.\n");
+		goto err_phy_init;
+	}
+
+	ret = phy_power_on(glue->phy);
+	if (ret) {
+		dev_err(glue->dev, "Failed to power on phy.\n");
+		goto err_phy_power_on;
+	}
 
 	msleep(5);
 
 	/* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
-	pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
-		 rev, __raw_readl(CFGCHIP2),
+	pr_debug("DA8xx OTG revision %08x, control %02x\n", rev,
 		 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
 
 	musb->isr = da8xx_musb_interrupt;
 	return 0;
+
+err_phy_power_on:
+	phy_exit(glue->phy);
+err_phy_init:
+	clk_disable_unprepare(glue->clk);
 fail:
 	return ret;
 }
 
 static int da8xx_musb_exit(struct musb *musb)
 {
+	struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
+
 	del_timer_sync(&otg_workaround);
 
-	phy_off();
+	phy_power_off(glue->phy);
+	phy_exit(glue->phy);
+	clk_disable_unprepare(glue->clk);
 
 	usb_put_phy(musb->xceiv);
 
@@ -504,10 +480,10 @@ static int da8xx_probe(struct platform_device *pdev)
 		return PTR_ERR(clk);
 	}
 
-	ret = clk_enable(clk);
-	if (ret) {
-		dev_err(&pdev->dev, "failed to enable clock\n");
-		goto err4;
+	glue->phy = devm_phy_get(&pdev->dev, "usbphy");
+	if (IS_ERR(glue->phy)) {
+		dev_err(&pdev->dev, "failed to get phy\n");
+		return PTR_ERR(glue->phy);
 	}
 
 	glue->dev			= &pdev->dev;
@@ -515,10 +491,10 @@ static int da8xx_probe(struct platform_device *pdev)
 
 	pdata->platform_ops		= &da8xx_ops;
 
-	glue->phy = usb_phy_generic_register();
-	if (IS_ERR(glue->phy)) {
-		ret = PTR_ERR(glue->phy);
-		goto err5;
+	glue->usb_phy = usb_phy_generic_register();
+	if (IS_ERR(glue->usb_phy)) {
+		dev_err(&pdev->dev, "failed to register usb_phy\n");
+		return PTR_ERR(glue->usb_phy);
 	}
 	platform_set_drvdata(pdev, glue);
 
@@ -544,22 +520,12 @@ static int da8xx_probe(struct platform_device *pdev)
 
 	glue->musb = musb = platform_device_register_full(&pinfo);
 	if (IS_ERR(musb)) {
-		ret = PTR_ERR(musb);
 		dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
-		goto err6;
+		usb_phy_generic_unregister(glue->usb_phy);
+		return PTR_ERR(musb);
 	}
 
 	return 0;
-
-err6:
-	usb_phy_generic_unregister(glue->phy);
-
-err5:
-	clk_disable(clk);
-
-err4:
-
-	return ret;
 }
 
 static int da8xx_remove(struct platform_device *pdev)
@@ -567,8 +533,7 @@ static int da8xx_remove(struct platform_device *pdev)
 	struct da8xx_glue		*glue = platform_get_drvdata(pdev);
 
 	platform_device_unregister(glue->musb);
-	usb_phy_generic_unregister(glue->phy);
-	clk_disable(glue->clk);
+	usb_phy_generic_unregister(glue->usb_phy);
 
 	return 0;
 }
-- 
1.9.1

Re: [PATCH v4 0/7] da8xx USB PHY (was da8xx USB clocks)

[David Lechner]

On 04/14/2016 01:35 PM, David Lechner wrote:
> The "da8xx USB clocks" patch series was growing a bit too big, so on the advice
> of Sekhar Nori, I am splitting it into two parts. This part contains everything
> in drivers/ and the other part will contain everything in arch/arm/mach-davinci.
>
> This patch series will apply and build on its own. It just won't work at runtime
> without the corresponding mach-davinci changes to provide clocks, etc.
>
> This round just contains changes from feedback. See individual patches for
> details.
>
> Tested working on LEGO MINDSTORMS EV3 using linux-davinci/master branch.
>
> David Lechner (7):
>    mfd: da8xx-cfgchip: New header file for CFGCHIP registers.
>    dt-bindings: Add bindings for phy-da8xx-usb
>    phy: Add set_mode callback
>    phy: da8xx-usb: new driver for DA8xx SoC USB PHY
>    usb: ohci-da8xx: Remove code that references mach
>    usb: musb: da8xx: Use devm in probe
>    usb: musb: da8xx: Remove mach code
>
>   .../devicetree/bindings/phy/phy-da8xx-usb.txt      |  40 ++++
>   drivers/phy/Kconfig                                |  10 +
>   drivers/phy/Makefile                               |   1 +
>   drivers/phy/phy-core.c                             |  15 ++
>   drivers/phy/phy-da8xx-usb.c                        | 245 +++++++++++++++++++++
>   drivers/usb/host/Kconfig                           |   1 +
>   drivers/usb/host/ohci-da8xx.c                      | 102 +++++----
>   drivers/usb/musb/Kconfig                           |   2 +-
>   drivers/usb/musb/da8xx.c                           | 160 +++++---------
>   include/linux/mfd/da8xx-cfgchip.h                  | 153 +++++++++++++
>   include/linux/phy/phy.h                            |  15 ++
>   include/linux/platform_data/usb-davinci.h          |  22 --
>   12 files changed, 594 insertions(+), 172 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
>   create mode 100644 drivers/phy/phy-da8xx-usb.c
>   create mode 100644 include/linux/mfd/da8xx-cfgchip.h
>

I think all of the maintainers have weighed in now. So, I think I am 
ready to submit a v5 series to address some small issues to get this to 
"good enough" status. Which maintainer will take responsibility for 
including this in his tree?
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