From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kedareswara rao Appana Subject: [PATCH v7 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation Date: Wed, 27 Apr 2016 12:35:28 +0530 Message-ID: <1461740729-30715-1-git-send-email-appanad@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: Sender: linux-kernel-owner@vger.kernel.org To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, michal.simek@xilinx.com, soren.brinkmann@xilinx.com, vinod.koul@intel.com, dan.j.williams@intel.com, appanad@xilinx.com, moritz.fischer@ettus.com, laurent.pinchart@ideasonboard.com, luis@debethencourt.com, anirudh@xilinx.com, punnaia@xilinx.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org List-Id: devicetree@vger.kernel.org Device-tree binding documentation for Xilinx zynqmp dma engine used in Zynq UltraScale+ MPSoC. Signed-off-by: Punnaiah Choudary Kalluri Signed-off-by: Kedareswara rao Appana --- Changes in v7: - None. Changes in v6: - Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties from the binding doc as it allow broken combinations when dma-coherent is set as suggested by Rob. - Fixed minor comments given by Rob related coding(lower case DT node name). Changes in v5: - Use dma-coherent flag for coherent transfers as suggested by rob. - Removed unnecessary properties from binding doc as suggested by Rob. Changes in v4: - None Changes in v3: - None Changes in v2: - None. .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt new file mode 100644 index 0000000..f0f0b54 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt @@ -0,0 +1,44 @@ +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, +memory to device and device to memory transfers. It also has flow +control and rate control support for slave/peripheral dma access. + +Required properties: +- compatible : Should be "xlnx,zynqmp-dma-1.0" +- reg : Memory map for gdma/adma module access. +- interrupt-parent : Interrupt controller the interrupt is routed through +- interrupts : Should contain DMA channel interrupt. +- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 +- clock-names : List of input clocks "clk_main", "clk_apb" + (see clock bindings for details) + +Optional properties: +- xlnx,include-sg : Indicates the controller to operate in simple or + scatter gather dma mode +- xlnx,ratectrl : Scheduling interval in terms of clock cycles for + source AXI transaction +- xlnx,overfetch : Tells whether the channel is allowed to over + fetch the data +- xlnx,src-issue : Number of AXI outstanding transactions on source side +- xlnx,src-burst-len : AXI length for data read. Support only power of + 2 byte values. +- xlnx,dst-burst-len : AXI length for data write. Support only power of + 2 byte values. +- dma-coherent : Present if dma operations are coherent. + +Example: +++++++++ +fpd_dma_chan1: dma@fd500000 { + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xFD500000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 117 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + xlnx,include-sg; + xlnx,overfetch; + dma-coherent; + xlnx,ratectrl = <0>; + xlnx,src-issue = <16>; + xlnx,src-burst-len = <4>; + xlnx,dst-burst-len = <4>; +}; -- 2.1.2