From: Benjamin Herrenschmidt <benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>
To: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
Cc: tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org,
jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org,
marc.zyngier-5wv7dgnIgG8@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
jk-mnsaURCQ41sdnm+yROfE0A@public.gmane.org,
arnd-r2nGTMty4D4@public.gmane.org
Subject: Re: [PATCH 1/2] doc/devicetree: Add Aspeed VIC bindings
Date: Tue, 10 May 2016 08:04:40 +1000 [thread overview]
Message-ID: <1462831480.20290.120.camel@kernel.crashing.org> (raw)
In-Reply-To: <20160509152003.GA13842@leverpostej>
On Mon, 2016-05-09 at 16:20 +0100, Mark Rutland wrote:
>
> Generally we steer clear of this kind of bitmap encoding in DT.
>
> Is this actually necessary? What does htis gain us?
>
> Why can we not just register with the full set of possible
> interrupts?
Trying to remember why I did that ... I think it has to do with
supporting multiple SoCs that have different possible sources...
There might also be a case of some sources routed to the internal
coldfire microcontroller or the LPC bus instead of the ARM but I'm not
100% certain.
Cheers,
Ben.
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next prev parent reply other threads:[~2016-05-09 22:04 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-09 12:33 [PATCH 0/2] irqchip: Support Aspeed IRQ controller Joel Stanley
[not found] ` <1462797239-14765-1-git-send-email-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
2016-05-09 12:33 ` [PATCH 1/2] doc/devicetree: Add Aspeed VIC bindings Joel Stanley
2016-05-09 12:50 ` Baruch Siach
2016-05-09 12:55 ` Arnd Bergmann
2016-05-09 15:20 ` Mark Rutland
2016-05-09 22:04 ` Benjamin Herrenschmidt [this message]
2016-05-09 12:33 ` [PATCH 2/2] irqchip: Add irq controller for Aspeed Joel Stanley
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