From mboxrd@z Thu Jan  1 00:00:00 1970
From: Priit Laes <plaes@plaes.org>
Subject: Re: [linux-sunxi] Re: [PATCH v4 01/11] clk: sunxi: Add display and
 TCON0 clocks driver
Date: Tue, 10 May 2016 22:10:59 +0300
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To: sboyd@codeaurora.org, Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mike Turquette <mturquette@baylibre.com>, David Airlie <airlied@linux.ie>, Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>, Daniel Vetter <daniel@ffwll.ch>, Hans de Goede <hdegoede@redhat.com>, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, dri-devel@lists.freedesktop.org, Boris Brezillon <boris.brezillon@free-electrons.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, Alexander Kaplan <alex@nextthing.co>, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
List-Id: devicetree@vger.kernel.org

On Mon, 2016-05-09 at 15:39 -0700, Stephen Boyd wrote:
> On 05/09, Stephen Boyd wrote:
> >=20
> >=20
> > Ok I applied this one to clk-next.
> >=20
> And I squashed this in to silence the following checker warning.
>=20
> drivers/clk/sunxi/clk-sun4i-display.c:110:33: warning: Variable
> length array is used.
>=20
> ---8<---
> diff --git a/drivers/clk/sunxi/clk-sun4i-display.c
> b/drivers/clk/sunxi/clk-sun4i-display.c
> index f02e250e64ed..f8ff6c4a5633 100644
> --- a/drivers/clk/sunxi/clk-sun4i-display.c
> +++ b/drivers/clk/sunxi/clk-sun4i-display.c
> @@ -107,7 +107,7 @@ static int sun4i_a10_display_reset_xlate(struct
> reset_controller_dev *rcdev,
> =C2=A0static void __init sun4i_a10_display_init(struct device_node *n=
ode,
> =C2=A0					=C2=A0=C2=A0const struct
> sun4i_a10_display_clk_data *data)
> =C2=A0{
> -	const char *parents[data->parents];
> +	const char *parents[4];
> =C2=A0	const char *clk_name =3D node->name;
> =C2=A0	struct reset_data *reset_data;
> =C2=A0	struct clk_divider *div =3D NULL;
> @@ -126,8 +126,8 @@ static void __init sun4i_a10_display_init(struct
> device_node *node,
> =C2=A0		return;
> =C2=A0	}
> =C2=A0
> -	ret =3D of_clk_parent_fill(node, parents, data->parents);
> -	if (ret !=3D data->parents) {
> +	ret =3D of_clk_parent_fill(node, parents,
> ARRAY_SIZE(parents));
> +	if (ret !=3D ARRAY_SIZE(parents)) {
> =C2=A0		pr_err("%s: Could not retrieve the parents\n",
> clk_name);
> =C2=A0		goto unmap;
> =C2=A0	}

This change breaks at least de_[bf]e clocks which have 3 clock parents.