[PATCH-V2 0/6] ARM: memory: bcm: add sdram driver

[PATCH-V2 0/6] ARM: memory: bcm: add sdram driver

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Add a sdram driver for the bcm2835 SOC.

This is needed (especially) as there are 2 clocks that are needed
by the SDram related HW block, which - right now are not claimed.

Without this driver there is a possibility that one of these
clocks (sdram (for low-voltage modes) or pll_core) or one of their
parents does get disabled when the clocks or PLLs are actually
needed.

In the current form of this driver there is still no absolute
certainty that such a situation can not happen under all
cirumstances, but it reduces the likleyhood that this happens.

To avoid this situation a patch-set will be needed that moves
bcm2835-clk and bcm2835-sdram to earlier stages during the
boot process.

The driver also claims the 3 necessary register ranges
to fully control the sdram (SDRAM, APHY, DPHY).

But for some reasons these registers are not accessible and
read as 0.

It is still unclear if this is a general feature of the SOC
or if this is configured by the binary-blob firmware.

That is why this patchset includes an optional patch
(patch 6: memory: bcm2835: expose register ranges via debugfs)
that exposes these register sets via debugfs.

Martin Sperl (6):
  dt: bindings: add bcm2835-memory-controller documentation
  memory: bcm2835: add bcm2835-memory controller
  ARM: dts: bcm2835: add the bcm2835-sdram-controller to the dt
  ARM: bcm2835_defconfig: add bcm2835-sdram controller
  ARM: multi_v7_defconfig: bcm2835: add bcm2835-sdram driver
  memory: bcm2835: expose register ranges via debugfs

 .../memory-controllers/brcm,bcm2835-sdram.txt      |  30 ++
 arch/arm/boot/dts/bcm283x.dtsi                     |  11 +
 arch/arm/configs/bcm2835_defconfig                 |   1 +
 arch/arm/configs/multi_v7_defconfig                |   1 +
 drivers/memory/Kconfig                             |   7 +
 drivers/memory/Makefile                            |   1 +
 drivers/memory/bcm2835-sdram.c                     | 464 +++++++++++++++++++++
 7 files changed, 515 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/brcm,bcm2835-sdram.txt
 create mode 100644 drivers/memory/bcm2835-sdram.c

--
2.1.4
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[PATCH-V2 1/6] dt: bindings: add bcm2835-memory-controller documentation

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Add memory controller dt-binding documentation for the
bcm2835 soc.

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Changelog:
  V2 -> V3: added additional clock
	      (for the Controller internal PLL)
	    added clock-names
	    added additional register ranges for the
	      SDRAM Adress and Data PHY
	    added reg-names
---
 .../memory-controllers/brcm,bcm2835-sdram.txt      | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/brcm,bcm2835-sdram.txt

diff --git a/Documentation/devicetree/bindings/memory-controllers/brcm,bcm2835-sdram.txt b/Documentation/devicetree/bindings/memory-controllers/brcm,bcm2835-sdram.txt
new file mode 100644
index 0000000..5c4182f
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/brcm,bcm2835-sdram.txt
@@ -0,0 +1,30 @@
+Binding for SDRAM driver for BCM2835 SoCs.
+
+Required parameters:
+-------------------
+
+compatible : 	should be: "brcm,bcm2835-sdram"
+reg :		Address range of the register-set:
+		  * SD
+		  * APHY_CSR
+		  * DPHY_CSR
+reg-names :	Names of the register ranges:
+		  "sdram", "aphy_csr", "dphy_csr"
+clocks : 	Phandle of the clocks used by the sdram
+		  * low voltage clock
+		  * pll parent clock
+clock-names:	Names of the clocks:
+		  "low-voltage", "pll-parent"
+
+Example:
+
+memory-conroller@7ee00000 {
+	compatible = "brcm,bcm2835-sdram";
+	reg = <0x7ee00000 0x18c>,
+	      <0x7ee06000 0x94>,
+	      <0x7ee07000 0x808>;
+	reg-names = "sdram", "aphy_csr", "dphy_csr";
+	clocks = <&clocks BCM2835_CLOCK_SDRAM>,
+		 <&clocks BCM2835_PLLD_CORE>;
+	clock-names = "low-voltage", "pll-parent";
+};
-- 
2.1.4

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Re: [PATCH-V2 1/6] dt: bindings: add bcm2835-memory-controller documentation

[Rob Herring]

On Wed, May 18, 2016 at 03:40:25PM +0000, kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org wrote:
> From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
> 
> Add memory controller dt-binding documentation for the
> bcm2835 soc.
> 
> Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
> 
> Changelog:
>   V2 -> V3: added additional clock
> 	      (for the Controller internal PLL)
> 	    added clock-names
> 	    added additional register ranges for the
> 	      SDRAM Adress and Data PHY
> 	    added reg-names
> ---
>  .../memory-controllers/brcm,bcm2835-sdram.txt      | 30 ++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/brcm,bcm2835-sdram.txt

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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[PATCH-V2 2/6] memory: bcm2835: add bcm2835-memory controller

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Add a memory-controller driver for the bcm2835 SOC.

This is mostly needed to claim the SDRAM clocks
so that this (and the corresponding parent pll)
never gets disabled.

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Changelog:
 V1->V2: moved to different register sets (that are also
     	  set up by the alternative boot loader to enable sdram)
	 added 2 distinct clocks (for low voltage and internal pll)
	 made the use of "names" for reg and clocks
---
 drivers/memory/Kconfig         |   7 +++
 drivers/memory/Makefile        |   1 +
 drivers/memory/bcm2835-sdram.c | 128 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 136 insertions(+)
 create mode 100644 drivers/memory/bcm2835-sdram.c

diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 51d5cd2..a55cad3 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -25,6 +25,13 @@ config ATMEL_SDRAMC
 	  Starting with the at91sam9g45, this controller supports SDR, DDR and
 	  LP-DDR memories.
 
+config BCM2835_SDRAM
+	bool "Broadcom BCM2835 SDRAM Controller"
+	default y
+	depends on ARCH_BCM2835 || COMPILE_TEST
+	help
+	  This driver is for Broadcom BCM2835 SDRAM Controller.
+
 config TI_AEMIF
 	tristate "Texas Instruments AEMIF driver"
 	depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 890bdf4..1287b90 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_OF)		+= of_memory.o
 endif
 obj-$(CONFIG_ARM_PL172_MPMC)	+= pl172.o
 obj-$(CONFIG_ATMEL_SDRAMC)	+= atmel-sdramc.o
+obj-$(CONFIG_BCM2835_SDRAM)	+= bcm2835-sdram.o
 obj-$(CONFIG_TI_AEMIF)		+= ti-aemif.o
 obj-$(CONFIG_TI_EMIF)		+= emif.o
 obj-$(CONFIG_OMAP_GPMC)		+= omap-gpmc.o
diff --git a/drivers/memory/bcm2835-sdram.c b/drivers/memory/bcm2835-sdram.c
new file mode 100644
index 0000000..ce985ee
--- /dev/null
+++ b/drivers/memory/bcm2835-sdram.c
@@ -0,0 +1,128 @@
+/*
+ * Driver for Broadcom BCM2835 soc sdram controller
+ *
+ * Copyright (C) 2016 Martin Sperl
+ *
+ * inspired by: atmel-sdramc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+struct bcm2835_sdram_data {
+	void __iomem	*sdram_regs;
+	void __iomem	*aphy_csr_regs;
+	void __iomem	*dphy_csr_regs;
+
+	struct clk	*clk_lv;
+	struct clk	*clk_pll_parent;
+};
+
+static int bcm2835_sdram_probe_reg(struct platform_device *pdev,
+				   const char *name,
+				   void __iomem **ptr)
+{
+	struct resource *res;
+	int err = 0;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+	if (!res) {
+		dev_err(&pdev->dev,
+			"Could not find register range %s\n",
+			name);
+		return -EINVAL;
+	}
+
+	*ptr = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(*ptr)) {
+		err = PTR_ERR(*ptr);
+		dev_err(&pdev->dev,
+			"Could not get register range %s: %d\n",
+			name, err);
+	}
+
+	return err;
+}
+
+static int bcm2835_sdram_probe(struct platform_device *pdev)
+{
+	struct bcm2835_sdram_data *data;
+	int ret;
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, data);
+
+	/* get registers */
+	ret = bcm2835_sdram_probe_reg(pdev, "sdram",
+				      &data->sdram_regs);
+	if (ret)
+		return ret;
+	ret = bcm2835_sdram_probe_reg(pdev, "aphy_csr",
+				      &data->aphy_csr_regs);
+	if (ret)
+		return ret;
+	ret = bcm2835_sdram_probe_reg(pdev, "dphy_csr",
+				      &data->dphy_csr_regs);
+	if (ret)
+		return ret;
+
+	/* get clocks */
+	data->clk_lv = devm_clk_get(&pdev->dev, "low-voltage");
+	if (IS_ERR(data->clk_lv)) {
+		ret = PTR_ERR(data->clk_lv);
+		dev_err(&pdev->dev, "Could not get clock named %s - %d\n",
+			"low-voltage", ret);
+		return ret;
+	}
+	data->clk_pll_parent = devm_clk_get(&pdev->dev, "pll-parent");
+	if (IS_ERR(data->clk_pll_parent)) {
+		ret = PTR_ERR(data->clk_pll_parent);
+		dev_err(&pdev->dev, "Could not get clock named %s - %d\n",
+			"pll-parent", ret);
+		return ret;
+	}
+
+	/* finally prepare both */
+	clk_prepare_enable(data->clk_lv);
+	clk_prepare_enable(data->clk_pll_parent);
+
+	return 0;
+}
+
+static const struct of_device_id bcm2835_sdram_of_match_table[] = {
+	{ .compatible = "brcm,bcm2835-sdram", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, bcm2835_sdram_of_match_table);
+
+static struct platform_driver bcm2835_sdram_driver = {
+	.probe = bcm2835_sdram_probe,
+	.driver = {
+		.name = "bcm2835_sdram",
+		.of_match_table = bcm2835_sdram_of_match_table,
+	},
+};
+module_platform_driver(bcm2835_sdram_driver);
+
+MODULE_AUTHOR("Martin Sperl");
+MODULE_DESCRIPTION("sdram driver for bcm2835 chip");
+MODULE_LICENSE("GPL");
-- 
2.1.4

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[PATCH-V2 3/6] ARM: dts: bcm2835: add the bcm2835-sdram-controller to the dt

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Add the bcm2835 sdram controller to the device tree.

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
---
 arch/arm/boot/dts/bcm283x.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 2b5cbc6..177045a 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -237,6 +237,17 @@
 			reg = <0x7e980000 0x10000>;
 			interrupts = <1 9>;
 		};
+
+		memory-conroller@7ee00000 {
+			compatible = "brcm,bcm2835-sdram";
+			reg = <0x7ee00000 0x18c>,
+			      <0x7ee06000 0x94>,
+			      <0x7ee07000 0x808>;
+			reg-names = "sdram", "aphy_csr", "dphy_csr";
+			clocks = <&clocks BCM2835_CLOCK_SDRAM>,
+				 <&clocks BCM2835_PLLD_CORE>;
+			clock-names = "low-voltage", "pll-parent";
+		};
 	};
 
 	clocks {
-- 
2.1.4

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[PATCH-V2 4/6] ARM: bcm2835_defconfig: add bcm2835-sdram controller

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Add the bcm2835-sdram controller driver to the default config.
(as the driver is enabled by default vi KConfig, we only need
to enable CONFIG_MEMORY)

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
---
 arch/arm/configs/bcm2835_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index f254d6b..634e07e 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -109,6 +109,7 @@ CONFIG_MAILBOX=y
 CONFIG_BCM2835_MBOX=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_RASPBERRYPI_POWER=y
+CONFIG_MEMORY=y
 CONFIG_PWM=y
 CONFIG_PWM_BCM2835=y
 CONFIG_RASPBERRYPI_FIRMWARE=y
-- 
2.1.4

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[PATCH-V2 5/6] ARM: multi_v7_defconfig: bcm2835: add bcm2835-sdram driver

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

ad the sdram driver of bcm2835 to the list of compiled
modules in multi_v7_defconfig

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 9108cc7..bd6d400 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -764,6 +764,7 @@ CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_PM_DEVFREQ=y
 CONFIG_ARM_TEGRA_DEVFREQ=m
 CONFIG_MEMORY=y
+CONFIG_BCM2835_SDRAM=y
 CONFIG_EXTCON=y
 CONFIG_TI_AEMIF=y
 CONFIG_IIO=y
-- 
2.1.4

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[PATCH-V2 6/6] memory: bcm2835: expose register ranges via debugfs

[kernel-TqfNSX0MhmxHKSADF0wUEw]

From: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>

Expose the assigned register ranges via debugfs.

For some reason these register ranges are reading as 0
when running with the binary firmware - this may be a limitation
introduced by the firmware or it may be something that
the SOC is blocking.

This is there just to allow/document those registers,
that are visible on the VC4/GPU side.

Signed-off-by: Martin Sperl <kernel-TqfNSX0MhmxHKSADF0wUEw@public.gmane.org>
---
 drivers/memory/bcm2835-sdram.c | 336 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 336 insertions(+)

diff --git a/drivers/memory/bcm2835-sdram.c b/drivers/memory/bcm2835-sdram.c
index ce985ee..9d8cce2 100644
--- a/drivers/memory/bcm2835-sdram.c
+++ b/drivers/memory/bcm2835-sdram.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/debugfs.h>
 #include <linux/device.h>
 #include <linux/err.h>
 #include <linux/io.h>
@@ -26,6 +27,140 @@
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
 
+/* the set of registers of the sdram controller */
+#define BCM2835_SD_CS		0x000
+#define BCM2835_SD_SA		0x004
+#define BCM2835_SD_SB		0x008
+#define BCM2835_SD_SC		0x00c
+#define BCM2835_SD_PT2		0x010
+#define BCM2835_SD_PT1		0x014
+#define BCM2835_SD_SECSRT0	0x03c
+#define BCM2835_SD_SECEND0	0x040
+#define BCM2835_SD_SECSRT1	0x044
+#define BCM2835_SD_SECEND1	0x048
+#define BCM2835_SD_SECSRT2	0x04c
+#define BCM2835_SD_SECEND2	0x050
+#define BCM2835_SD_SECSRT3	0x054
+#define BCM2835_SD_SECEND3	0x058
+#define BCM2835_SD_PHYC		0x060
+#define BCM2835_SD_MRT		0x064
+#define BCM2835_SD_TMC		0x07c
+#define BCM2835_SD_RWC		0x080
+#define BCM2835_SD_VIN		0x088
+#define BCM2835_SD_MR		0x090
+#define BCM2835_SD_SD		0x094
+#define BCM2835_SD_SE		0x098
+#define BCM2835_SD_STALL	0x0a0
+#define BCM2835_SD_SF		0x0b4
+#define BCM2835_SD_CARCRC	0x100
+#define BCM2835_SD_DMRCRC0	0x104
+#define BCM2835_SD_DMRCRC1	0x108
+#define BCM2835_SD_DQRCRC0	0x10c
+#define BCM2835_SD_DQRCRC1	0x110
+#define BCM2835_SD_DQRCRC2	0x114
+#define BCM2835_SD_DQRCRC3	0x118
+#define BCM2835_SD_DQRCRC4	0x11c
+#define BCM2835_SD_DQRCRC5	0x120
+#define BCM2835_SD_DQRCRC6	0x124
+#define BCM2835_SD_DQRCRC7	0x128
+#define BCM2835_SD_DQRCRC8	0x12c
+#define BCM2835_SD_DQRCRC9	0x130
+#define BCM2835_SD_DQRCRC10	0x134
+#define BCM2835_SD_DQRCRC11	0x138
+#define BCM2835_SD_DQRCRC12	0x13c
+#define BCM2835_SD_DQRCRC13	0x140
+#define BCM2835_SD_DQRCRC14	0x144
+#define BCM2835_SD_DQRCRC15	0x148
+#define BCM2835_SD_DQLCRC0	0x14c
+#define BCM2835_SD_DQLCRC1	0x150
+#define BCM2835_SD_DQLCRC2	0x154
+#define BCM2835_SD_DQLCRC3	0x158
+#define BCM2835_SD_DQLCRC4	0x15c
+#define BCM2835_SD_DQLCRC5	0x160
+#define BCM2835_SD_DQLCRC6	0x164
+#define BCM2835_SD_DQLCRC7	0x168
+#define BCM2835_SD_DQLCRC8	0x16c
+#define BCM2835_SD_DQLCRC9	0x170
+#define BCM2835_SD_DQLCRC10	0x174
+#define BCM2835_SD_DQLCRC11	0x178
+#define BCM2835_SD_DQLCRC12	0x17c
+#define BCM2835_SD_DQLCRC13	0x180
+#define BCM2835_SD_DQLCRC14	0x184
+#define BCM2835_SD_DQLCRC15	0x188
+
+/* the set of registers of the APHY_CSR, which also contains the pll */
+#define APHY_CSR_ADDR_REV_ID			0x000
+#define APHY_CSR_GLBL_ADDR_DLL_RESET		0x004
+#define APHY_CSR_GLBL_ADDR_DLL_RECAL		0x008
+#define APHY_CSR_GLBL_ADDR_DLL_CNTRL		0x00c
+#define APHY_CSR_GLBL_ADDR_DLL_PH_LD_VAL	0x010
+#define APHY_CSR_ADDR_MASTER_DLL_OUTPUT		0x014
+#define APHY_CSR_ADDR_SLAVE_DLL_OFFSET		0x018
+#define APHY_CSR_GLBL_ADR_MSTR_DLL_BYPEN	0x01c
+#define APHY_CSR_GLBL_ADR_DLL_LOCK_STAT		0x020
+#define APHY_CSR_DDR_PLL_GLOBAL_RESET		0x024
+#define APHY_CSR_DDR_PLL_POST_DIV_RESET		0x028
+#define APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0	0x02c
+#define APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1	0x030
+#define APHY_CSR_DDR_PLL_MDIV_VALUE		0x034
+#define APHY_CSR_DDR_PLL_CONFIG_CNTRL		0x038
+#define APHY_CSR_DDR_PLL_MISC_CNTRL		0x03c
+#define APHY_CSR_DDR_PLL_SPRDSPECT_CTRL0	0x040
+#define APHY_CSR_DDR_PLL_SPRDSPECT_CTRL1	0x044
+#define APHY_CSR_DDR_PLL_LOCK_STATUS		0x048
+#define APHY_CSR_DDR_PLL_HOLD_CH		0x04c
+#define APHY_CSR_DDR_PLL_ENABLE_CH		0x050
+#define APHY_CSR_DDR_PLL_BYPASS			0x054
+#define APHY_CSR_DDR_PLL_PWRDWN			0x058
+#define APHY_CSR_DDR_PLL_CH0_DESKEW_CTRL	0x05c
+#define APHY_CSR_DDR_PLL_CH1_DESKEW_CTRL	0x060
+#define APHY_CSR_DDR_PLL_DESKEW_STATUS		0x064
+#define APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL		0x068
+#define APHY_CSR_ADDR_PAD_MISC_CTRL		0x06c
+#define APHY_CSR_ADDR_PVT_COMP_CTRL		0x070
+#define APHY_CSR_ADDR_PVT_COMP_OVRD_CTRL	0x074
+#define APHY_CSR_ADDR_PVT_COMP_STATUS		0x078
+#define APHY_CSR_ADDR_PVT_COMP_DEBUG		0x07c
+#define APHY_CSR_PHY_BIST_CNTRL_SPR		0x080
+#define APHY_CSR_PHY_BIST_CA_CRC_SPR		0x084
+#define APHY_CSR_ADDR_SPR0_RW			0x088
+#define APHY_CSR_ADDR_SPR1_RO			0x08c
+#define APHY_CSR_ADDR_SPR_RO			0x090
+
+/* the set of registers of the DPHY_CSR */
+#define DPHY_CSR_DQ_REV_ID			0x000
+#define DPHY_CSR_GLBL_DQ_DLL_RESET		0x004
+#define DPHY_CSR_GLBL_DQ_DLL_RECALIBRATE	0x008
+#define DPHY_CSR_GLBL_DQ_DLL_CNTRL		0x00c
+#define DPHY_CSR_GLBL_DQ_DLL_PHASE_LD_VL	0x010
+#define DPHY_CSR_GLBL_DQ_MSTR_DLL_BYP_EN	0x014
+#define DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT	0x018
+#define DPHY_CSR_BYTE0_SLAVE_DLL_OFFSET		0x01c
+#define DPHY_CSR_BYTE1_SLAVE_DLL_OFFSET		0x020
+#define DPHY_CSR_BYTE2_SLAVE_DLL_OFFSET		0x024
+#define DPHY_CSR_BYTE3_SLAVE_DLL_OFFSET		0x028
+#define DPHY_CSR_BYTE0_MASTER_DLL_OUTPUT	0x02c
+#define DPHY_CSR_BYTE1_MASTER_DLL_OUTPUT	0x030
+#define DPHY_CSR_BYTE2_MASTER_DLL_OUTPUT	0x034
+#define DPHY_CSR_BYTE3_MASTER_DLL_OUTPUT	0x038
+#define DPHY_CSR_NORM_READ_DQS_GATE_CTRL	0x03c
+#define DPHY_CSR_BOOT_READ_DQS_GATE_CTRL	0x040
+#define DPHY_CSR_PHY_FIFO_PNTRS			0x044
+#define DPHY_CSR_DQ_PHY_MISC_CTRL		0x048
+#define DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL		0x04c
+#define DPHY_CSR_DQ_PAD_MISC_CTRL		0x050
+#define DPHY_CSR_DQ_PVT_COMP_CTRL		0x054
+#define DPHY_CSR_DQ_PVT_COMP_OVERRD_CTRL	0x058
+#define DPHY_CSR_DQ_PVT_COMP_STATUS		0x05c
+#define DPHY_CSR_DQ_PVT_COMP_DEBUG		0x060
+#define DPHY_CSR_DQ_PHY_READ_CTRL		0x064
+#define DPHY_CSR_DQ_PHY_READ_STATUS		0x068
+#define DPHY_CSR_DQ_SPR_RW			0x06c
+#define DPHY_CSR_DQ_SPR1_RO			0x070
+#define DPHY_CSR_DQ_SPR_RO			0x074
+#define DPHY_CSR_CRC_CTRL			0x800
+#define DPHY_CSR_CRC_DATA			0x804
+
 struct bcm2835_sdram_data {
 	void __iomem	*sdram_regs;
 	void __iomem	*aphy_csr_regs;
@@ -33,8 +168,196 @@ struct bcm2835_sdram_data {
 
 	struct clk	*clk_lv;
 	struct clk	*clk_pll_parent;
+
+	struct dentry	*debugfsdir;
+};
+
+#define R(n, o) { .name = n, .offset = o }
+static const struct debugfs_reg32 bcm2835_sdram_regs[] = {
+	R("cs",		BCM2835_SD_CS),
+	R("sa",		BCM2835_SD_SA),
+	R("sb",		BCM2835_SD_SB),
+	R("sc",		BCM2835_SD_SC),
+	R("pt2",	BCM2835_SD_PT2),
+	R("pt1",	BCM2835_SD_PT1),
+	R("secsrt0",	BCM2835_SD_SECSRT0),
+	R("secend0",	BCM2835_SD_SECEND0),
+	R("secsrt1",	BCM2835_SD_SECSRT1),
+	R("secend1",	BCM2835_SD_SECEND1),
+	R("secsrt2",	BCM2835_SD_SECSRT2),
+	R("secend2",	BCM2835_SD_SECEND2),
+	R("secsrt3",	BCM2835_SD_SECSRT3),
+	R("secend3",	BCM2835_SD_SECEND3),
+	R("phyc",	BCM2835_SD_PHYC),
+	R("mrt",	BCM2835_SD_MRT),
+	R("tmc",	BCM2835_SD_TMC),
+	R("rwc",	BCM2835_SD_RWC),
+	R("vin",	BCM2835_SD_VIN),
+	/*
+	 * this is not exposed as this may result in races with
+	 * a parallel read - possibly by the firmware:
+	 * R("mr",		BCM2835_SD_MR),
+	 */
+	R("sd",		BCM2835_SD_SD),
+	R("se",		BCM2835_SD_SE),
+	R("stall",	BCM2835_SD_STALL),
+	R("sf",		BCM2835_SD_SF),
+	R("carcrc",	BCM2835_SD_CARCRC),
+	R("dmrcrc0",	BCM2835_SD_DMRCRC0),
+	R("dmrcrc1",	BCM2835_SD_DMRCRC1),
+	R("dqrcrc0",	BCM2835_SD_DQRCRC0),
+	R("dqrcrc1",	BCM2835_SD_DQRCRC1),
+	R("dqrcrc2",	BCM2835_SD_DQRCRC2),
+	R("dqrcrc3",	BCM2835_SD_DQRCRC3),
+	R("dqrcrc4",	BCM2835_SD_DQRCRC4),
+	R("dqrcrc5",	BCM2835_SD_DQRCRC5),
+	R("dqrcrc6",	BCM2835_SD_DQRCRC6),
+	R("dqrcrc7",	BCM2835_SD_DQRCRC7),
+	R("dqrcrc8",	BCM2835_SD_DQRCRC8),
+	R("dqrcrc9",	BCM2835_SD_DQRCRC9),
+	R("dqrcrc10",	BCM2835_SD_DQRCRC10),
+	R("dqrcrc11",	BCM2835_SD_DQRCRC11),
+	R("dqrcrc12",	BCM2835_SD_DQRCRC12),
+	R("dqrcrc13",	BCM2835_SD_DQRCRC13),
+	R("dqrcrc14",	BCM2835_SD_DQRCRC14),
+	R("dqrcrc15",	BCM2835_SD_DQRCRC15),
+	R("dqlcrc0",	BCM2835_SD_DQLCRC0),
+	R("dqlcrc1",	BCM2835_SD_DQLCRC1),
+	R("dqlcrc2",	BCM2835_SD_DQLCRC2),
+	R("dqlcrc3",	BCM2835_SD_DQLCRC3),
+	R("dqlcrc4",	BCM2835_SD_DQLCRC4),
+	R("dqlcrc5",	BCM2835_SD_DQLCRC5),
+	R("dqlcrc6",	BCM2835_SD_DQLCRC6),
+	R("dqlcrc7",	BCM2835_SD_DQLCRC7),
+	R("dqlcrc8",	BCM2835_SD_DQLCRC8),
+	R("dqlcrc9",	BCM2835_SD_DQLCRC9),
+	R("dqlcrc10",	BCM2835_SD_DQLCRC10),
+	R("dqlcrc11",	BCM2835_SD_DQLCRC11),
+	R("dqlcrc12",	BCM2835_SD_DQLCRC12),
+	R("dqlcrc13",	BCM2835_SD_DQLCRC13),
+	R("dqlcrc14",	BCM2835_SD_DQLCRC14),
+	R("dqlcrc15",	BCM2835_SD_DQLCRC15)
+};
+
+static const struct debugfs_reg32 bcm2835_aphy_csr_regs[] = {
+	R("addr_rev_id",		APHY_CSR_ADDR_REV_ID),
+	R("glbl_addr_dll_reset",	APHY_CSR_GLBL_ADDR_DLL_RESET),
+	R("glbl_addr_dll_recal",	APHY_CSR_GLBL_ADDR_DLL_RECAL),
+	R("glbl_addr_dll_cntrl",	APHY_CSR_GLBL_ADDR_DLL_CNTRL),
+	R("glbl_addr_dll_ph_ld_val",	APHY_CSR_GLBL_ADDR_DLL_PH_LD_VAL),
+	R("addr_master_dll_output",	APHY_CSR_ADDR_MASTER_DLL_OUTPUT),
+	R("addr_slave_dll_offset",	APHY_CSR_ADDR_SLAVE_DLL_OFFSET),
+	R("glbl_adr_mstr_dll_bypen",	APHY_CSR_GLBL_ADR_MSTR_DLL_BYPEN),
+	R("glbl_adr_dll_lock_stat",	APHY_CSR_GLBL_ADR_DLL_LOCK_STAT),
+	R("ddr_pll_global_reset",	APHY_CSR_DDR_PLL_GLOBAL_RESET),
+	R("ddr_pll_post_div_reset",	APHY_CSR_DDR_PLL_POST_DIV_RESET),
+	R("ddr_pll_vco_freq_cntrl0",	APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0),
+	R("ddr_pll_vco_freq_cntrl1",	APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1),
+	R("ddr_pll_mdiv_value",		APHY_CSR_DDR_PLL_MDIV_VALUE),
+	R("ddr_pll_config_cntrl",	APHY_CSR_DDR_PLL_CONFIG_CNTRL),
+	R("ddr_pll_misc_cntrl",		APHY_CSR_DDR_PLL_MISC_CNTRL),
+	R("ddr_pll_sprdspect_ctrl0",	APHY_CSR_DDR_PLL_SPRDSPECT_CTRL0),
+	R("ddr_pll_sprdspect_ctrl1",	APHY_CSR_DDR_PLL_SPRDSPECT_CTRL1),
+	R("ddr_pll_lock_status",	APHY_CSR_DDR_PLL_LOCK_STATUS),
+	R("ddr_pll_hold_ch",		APHY_CSR_DDR_PLL_HOLD_CH),
+	R("ddr_pll_enable_ch",		APHY_CSR_DDR_PLL_ENABLE_CH),
+	R("ddr_pll_bypass",		APHY_CSR_DDR_PLL_BYPASS),
+	R("ddr_pll_pwrdwn",		APHY_CSR_DDR_PLL_PWRDWN),
+	R("ddr_pll_ch0_deskew_ctrl",	APHY_CSR_DDR_PLL_CH0_DESKEW_CTRL),
+	R("ddr_pll_ch1_deskew_ctrl",	APHY_CSR_DDR_PLL_CH1_DESKEW_CTRL),
+	R("ddr_pll_deskew_status",	APHY_CSR_DDR_PLL_DESKEW_STATUS),
+	R("addr_pad_drv_slew_ctrl",	APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL),
+	R("addr_pad_misc_ctrl",		APHY_CSR_ADDR_PAD_MISC_CTRL),
+	R("addr_pvt_comp_ctrl",		APHY_CSR_ADDR_PVT_COMP_CTRL),
+	R("addr_pvt_comp_ovrd_ctrl",	APHY_CSR_ADDR_PVT_COMP_OVRD_CTRL),
+	R("addr_pvt_comp_status",	APHY_CSR_ADDR_PVT_COMP_STATUS),
+	R("addr_pvt_comp_debug",	APHY_CSR_ADDR_PVT_COMP_DEBUG),
+	R("phy_bist_cntrl_spr",		APHY_CSR_PHY_BIST_CNTRL_SPR),
+	R("phy_bist_ca_crc_spr",	APHY_CSR_PHY_BIST_CA_CRC_SPR),
+	R("addr_spr0_rw",		APHY_CSR_ADDR_SPR0_RW),
+	R("addr_spr1_ro",		APHY_CSR_ADDR_SPR1_RO),
+	R("addr_spr_ro",		APHY_CSR_ADDR_SPR_RO)
+};
+
+static const struct debugfs_reg32 bcm2835_dphy_csr_regs[] = {
+	R("dq_rev_id",			DPHY_CSR_DQ_REV_ID),
+	R("glbl_dq_dll_reset",		DPHY_CSR_GLBL_DQ_DLL_RESET),
+	R("glbl_dq_dll_recalibrate",	DPHY_CSR_GLBL_DQ_DLL_RECALIBRATE),
+	R("glbl_dq_dll_cntrl",		DPHY_CSR_GLBL_DQ_DLL_CNTRL),
+	R("glbl_dq_dll_phase_ld_vl",	DPHY_CSR_GLBL_DQ_DLL_PHASE_LD_VL),
+	R("glbl_dq_mstr_dll_byp_en",	DPHY_CSR_GLBL_DQ_MSTR_DLL_BYP_EN),
+	R("glbl_mstr_dll_lock_stat",	DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT),
+	R("byte0_slave_dll_offset",	DPHY_CSR_BYTE0_SLAVE_DLL_OFFSET),
+	R("byte1_slave_dll_offset",	DPHY_CSR_BYTE1_SLAVE_DLL_OFFSET),
+	R("byte2_slave_dll_offset",	DPHY_CSR_BYTE2_SLAVE_DLL_OFFSET),
+	R("byte3_slave_dll_offset",	DPHY_CSR_BYTE3_SLAVE_DLL_OFFSET),
+	R("byte0_master_dll_output",	DPHY_CSR_BYTE0_MASTER_DLL_OUTPUT),
+	R("byte1_master_dll_output",	DPHY_CSR_BYTE1_MASTER_DLL_OUTPUT),
+	R("byte2_master_dll_output",	DPHY_CSR_BYTE2_MASTER_DLL_OUTPUT),
+	R("byte3_master_dll_output",	DPHY_CSR_BYTE3_MASTER_DLL_OUTPUT),
+	R("norm_read_dqs_gate_ctrl",	DPHY_CSR_NORM_READ_DQS_GATE_CTRL),
+	R("boot_read_dqs_gate_ctrl",	DPHY_CSR_BOOT_READ_DQS_GATE_CTRL),
+	R("phy_fifo_pntrs",		DPHY_CSR_PHY_FIFO_PNTRS),
+	R("dq_phy_misc_ctrl",		DPHY_CSR_DQ_PHY_MISC_CTRL),
+	R("dq_pad_drv_slew_ctrl",	DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL),
+	R("dq_pad_misc_ctrl",		DPHY_CSR_DQ_PAD_MISC_CTRL),
+	R("dq_pvt_comp_ctrl",		DPHY_CSR_DQ_PVT_COMP_CTRL),
+	R("dq_pvt_comp_overrd_ctrl",	DPHY_CSR_DQ_PVT_COMP_OVERRD_CTRL),
+	R("dq_pvt_comp_status",		DPHY_CSR_DQ_PVT_COMP_STATUS),
+	R("dq_pvt_comp_debug",		DPHY_CSR_DQ_PVT_COMP_DEBUG),
+	R("dq_phy_read_ctrl",		DPHY_CSR_DQ_PHY_READ_CTRL),
+	R("dq_phy_read_status",		DPHY_CSR_DQ_PHY_READ_STATUS),
+	R("dq_spr_rw",			DPHY_CSR_DQ_SPR_RW),
+	R("dq_spr1_ro",			DPHY_CSR_DQ_SPR1_RO),
+	R("dq_spr_ro",			DPHY_CSR_DQ_SPR_RO),
+	R("crc_ctrl",			DPHY_CSR_CRC_CTRL),
+	R("crc_data",			DPHY_CSR_CRC_DATA),
 };
 
+static void bcm2835_sdram_debugfs_regset(struct platform_device *pdev,
+					 const char *name,
+					 const struct debugfs_reg32 *reg32,
+					 size_t size,
+					 void *base)
+{
+	struct bcm2835_sdram_data *data = platform_get_drvdata(pdev);
+	struct debugfs_regset32 *regset;
+
+	regset = devm_kzalloc(&pdev->dev, sizeof(*regset),
+			      GFP_KERNEL);
+	if (!regset)
+		return;
+
+	regset->regs = reg32;
+	regset->nregs = size;
+	regset->base = base;
+
+	debugfs_create_regset32(name, S_IRUGO,
+				data->debugfsdir, regset);
+}
+
+static void bcm2835_sdram_debugfs(struct platform_device *pdev)
+{
+	struct bcm2835_sdram_data *data = platform_get_drvdata(pdev);
+
+	data->debugfsdir = debugfs_create_dir("bcm2835_sdram", NULL);
+	if (!data->debugfsdir)
+		return;
+
+	bcm2835_sdram_debugfs_regset(pdev, "sdram-regset",
+				     bcm2835_sdram_regs,
+				     ARRAY_SIZE(bcm2835_sdram_regs),
+				     data->sdram_regs);
+	bcm2835_sdram_debugfs_regset(pdev, "aphy_csr-regset",
+				     bcm2835_aphy_csr_regs,
+				     ARRAY_SIZE(bcm2835_aphy_csr_regs),
+				     data->aphy_csr_regs);
+	bcm2835_sdram_debugfs_regset(pdev, "dphy_csr-regset",
+				     bcm2835_dphy_csr_regs,
+				     ARRAY_SIZE(bcm2835_dphy_csr_regs),
+				     data->dphy_csr_regs);
+}
+
 static int bcm2835_sdram_probe_reg(struct platform_device *pdev,
 				   const char *name,
 				   void __iomem **ptr)
@@ -105,6 +428,18 @@ static int bcm2835_sdram_probe(struct platform_device *pdev)
 	clk_prepare_enable(data->clk_lv);
 	clk_prepare_enable(data->clk_pll_parent);
 
+	/* setup debugfs */
+	bcm2835_sdram_debugfs(pdev);
+
+	return 0;
+}
+
+static int bcm2835_sdram_remove(struct platform_device *pdev)
+{
+	struct bcm2835_sdram_data *data = platform_get_drvdata(pdev);
+
+	debugfs_remove_recursive(data->debugfsdir);
+
 	return 0;
 }
 
@@ -116,6 +451,7 @@ MODULE_DEVICE_TABLE(of, bcm2835_sdram_of_match_table);
 
 static struct platform_driver bcm2835_sdram_driver = {
 	.probe = bcm2835_sdram_probe,
+	.remove = bcm2835_sdram_remove,
 	.driver = {
 		.name = "bcm2835_sdram",
 		.of_match_table = bcm2835_sdram_of_match_table,
-- 
2.1.4

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