From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subject: [PATCHv2 5/8] ARM: socfpga: dts: Add SPI Master1 for Arria10 SR chip Date: Thu, 2 Jun 2016 12:52:25 -0500 Message-ID: <1464889948-28793-6-git-send-email-tthayer@opensource.altera.com> References: <1464889948-28793-1-git-send-email-tthayer@opensource.altera.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1464889948-28793-1-git-send-email-tthayer@opensource.altera.com> Sender: linux-gpio-owner@vger.kernel.org To: lee.jones@linaro.org, linus.walleij@linaro.org, gnurou@gmail.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, dinguyen@opensource.altera.com Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Thor Thayer List-Id: devicetree@vger.kernel.org From: Thor Thayer Add the Altera Arria10 SPI Master Node in preparation for the A10SR MFD node. Signed-off-by: Thor Thayer --- v2: No change --- arch/arm/boot/dts/socfpga_arria10.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 17e81dc..e7b6c4a 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -567,6 +567,21 @@ status = "disabled"; }; + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x100>; + interrupts = <0 102 4>; + num-chipselect = <4>; + bus-num = <0>; + /*32bit_access;*/ + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + sdr: sdr@ffc25000 { compatible = "syscon"; reg = <0xffcfb100 0x80>; -- 1.7.9.5