From mboxrd@z Thu Jan 1 00:00:00 1970 From: Geert Uytterhoeven Subject: [PATCH v4 01/13] devicetree: bindings: Renesas APMU and SMP Enable method Date: Thu, 16 Jun 2016 12:27:30 +0200 Message-ID: <1466072862-28030-2-git-send-email-geert+renesas@glider.be> References: <1466072862-28030-1-git-send-email-geert+renesas@glider.be> Return-path: In-Reply-To: <1466072862-28030-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org To: Simon Horman , Magnus Damm Cc: Mark Rutland , Lorenzo Pieralisi , Keita Kobayashi , Laurent Pinchart , Sergei Shtylyov , linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Magnus Damm , Geert Uytterhoeven , Rob Herring , devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org From: Magnus Damm Add DT binding documentation for the APMU hardware and add "renesas,apmu" to the list of enable methods for the ARM cpus. Signed-off-by: Magnus Damm Signed-off-by: Geert Uytterhoeven Cc: Rob Herring Cc: devicetree@vger.kernel.org --- v4: - s/reigsters/registers/, - Use "renesas,-apmu" instead of "renesas,apmu-", v3: - s/Until/Unit/g, v2: - No changes. --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + .../devicetree/bindings/power/renesas,apmu.txt | 31 ++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/renesas,apmu.txt diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 3f0cbbb8395f84ef..fa7520eb6387edbe 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -204,6 +204,7 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "renesas,apmu" "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp" diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt new file mode 100644 index 0000000000000000..84404c9edff73d97 --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt @@ -0,0 +1,31 @@ +DT bindings for the Renesas Advanced Power Management Unit + +Renesas R-Car line of SoCs utilize one or more APMU hardware units +for CPU core power domain control including SMP boot and CPU Hotplug. + +Required properties: + +- compatible: Should be "renesas,-apmu", "renesas,apmu" as fallback. + Examples with soctypes are: + - "renesas,r8a7790-apmu" (R-Car H2) + - "renesas,r8a7791-apmu" (R-Car M2-W) + - "renesas,r8a7792-apmu" (R-Car V2H) + - "renesas,r8a7793-apmu" (R-Car M2-N) + - "renesas,r8a7794-apmu" (R-Car E2) + +- reg: Base address and length of the I/O registers used by the APMU. + +- cpus: This node contains a list of CPU cores, which should match the order + of CPU cores used by the WUPCR and PSTR registers in the Advanced Power + Management Unit section of the device's datasheet. + + +Example: + +This shows the r8a7791 APMU that can control CPU0 and CPU1. + + apmu@e6152000 { + compatible = "renesas,r8a7791-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; -- 1.9.1