* [PATCH 1/3] dt-bindings: auxadc: Add binding document for Mediatek auxadc.
2016-06-24 7:37 [PATCH 0/3] AUXADC: Mediatek auxadc driver zhiyong.tao
@ 2016-06-24 7:37 ` zhiyong.tao
2016-06-24 7:37 ` [PATCH 2/3] auxadc: Add Mediatek auxadc driver for mt2701 zhiyong.tao
2016-06-24 7:37 ` [PATCH 3/3] arm: dts: auxadc: Add auxadc node zhiyong.tao
2 siblings, 0 replies; 4+ messages in thread
From: zhiyong.tao @ 2016-06-24 7:37 UTC (permalink / raw)
To: robh+dt, jic23, knaack.h, lars, pmeerw
Cc: srv_heupstream, liguo.zhang, yingjoe.chen, eddie.huang, erin.lo,
dawei.chien, matthias.bgg, s.hauer, devicetree, linux-kernel,
linux-arm-kernel, linux-iio, linux-mediatek, Zhiyong Tao
[-- Attachment #1.1: Type: text/html, Size: 4226 bytes --]
[-- Attachment #1.2: Type: text/plain, Size: 3136 bytes --]
From: Zhiyong Tao <zhiyong.tao@mediatek.com>
The commit adds the device tree binding documentation for the mediatek
auxadc found on Mediatek MT2701.
Thermal gets auxadc sample data by iio device.
So the commit changes auxadc device tree binding documentation from
/soc/mediatek/auxadc.txt to /iio/adc/mt65xx_auxadc.txt.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
---
.../devicetree/bindings/iio/adc/mt65xx_auxadc.txt | 27
++++++++++++++++++++
.../devicetree/bindings/soc/mediatek/auxadc.txt | 21 ---------------
2 files changed, 27 insertions(+), 21 deletions(-)
create mode 100644
Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
delete mode 100644
Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
b/Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
new file mode 100644
index 0000000..47fcd1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/mt65xx_auxadc.txt
@@ -0,0 +1,27 @@
+* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc
(mt65xx/mt81xx/mt27xx)
+===============
+
+The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
+in some Mediatek SoCs which among other things measures the temperatures
+in the SoC. It can be used directly with register accesses, but it is also
+used by thermal controller which reads the temperatures from the AUXADC
+directly via its own bus interface. See
+Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
+for the Thermal Controller which holds a phandle to the AUXADC.
+
+Required properties:
+ - compatible: "mediatek,mt2701-auxadc" or "mediatek,mt8173-auxadc"
+ - reg: Address range of the AUXADC unit.
+ - clocks: Should contain a clock specifier for each entry in clock-names
+ - clock-names: Should contain "main".
+ - io-channel-cells: Should be 1, see ../iio-bindings.txt
+
+Example:
+
+auxadc: auxadc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
b/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
deleted file mode 100644
index bdb7829..0000000
--- a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-MediaTek AUXADC
-===============
-
-The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
-in some Mediatek SoCs which among other things measures the temperatures
-in the SoC. It can be used directly with register accesses, but it is also
-used by thermal controller which reads the temperatures from the AUXADC
-directly via its own bus interface. See
-Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
-for the Thermal Controller which holds a phandle to the AUXADC.
-
-Required properties:
-- compatible: Must be "mediatek,mt8173-auxadc"
-- reg: Address range of the AUXADC unit
-
-Example:
-
-auxadc: auxadc@11001000 {
- compatible = "mediatek,mt8173-auxadc";
- reg = <0 0x11001000 0 0x1000>;
-};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/3] auxadc: Add Mediatek auxadc driver for mt2701.
2016-06-24 7:37 [PATCH 0/3] AUXADC: Mediatek auxadc driver zhiyong.tao
2016-06-24 7:37 ` [PATCH 1/3] dt-bindings: auxadc: Add binding document for Mediatek auxadc zhiyong.tao
@ 2016-06-24 7:37 ` zhiyong.tao
2016-06-24 7:37 ` [PATCH 3/3] arm: dts: auxadc: Add auxadc node zhiyong.tao
2 siblings, 0 replies; 4+ messages in thread
From: zhiyong.tao @ 2016-06-24 7:37 UTC (permalink / raw)
To: robh+dt, jic23, knaack.h, lars, pmeerw
Cc: srv_heupstream, liguo.zhang, yingjoe.chen, eddie.huang, erin.lo,
dawei.chien, matthias.bgg, s.hauer, devicetree, linux-kernel,
linux-arm-kernel, linux-iio, linux-mediatek, Zhiyong Tao
[-- Attachment #1.1: Type: text/html, Size: 11574 bytes --]
[-- Attachment #1.2: Type: text/plain, Size: 9866 bytes --]
From: Zhiyong Tao <zhiyong.tao@mediatek.com>
Add Mediatek auxadc driver in iio.
It will register a device in iio and support iio.
So thermal can read auxadc channel to sample data by iio device.
It is tested successfully on mt2701 platform.
Mt8173 platform is not tested. But the expectation is compatible.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
---
drivers/iio/adc/Kconfig | 11 ++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/mt65xx_auxadc.c | 269
+++++++++++++++++++++++++++++++++++++++
3 files changed, 281 insertions(+)
create mode 100644 drivers/iio/adc/mt65xx_auxadc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 25378c5..7684849 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -315,6 +315,17 @@ config MEN_Z188_ADC
This driver can also be built as a module. If so, the module will be
called men_z188_adc.
+config MEDIATEK_MT65XX_AUXADC
+ tristate "MediaTek AUXADC driver"
+ help
+ Say yes here to enable support for MediaTek mt65xx AUXADC.
+
+ The driver supports immediate mode operation to read from one of sixteen
+ channels (external or internal).
+
+ This driver can also be built as a module. If so, the module will be
+ called mt65xx_auxadc.
+
config MXS_LRADC
tristate "Freescale i.MX23/i.MX28 LRADC"
depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 38638d4..bc62209 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_MAX1363) += max1363.o
obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
+obj-$(CONFIG_MEDIATEK_MT65XX_AUXADC) += mt65xx_auxadc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
diff --git a/drivers/iio/adc/mt65xx_auxadc.c
b/drivers/iio/adc/mt65xx_auxadc.c
new file mode 100644
index 0000000..b3c059c
--- /dev/null
+++ b/drivers/iio/adc/mt65xx_auxadc.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/iopoll.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+
+/* Registers define*/
+#define MT65XX_AUXADC_CON0 0x00
+#define MT65XX_AUXADC_CON1 0x04
+#define MT65XX_AUXADC_CON2 0x10
+#define MT65XX_AUXADC_STA BIT(0)
+
+#define MT65XX_AUXADC_DAT0 0x14
+#define MT65XX_AUXADC_RDY0 BIT(12)
+
+#define MT65XX_AUXADC_MISC 0x94
+#define MT65XX_AUXADC_PDN_EN BIT(14)
+
+#define MT65XX_AUXADC_DAT_MASK 0xfff
+#define MT65XX_AUXADC_SLEEP_US 1000
+#define MT65XX_AUXADC_TIMEOUT_US 10000
+#define MT65XX_AUXADC_POWER_READY_MS 1
+#define MT65XX_AUXADC_SAMPLE_READY_US 25
+
+struct mt65xx_auxadc_device {
+ void __iomem *reg_base;
+ struct clk *adc_clk;
+ struct mutex lock; /*generic mutex for auxadc driver*/
+ unsigned int power_ready_ms;
+ unsigned int sample_ready_us;
+};
+
+#define MT65xx_AUXADC_CHANNEL(idx) { \
+ .type = IIO_VOLTAGE, \
+ .indexed = 1, \
+ .channel = (idx), \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_OFFSET), \
+}
+
+static const struct iio_chan_spec mt65xx_auxadc_iio_channels[] = {
+ MT65xx_AUXADC_CHANNEL(0),
+ MT65xx_AUXADC_CHANNEL(1),
+ MT65xx_AUXADC_CHANNEL(2),
+ MT65xx_AUXADC_CHANNEL(3),
+ MT65xx_AUXADC_CHANNEL(4),
+ MT65xx_AUXADC_CHANNEL(5),
+ MT65xx_AUXADC_CHANNEL(6),
+ MT65xx_AUXADC_CHANNEL(7),
+ MT65xx_AUXADC_CHANNEL(8),
+ MT65xx_AUXADC_CHANNEL(9),
+ MT65xx_AUXADC_CHANNEL(10),
+ MT65xx_AUXADC_CHANNEL(11),
+ MT65xx_AUXADC_CHANNEL(12),
+ MT65xx_AUXADC_CHANNEL(13),
+ MT65xx_AUXADC_CHANNEL(14),
+ MT65xx_AUXADC_CHANNEL(15),
+};
+
+static int mt65xx_auxadc_read(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan)
+{
+ u32 rawdata, val;
+ void __iomem *reg_channel;
+ struct mt65xx_auxadc_device *adc_dev = iio_priv(indio_dev);
+
+ reg_channel = adc_dev->reg_base + MT65XX_AUXADC_DAT0 +
+ chan->channel * 0x04;
+
+ mutex_lock(&adc_dev->lock);
+
+ val = readl(adc_dev->reg_base + MT65XX_AUXADC_CON1);
+ val &= ~(1 << chan->channel);
+ writel(val, adc_dev->reg_base + MT65XX_AUXADC_CON1);
+
+ /* read channel and make sure old ready bit ==0 */
+ readl_poll_timeout(reg_channel, val,
+ ((val & MT65XX_AUXADC_RDY0) == 0),
+ MT65XX_AUXADC_SLEEP_US,
+ MT65XX_AUXADC_TIMEOUT_US);
+
+ /* set bit to trigger sample */
+ val = readl(adc_dev->reg_base + MT65XX_AUXADC_CON1);
+ val |= 1 << chan->channel;
+ writel(val, adc_dev->reg_base + MT65XX_AUXADC_CON1);
+
+ /* we must delay here for hardware sample channel data */
+ udelay(adc_dev->sample_ready_us);
+
+ /* check MTK_AUXADC_CON2 if auxadc is idle */
+ readl_poll_timeout(adc_dev->reg_base + MT65XX_AUXADC_CON2, val,
+ ((val & MT65XX_AUXADC_STA) == 0),
+ MT65XX_AUXADC_SLEEP_US,
+ MT65XX_AUXADC_TIMEOUT_US);
+
+ /* read channel and make sure ready bit ==1 */
+ readl_poll_timeout(reg_channel, val,
+ ((val & MT65XX_AUXADC_RDY0) == 1),
+ MT65XX_AUXADC_SLEEP_US,
+ MT65XX_AUXADC_TIMEOUT_US);
+
+ /* read data */
+ rawdata = readl(reg_channel) & MT65XX_AUXADC_DAT_MASK;
+
+ mutex_unlock(&adc_dev->lock);
+
+ return rawdata;
+}
+
+static int mt65xx_auxadc_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long info)
+{
+ int ret;
+
+ switch (info) {
+ case IIO_CHAN_INFO_RAW:
+ *val = mt65xx_auxadc_read(indio_dev, chan);
+ ret = IIO_VAL_INT;
+ break;
+ case IIO_CHAN_INFO_SCALE:
+ *val = 1;
+ ret = IIO_VAL_INT;
+ break;
+ case IIO_CHAN_INFO_OFFSET:
+ *val = 0;
+ ret = IIO_VAL_INT;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static const struct iio_info mt65xx_auxadc_info = {
+ .driver_module = THIS_MODULE,
+ .read_raw = &mt65xx_auxadc_read_raw,
+};
+
+static int mt65xx_auxadc_probe(struct platform_device *pdev)
+{
+ struct mt65xx_auxadc_device *adc_dev;
+ unsigned long adc_clk_rate;
+ struct resource *res;
+ struct iio_dev *indio_dev;
+ int ret;
+ u32 val;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ adc_dev = iio_priv(indio_dev);
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->name = dev_name(&pdev->dev);
+ indio_dev->info = &mt65xx_auxadc_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->channels = mt65xx_auxadc_iio_channels;
+ indio_dev->num_channels = ARRAY_SIZE(mt65xx_auxadc_iio_channels);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ adc_dev->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(adc_dev->reg_base)) {
+ dev_err(&pdev->dev, "failed to get auxadc base address.\n");
+ return PTR_ERR(adc_dev->reg_base);
+ }
+
+ adc_dev->adc_clk = devm_clk_get(&pdev->dev, "main");
+ if (IS_ERR(adc_dev->adc_clk)) {
+ dev_err(&pdev->dev, "failed to get axuadc clock\n");
+ return PTR_ERR(adc_dev->adc_clk);
+ }
+
+ ret = clk_prepare_enable(adc_dev->adc_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable auxadc clock\n");
+ return ret;
+ }
+
+ adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
+ if (!adc_clk_rate) {
+ dev_err(&pdev->dev, "null clock rate!\n");
+ clk_disable_unprepare(adc_dev->adc_clk);
+ return -EINVAL;
+ }
+
+ adc_dev->power_ready_ms = MT65XX_AUXADC_POWER_READY_MS;
+ adc_dev->sample_ready_us = MT65XX_AUXADC_SAMPLE_READY_US;
+
+ mutex_init(&adc_dev->lock);
+
+ val = readl(adc_dev->reg_base + MT65XX_AUXADC_MISC);
+ val |= MT65XX_AUXADC_PDN_EN;
+ writel(val, adc_dev->reg_base + MT65XX_AUXADC_MISC);
+ mdelay(adc_dev->power_ready_ms);
+
+ ret = iio_device_register(indio_dev);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to register iio device!\n");
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ return 0;
+}
+
+static int mt65xx_auxadc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+ struct mt65xx_auxadc_device *adc_dev = iio_priv(indio_dev);
+ u32 val;
+
+ iio_device_unregister(indio_dev);
+
+ val = readl(adc_dev->reg_base + MT65XX_AUXADC_MISC);
+ val &= ~MT65XX_AUXADC_PDN_EN;
+ writel(val, adc_dev->reg_base + MT65XX_AUXADC_MISC);
+
+ clk_disable_unprepare(adc_dev->adc_clk);
+
+ return 0;
+}
+
+static const struct of_device_id mt65xx_auxadc_of_match[] = {
+ { .compatible = "mediatek,mt2701-auxadc", },
+ { .compatible = "mediatek,mt8173-auxadc", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, mt65xx_auxadc_of_match);
+
+static struct platform_driver mt65xx_auxadc_driver = {
+ .driver = {
+ .name = "mt65xx-auxadc",
+ .of_match_table = mt65xx_auxadc_of_match,
+ },
+ .probe = mt65xx_auxadc_probe,
+ .remove = mt65xx_auxadc_remove,
+};
+module_platform_driver(mt65xx_auxadc_driver);
+
+MODULE_AUTHOR("Zhiyong Tao <zhiyong.tao@mediatek.com>");
+MODULE_DESCRIPTION("MTK AUXADC Device Driver");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 3/3] arm: dts: auxadc: Add auxadc node.
2016-06-24 7:37 [PATCH 0/3] AUXADC: Mediatek auxadc driver zhiyong.tao
2016-06-24 7:37 ` [PATCH 1/3] dt-bindings: auxadc: Add binding document for Mediatek auxadc zhiyong.tao
2016-06-24 7:37 ` [PATCH 2/3] auxadc: Add Mediatek auxadc driver for mt2701 zhiyong.tao
@ 2016-06-24 7:37 ` zhiyong.tao
2 siblings, 0 replies; 4+ messages in thread
From: zhiyong.tao @ 2016-06-24 7:37 UTC (permalink / raw)
To: robh+dt, jic23, knaack.h, lars, pmeerw
Cc: srv_heupstream, liguo.zhang, yingjoe.chen, eddie.huang, erin.lo,
dawei.chien, matthias.bgg, s.hauer, devicetree, linux-kernel,
linux-arm-kernel, linux-iio, linux-mediatek, Zhiyong Tao
[-- Attachment #1.1: Type: text/html, Size: 1858 bytes --]
[-- Attachment #1.2: Type: text/plain, Size: 829 bytes --]
From: Zhiyong Tao <zhiyong.tao@mediatek.com>
The commit adds auxadc nodes to the Mediatek MT2701 dtsi file.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 42d5a37..464c86a 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -187,6 +187,15 @@
<0 0x10216000 0 0x2000>;
};
+ auxadc: auxadc@11001000 {
+ compatible = "mediatek,mt2701-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt2701-uart",
"mediatek,mt6577-uart";
--
1.7.9.5
^ permalink raw reply related [flat|nested] 4+ messages in thread