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[72.194.116.95]) by smtp.gmail.com with ESMTPSA id b19-20020a17090a991300b001df4a0e9357sm39788pjp.12.2022.05.17.13.29.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 May 2022 13:29:37 -0700 (PDT) Message-ID: <146fb86f-c66d-4c72-d953-a73271d855f4@gmail.com> Date: Tue, 17 May 2022 13:29:35 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH v2 2/2] mmc: sdhci-brcmstb: Add ability to increase max clock rate for 72116b0 Content-Language: en-US To: Kamal Dasu , ulf.hansson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, alcooperx@gmail.com Cc: bcm-kernel-feedback-list@broadcom.com, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20220517180435.29940-1-kdasu.kdev@gmail.com> <20220517180435.29940-3-kdasu.kdev@gmail.com> From: Florian Fainelli In-Reply-To: <20220517180435.29940-3-kdasu.kdev@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Kamal, On 5/17/2022 11:04 AM, Kamal Dasu wrote: > From: Al Cooper > > The 72116B0 has improved SDIO controllers that allow the max clock > rate to be increased from a max of 100MHz to a max of 150MHz. The > driver will need to get the clock and increase it's default rate > and override the caps register, that still indicates a max of 100MHz. > The new clock will be named "sdio_freq" in the DT node's "clock-names" > list. The driver will use a DT property, "max-frequency", to > enable this functionality and will get the actual rate in MHz > from the property to allow various speeds to be requested. > > Signed-off-by: Al Cooper > Signed-off-by: Kamal Dasu > --- > drivers/mmc/host/sdhci-brcmstb.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c > index 8eb57de48e0c..bb614a5e1ea4 100644 > --- a/drivers/mmc/host/sdhci-brcmstb.c > +++ b/drivers/mmc/host/sdhci-brcmstb.c > @@ -250,6 +250,8 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) > struct sdhci_pltfm_host *pltfm_host; > const struct of_device_id *match; > struct sdhci_brcmstb_priv *priv; > + struct clk *master_clk; > + u32 actual_clock_mhz; > struct sdhci_host *host; > struct resource *iomem; > struct clk *clk; > @@ -330,6 +332,32 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) > if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) > host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; > > + /* Change the base clock frequency if the DT property exists */ > + if (!(host->mmc->f_max)) > + goto add_host; > + > + master_clk = devm_clk_get(&pdev->dev, "sdio_freq"); This looks like a candidate for devm_clk_get_optional() since the clock is optional. Then you can call clk_prepare_enable() unconditionally even if it is NULL/non-existent. > + if (IS_ERR(master_clk)) { > + dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n"); > + goto add_host; > + } else { > + res = clk_prepare_enable(master_clk); > + if (res) > + goto err; It looks like we may be leaving the clock enabled even when we did not want to (e.g.: error path) and do not we need to turn if off, respectively turn it back on in .suspend() and .resume()? > + } > + > + /* set improved clock rate */ > + clk_set_rate(master_clk, host->mmc->f_max); > + actual_clock_mhz = clk_get_rate(master_clk) / 1000000; > + > + host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; > + host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT); > + /* Disable presets because they are now incorrect */ > + host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; > + dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n", > + actual_clock_mhz); > + > +add_host: > res = sdhci_brcmstb_add_host(host, priv); > if (res) > goto err; It looks like we would need to unwind the clk_prepare_enable(master_clk) in case of failures here. -- Florian