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From: Sinan Kaya <okaya@codeaurora.org>
To: dmaengine@vger.kernel.org, timur@codeaurora.org,
	devicetree@vger.kernel.org, cov@codeaurora.org,
	vinod.koul@intel.com, jcm@redhat.com
Cc: agross@codeaurora.org, arnd@arndb.de,
	linux-arm-msm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Sinan Kaya <okaya@codeaurora.org>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH V3 01/10] Documentation: DT: qcom_hidma: update binding for MSI
Date: Thu, 15 Sep 2016 13:22:37 -0400	[thread overview]
Message-ID: <1473960166-30155-2-git-send-email-okaya@codeaurora.org> (raw)
In-Reply-To: <1473960166-30155-1-git-send-email-okaya@codeaurora.org>

Adding a new binding for qcom,hidma-1.1 to distinguish HW supporting
MSI interrupts from the older revision.

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
 Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
index fd5618b..47bfb5a 100644
--- a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
@@ -47,12 +47,23 @@ When the OS is not in control of the management interface (i.e. it's a guest),
 the channel nodes appear on their own, not under a management node.
 
 Required properties:
-- compatible: must contain "qcom,hidma-1.0"
+- compatible: must contain "qcom,hidma-1.0" for initial HW or "qcom,hidma-1.1"
+for MSI capable HW.
 - reg: Addresses for the transfer and event channel
 - interrupts: Should contain the event interrupt
 - desc-count: Number of asynchronous requests this channel can handle
 - iommus: required a iommu node
 
+Optional properties for MSI:
+- msi-parent: pointer to the MSI controller object with the DeviceID in use.
+
+Example:
+ msi_parent: <&msi0 0x80024>
+
+msi0 is the MSI controller in the system. Bits 0-5 is the channel ID. 4
+is the channel ID. Bits 5-8 is the instance number. This is for the HIDMA
+instance 1.
+
 Example:
 
 Hypervisor OS configuration:
-- 
1.9.1

  reply	other threads:[~2016-09-15 17:22 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-15 17:22 [PATCH V3 00/10] dmaengine: qcom_hidma: add MSI interrupt support Sinan Kaya
2016-09-15 17:22 ` Sinan Kaya [this message]
2016-09-23 15:39   ` [PATCH V3 01/10] Documentation: DT: qcom_hidma: update binding for MSI Rob Herring
2016-09-23 17:22     ` Sinan Kaya
     [not found]   ` <1473960166-30155-2-git-send-email-okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-09-23 18:02     ` Mark Rutland
2016-09-23 18:58       ` Sinan Kaya
2016-09-15 17:22 ` [PATCH V3 02/10] Documentation: DT: qcom_hidma: correct spelling mistakes Sinan Kaya
2016-09-15 17:22 ` [PATCH V3 03/10] of: irq: make of_msi_configure accessible from modules Sinan Kaya
2016-09-15 17:22 ` [PATCH V3 04/10] dmaengine: qcom_hidma: configure DMA and MSI for OF Sinan Kaya
2016-09-15 17:22 ` [PATCH V3 05/10] dmaengine: qcom_hidma: make pending_tre_count atomic Sinan Kaya
2016-09-15 17:22 ` [PATCH V3 06/10] dmaengine: qcom_hidma: make error and success path common Sinan Kaya
2016-09-15 17:22 ` [PATCH V3 07/10] dmaengine: qcom_hidma: bring out interrupt cause Sinan Kaya
2016-09-15 17:22 ` [PATCH V3 08/10] dmaengine: qcom_hidma: add a common API to setup the interrupt Sinan Kaya
2016-09-15 17:22 ` [PATCH V3 09/10] dmaengine: qcom_hidma: protect common data structures Sinan Kaya
2016-09-15 17:22 ` [PATCH V3 10/10] dmaengine: qcom_hidma: add MSI support for interrupts Sinan Kaya

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