[PATCHv2 0/4] Add TX FIFO Threshold for Altera 16550-FIFOxx

[PATCHv2 0/4] Add TX FIFO Threshold for Altera 16550-FIFOxx

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

Some variants of the 16550 have a programmable TX FIFO threshold that
will trigger an IRQ when the FIFO drops below the threshold. The Altera
16550 compatible soft IP supports programmable TX FIFO thresholds.

This patch series adds the tx-threshold parameter to the device tree.
The tx_loadsz variable is amount of data that can be loaded into the
FIFO on an IRQ and is updated based on the tx-threshold value.

This patch series also adds support for the TX FIFO threshold registers
in the Altera 16550-FIFOxx soft IP.

Thor Thayer (4):
  Documentation: dt: serial: Add TX FIFO threshold parameter
  serial: 8250: of: Load TX FIFO Threshold from DT
  serial: 8250: Set Altera 16550 TX FIFO Threshold
  nios2: dts: 10m50: Add tx-threshold parameter

 Documentation/devicetree/bindings/serial/8250.txt |    2 +
 arch/nios2/boot/dts/10m50_devboard.dts            |    1 +
 drivers/tty/serial/8250/8250_of.c                 |    7 ++++
 drivers/tty/serial/8250/8250_port.c               |   43 +++++++++++++++++++++
 include/uapi/linux/serial_reg.h                   |    8 ++++
 5 files changed, 61 insertions(+)

-- 
1.7.9.5

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[PATCHv2 1/4] Documentation: dt: serial: Add TX FIFO threshold parameter

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the device tree binding needed to support the TX FIFO threshold
parameter.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2  Change parameter name from tx-loadsz to tx-threshold
---
 Documentation/devicetree/bindings/serial/8250.txt |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/8250.txt b/Documentation/devicetree/bindings/serial/8250.txt
index 936ab5b..f86bb06 100644
--- a/Documentation/devicetree/bindings/serial/8250.txt
+++ b/Documentation/devicetree/bindings/serial/8250.txt
@@ -42,6 +42,8 @@ Optional properties:
 - auto-flow-control: one way to enable automatic flow control support. The
   driver is allowed to detect support for the capability even without this
   property.
+- tx-threshold: Specify the TX FIFO low water indication for parts with
+  programmable TX FIFO thresholds.
 
 Note:
 * fsl,ns16550:
-- 
1.7.9.5

[PATCHv2 2/4] serial: 8250: of: Load TX FIFO Threshold from DT

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

Initialize the tx_loadsz parameter from passed in devicetree
tx-threshold parameter.
The tx_loadsz is calculated as the number of bytes to fill FIFO
when tx-threshold is triggered.

Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
v2  Change from reading tx-loadsz parameter to reading
    tx-threshold and calculating tx_loadsz.
---
 drivers/tty/serial/8250/8250_of.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c
index 38963d7..7a8b5fc 100644
--- a/drivers/tty/serial/8250/8250_of.c
+++ b/drivers/tty/serial/8250/8250_of.c
@@ -195,6 +195,7 @@ static int of_platform_serial_probe(struct platform_device *ofdev)
 	switch (port_type) {
 	case PORT_8250 ... PORT_MAX_8250:
 	{
+		u32 tx_threshold;
 		struct uart_8250_port port8250;
 		memset(&port8250, 0, sizeof(port8250));
 		port8250.port = port;
@@ -202,6 +203,12 @@ static int of_platform_serial_probe(struct platform_device *ofdev)
 		if (port.fifosize)
 			port8250.capabilities = UART_CAP_FIFO;
 
+		/* Check for TX FIFO threshold & set tx_loadsz */
+		if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
+					  &tx_threshold) == 0) &&
+		    (tx_threshold < port.fifosize))
+			port8250.tx_loadsz = port.fifosize - tx_threshold;
+
 		if (of_property_read_bool(ofdev->dev.of_node,
 					  "auto-flow-control"))
 			port8250.capabilities |= UART_CAP_AFE;
-- 
1.7.9.5

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[PATCHv2 3/4] serial: 8250: Set Altera 16550 TX FIFO Threshold

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

The Altera 16550 soft IP UART requires 2 additional registers for
TX FIFO threshold support. These 2 registers enable the TX FIFO
Low Watermark and set the TX FIFO Low Watermark.
Set the TX FIFO threshold to the FIFO size - tx_loadsz.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2  Add bounds checking of tx threshold value.
---
 drivers/tty/serial/8250/8250_port.c |   43 +++++++++++++++++++++++++++++++++++
 include/uapi/linux/serial_reg.h     |    8 +++++++
 2 files changed, 51 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index ae3a104..24ef65a 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -1870,6 +1870,30 @@ static int exar_handle_irq(struct uart_port *port)
 	return ret;
 }
 
+/*
+ * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
+ * have a programmable TX threshold that triggers the THRE interrupt in
+ * the IIR register. In this case, the THRE interrupt indicates the FIFO
+ * has space available. Load it up with tx_loadsz bytes.
+ */
+static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
+{
+	unsigned long flags;
+	unsigned int iir = serial_port_in(port, UART_IIR);
+
+	/* TX Threshold IRQ triggered so load up FIFO */
+	if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
+		struct uart_8250_port *up = up_to_u8250p(port);
+
+		spin_lock_irqsave(&port->lock, flags);
+		serial8250_tx_chars(up);
+		spin_unlock_irqrestore(&port->lock, flags);
+	}
+
+	iir = serial_port_in(port, UART_IIR);
+	return serial8250_handle_irq(port, iir);
+}
+
 static unsigned int serial8250_tx_empty(struct uart_port *port)
 {
 	struct uart_8250_port *up = up_to_u8250p(port);
@@ -2158,6 +2182,25 @@ int serial8250_do_startup(struct uart_port *port)
 		serial_port_out(port, UART_LCR, 0);
 	}
 
+	/*
+	 * For the Altera 16550 variants, set TX threshold trigger level.
+	 */
+	if (((port->type == PORT_ALTR_16550_F32) ||
+	     (port->type == PORT_ALTR_16550_F64) ||
+	     (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
+		/* Bounds checking of TX threshold (valid 0 to fifosize-2) */
+		if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
+			pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
+			       serial_index(port));
+		} else {
+			serial_port_out(port, UART_ALTR_AFR,
+					UART_ALTR_EN_TXFIFO_LW);
+			serial_port_out(port, UART_ALTR_TX_LOW,
+					port->fifosize - up->tx_loadsz);
+			port->handle_irq = serial8250_tx_threshold_handle_irq;
+		}
+	}
+
 	if (port->irq) {
 		unsigned char iir1;
 		/*
diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h
index 1e5ac4e7..b4c0484 100644
--- a/include/uapi/linux/serial_reg.h
+++ b/include/uapi/linux/serial_reg.h
@@ -376,5 +376,13 @@
 #define UART_EXAR_TXTRG		0x0a	/* Tx FIFO trigger level write-only */
 #define UART_EXAR_RXTRG		0x0b	/* Rx FIFO trigger level write-only */
 
+/*
+ * These are definitions for the Altera ALTR_16550_F32/F64/F128
+ * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs).
+ */
+#define UART_ALTR_AFR		0x40	/* Additional Features Register */
+#define UART_ALTR_EN_TXFIFO_LW	0x01	/* Enable the TX FIFO Low Watermark */
+#define UART_ALTR_TX_LOW	0x41	/* Tx FIFO Low Watermark */
+
 #endif /* _LINUX_SERIAL_REG_H */
 
-- 
1.7.9.5

[PATCHv2 4/4] nios2: dts: 10m50: Add tx-threshold parameter

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

The tx-threshold parameter sets the TX FIFO low water threshold
trigger for the Altera 16550-FIFO32 soft IP.

Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
v2   Change from tx-loadsz to tx-threshold
---
 arch/nios2/boot/dts/10m50_devboard.dts |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/nios2/boot/dts/10m50_devboard.dts b/arch/nios2/boot/dts/10m50_devboard.dts
index 3e411c6..f362b22 100755
--- a/arch/nios2/boot/dts/10m50_devboard.dts
+++ b/arch/nios2/boot/dts/10m50_devboard.dts
@@ -83,6 +83,7 @@
 			fifo-size = <32>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
+			tx-threshold = <16>;
 		};
 
 		sysid: sysid@18001528 {
-- 
1.7.9.5

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Re: [PATCHv2 1/4] Documentation: dt: serial: Add TX FIFO threshold parameter

[Rob Herring]

On Thu, Sep 22, 2016 at 02:56:14PM -0500, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> 
> Add the device tree binding needed to support the TX FIFO threshold
> parameter.
> 
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> ---
> v2  Change parameter name from tx-loadsz to tx-threshold
> ---
>  Documentation/devicetree/bindings/serial/8250.txt |    2 ++
>  1 file changed, 2 insertions(+)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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Re: [PATCHv2 4/4] nios2: dts: 10m50: Add tx-threshold parameter

[Ley Foon Tan]

On Fri, Sep 23, 2016 at 3:56 AM,  <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> wrote:
> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>
> The tx-threshold parameter sets the TX FIFO low water threshold
> trigger for the Altera 16550-FIFO32 soft IP.
>
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> ---
> v2   Change from tx-loadsz to tx-threshold
> ---
>  arch/nios2/boot/dts/10m50_devboard.dts |    1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/nios2/boot/dts/10m50_devboard.dts b/arch/nios2/boot/dts/10m50_devboard.dts
> index 3e411c6..f362b22 100755
> --- a/arch/nios2/boot/dts/10m50_devboard.dts
> +++ b/arch/nios2/boot/dts/10m50_devboard.dts
> @@ -83,6 +83,7 @@
>                         fifo-size = <32>;
>                         reg-io-width = <4>;
>                         reg-shift = <2>;
> +                       tx-threshold = <16>;
>                 };
>
>                 sysid: sysid@18001528 {

Acked-by: Ley Foon Tan <lftan-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
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