[PATCH v8 0/3] the fixup for the USB HOST1 at rk3288 platform

[PATCH v8 0/3] the fixup for the USB HOST1 at rk3288 platform

[Randy Li]

  At this stage it is the only "full features" and well verified 
USB EHCI controller in this platform. More review is always necessary.

Although V7 is almost fine but a forget a dummy function for the phy
system.

changelog:
v7
  add the forgot dummy phy_reset() for the generic phy is disabled.
v7
  Some minor fixup
v6
  Send the last two patches
v5
  A few modification at style, add the missing doc in the last 
  commit.
v4
  1. Adding the reset callback in struct phy_ops.
  2. Moving the reset into phy rockchip usb.
  3. Trying to call a reset when dwc2 wakeup in rk3288.
v3
 Rebased from previous commit
v2
 Rebased from previous commit
v1
 orignal from google

Randy Li (3):
  phy: Add reset callback for not generic phy
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 arch/arm/boot/dts/rk3288.dtsi |  4 ++++
 drivers/usb/dwc2/core_intr.c  | 11 +++++++++++
 include/linux/phy/phy.h       |  7 +++++++
 3 files changed, 22 insertions(+)

-- 
2.7.4

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[PATCH v8 1/3] phy: Add reset callback for not generic phy

[Randy Li]

I forget to add a dummy function in case the CONFIG_GENERIC_PHY
is disabled.

Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
---
 include/linux/phy/phy.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index ee1bed7..78bb0d7 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -253,6 +253,13 @@ static inline int phy_set_mode(struct phy *phy, enum phy_mode mode)
 	return -ENOSYS;
 }
 
+static inline int phy_reset(struct phy *phy)
+{
+	if (!phy)
+		return 0;
+	return -ENOSYS;
+}
+
 static inline int phy_get_bus_width(struct phy *phy)
 {
 	return -ENOSYS;
-- 
2.7.4

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[PATCH v8 2/3] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
---
 drivers/usb/dwc2/core_intr.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..af27edc 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
 	int ret;
+	struct device_node *np = hsotg->dev->of_node;
 
 	/* Clear interrupt */
 	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 			/* Restart the Phy Clock */
 			pcgcctl &= ~PCGCTL_STOPPCLK;
 			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+			/*
+			 * It is a quirk in Rockchip RK3288, causing by
+			 * a hardware bug. This will propagate out and
+			 * eventually we'll re-enumerate the device.
+			 * Not great but the best we can do.
+			 */
+			if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
+				phy_reset(hsotg->phy);
+
 			mod_timer(&hsotg->wkp_timer,
 				  jiffies + msecs_to_jiffies(71));
 		} else {
-- 
2.7.4

Re: [PATCH v8 2/3] usb: dwc2: assert phy reset when waking up in rk3288 platform

[John Youn]

On 9/24/2016 11:51 AM, Randy Li wrote:
> On the rk3288 USB host-only port (the one that's not the OTG-enabled
> port) the PHY can get into a bad state when a wakeup is asserted (not
> just a wakeup from full system suspend but also a wakeup from
> autosuspend).
> 
> We can get the PHY out of its bad state by asserting its "port reset",
> but unfortunately that seems to assert a reset onto the USB bus so it
> could confuse things if we don't actually deenumerate / reenumerate the
> device.
> 
> We can also get the PHY out of its bad state by fully resetting it using
> the reset from the CRU (clock reset unit) in chip, which does a more full
> reset.  The CRU-based reset appears to actually cause devices on the bus
> to be removed and reinserted, which fixes the problem (albeit in a hacky
> way).
> 
> It's unfortunate that we need to do a full re-enumeration of devices at
> wakeup time, but this is better than alternative of letting the bus get
> wedged.
> 
> Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
> ---
>  drivers/usb/dwc2/core_intr.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
> index d85c5c9..af27edc 100644
> --- a/drivers/usb/dwc2/core_intr.c
> +++ b/drivers/usb/dwc2/core_intr.c
> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>  static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>  {
>  	int ret;
> +	struct device_node *np = hsotg->dev->of_node;
>  
>  	/* Clear interrupt */
>  	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
> @@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>  			/* Restart the Phy Clock */
>  			pcgcctl &= ~PCGCTL_STOPPCLK;
>  			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
> +
> +			/*
> +			 * It is a quirk in Rockchip RK3288, causing by
> +			 * a hardware bug. This will propagate out and
> +			 * eventually we'll re-enumerate the device.
> +			 * Not great but the best we can do.
> +			 */
> +			if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
> +				phy_reset(hsotg->phy);
> +
>  			mod_timer(&hsotg->wkp_timer,
>  				  jiffies + msecs_to_jiffies(71));
>  		} else {
> 


Acked-by: John Youn <johnyoun-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>

Regards,
John

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Re: [PATCH v8 2/3] usb: dwc2: assert phy reset when waking up in rk3288 platform

[陈豪]

2016-09-25 2:50 GMT+08:00 Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>:
> On the rk3288 USB host-only port (the one that's not the OTG-enabled
> port) the PHY can get into a bad state when a wakeup is asserted (not
> just a wakeup from full system suspend but also a wakeup from
> autosuspend).
>
> We can get the PHY out of its bad state by asserting its "port reset",
> but unfortunately that seems to assert a reset onto the USB bus so it
> could confuse things if we don't actually deenumerate / reenumerate the
> device.
>
> We can also get the PHY out of its bad state by fully resetting it using
> the reset from the CRU (clock reset unit) in chip, which does a more full
> reset.  The CRU-based reset appears to actually cause devices on the bus
> to be removed and reinserted, which fixes the problem (albeit in a hacky
> way).
>
> It's unfortunate that we need to do a full re-enumeration of devices at
> wakeup time, but this is better than alternative of letting the bus get
> wedged.
>
> Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
> ---
>  drivers/usb/dwc2/core_intr.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
> index d85c5c9..af27edc 100644
> --- a/drivers/usb/dwc2/core_intr.c
> +++ b/drivers/usb/dwc2/core_intr.c
> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>  static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>  {
>         int ret;
> +       struct device_node *np = hsotg->dev->of_node;
>
>         /* Clear interrupt */
>         dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
> @@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>                         /* Restart the Phy Clock */
>                         pcgcctl &= ~PCGCTL_STOPPCLK;
>                         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
> +
> +                       /*
> +                        * It is a quirk in Rockchip RK3288, causing by
> +                        * a hardware bug. This will propagate out and
> +                        * eventually we'll re-enumerate the device.
> +                        * Not great but the best we can do.
> +                        */
> +                       if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
> +                               phy_reset(hsotg->phy);

It will call mutex_lock in phy_reset.


> +
>                         mod_timer(&hsotg->wkp_timer,
>                                   jiffies + msecs_to_jiffies(71));
>                 } else {
> --
> 2.7.4
>

What is the status of this patch？
Sleeping calls(phy_reset ==> mutex) shouldn't be used in irq handler.
Randy will correct that？
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Re: [PATCH v8 2/3] usb: dwc2: assert phy reset when waking up in rk3288 platform

[John Youn]

On 10/15/2016 8:07 AM, 陈豪 wrote:
> 2016-09-25 2:50 GMT+08:00 Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>:
>> On the rk3288 USB host-only port (the one that's not the OTG-enabled
>> port) the PHY can get into a bad state when a wakeup is asserted (not
>> just a wakeup from full system suspend but also a wakeup from
>> autosuspend).
>>
>> We can get the PHY out of its bad state by asserting its "port reset",
>> but unfortunately that seems to assert a reset onto the USB bus so it
>> could confuse things if we don't actually deenumerate / reenumerate the
>> device.
>>
>> We can also get the PHY out of its bad state by fully resetting it using
>> the reset from the CRU (clock reset unit) in chip, which does a more full
>> reset.  The CRU-based reset appears to actually cause devices on the bus
>> to be removed and reinserted, which fixes the problem (albeit in a hacky
>> way).
>>
>> It's unfortunate that we need to do a full re-enumeration of devices at
>> wakeup time, but this is better than alternative of letting the bus get
>> wedged.
>>
>> Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
>> ---
>>  drivers/usb/dwc2/core_intr.c | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>>
>> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
>> index d85c5c9..af27edc 100644
>> --- a/drivers/usb/dwc2/core_intr.c
>> +++ b/drivers/usb/dwc2/core_intr.c
>> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>>  static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>  {
>>         int ret;
>> +       struct device_node *np = hsotg->dev->of_node;
>>
>>         /* Clear interrupt */
>>         dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
>> @@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>                         /* Restart the Phy Clock */
>>                         pcgcctl &= ~PCGCTL_STOPPCLK;
>>                         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
>> +
>> +                       /*
>> +                        * It is a quirk in Rockchip RK3288, causing by
>> +                        * a hardware bug. This will propagate out and
>> +                        * eventually we'll re-enumerate the device.
>> +                        * Not great but the best we can do.
>> +                        */
>> +                       if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
>> +                               phy_reset(hsotg->phy);
> 
> It will call mutex_lock in phy_reset.
> 
> 
>> +
>>                         mod_timer(&hsotg->wkp_timer,
>>                                   jiffies + msecs_to_jiffies(71));
>>                 } else {
>> --
>> 2.7.4
>>
> 
> What is the status of this patch？
> Sleeping calls(phy_reset ==> mutex) shouldn't be used in irq handler.
> Randy will correct that？
> 

Yes, that's right, I missed that.

It will have to be fixed.

Regards,
John

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Re: [PATCH v8 2/3] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On 10/20/2016 06:58 AM, John Youn wrote:
> On 10/15/2016 8:07 AM, 陈豪 wrote:
>> 2016-09-25 2:50 GMT+08:00 Randy Li <ayaka@soulik.info>:
>>> On the rk3288 USB host-only port (the one that's not the OTG-enabled
>>> port) the PHY can get into a bad state when a wakeup is asserted (not
>>> just a wakeup from full system suspend but also a wakeup from
>>> autosuspend).
>>>
>>> We can get the PHY out of its bad state by asserting its "port reset",
>>> but unfortunately that seems to assert a reset onto the USB bus so it
>>> could confuse things if we don't actually deenumerate / reenumerate the
>>> device.
>>>
>>> We can also get the PHY out of its bad state by fully resetting it using
>>> the reset from the CRU (clock reset unit) in chip, which does a more full
>>> reset.  The CRU-based reset appears to actually cause devices on the bus
>>> to be removed and reinserted, which fixes the problem (albeit in a hacky
>>> way).
>>>
>>> It's unfortunate that we need to do a full re-enumeration of devices at
>>> wakeup time, but this is better than alternative of letting the bus get
>>> wedged.
>>>
>>> Signed-off-by: Randy Li <ayaka@soulik.info>
>>> ---
>>>  drivers/usb/dwc2/core_intr.c | 11 +++++++++++
>>>  1 file changed, 11 insertions(+)
>>>
>>> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
>>> index d85c5c9..af27edc 100644
>>> --- a/drivers/usb/dwc2/core_intr.c
>>> +++ b/drivers/usb/dwc2/core_intr.c
>>> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>>>  static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>>  {
>>>         int ret;
>>> +       struct device_node *np = hsotg->dev->of_node;
>>>
>>>         /* Clear interrupt */
>>>         dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
>>> @@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>>                         /* Restart the Phy Clock */
>>>                         pcgcctl &= ~PCGCTL_STOPPCLK;
>>>                         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
>>> +
>>> +                       /*
>>> +                        * It is a quirk in Rockchip RK3288, causing by
>>> +                        * a hardware bug. This will propagate out and
>>> +                        * eventually we'll re-enumerate the device.
>>> +                        * Not great but the best we can do.
>>> +                        */
>>> +                       if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
>>> +                               phy_reset(hsotg->phy);
>>
>> It will call mutex_lock in phy_reset.
>>
>>
>>> +
>>>                         mod_timer(&hsotg->wkp_timer,
>>>                                   jiffies + msecs_to_jiffies(71));
>>>                 } else {
>>> --
>>> 2.7.4
>>>
>>
>> What is the status of this patch？
>> Sleeping calls(phy_reset ==> mutex) shouldn't be used in irq handler.
>> Randy will correct that？
>>
>
> Yes, that's right, I missed that.
>
> It will have to be fixed.
I am still thinking a method to instead it.
>
> Regards,
> John
>
>

-- 
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[PATCH v8 3/3] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 2cf1eb2..b87f421 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -859,6 +859,8 @@
 				clocks = <&cru SCLK_OTGPHY0>;
 				clock-names = "phyclk";
 				#clock-cells = <0>;
+				resets = <&cru SRST_USBOTG_PHY>;
+				reset-names = "phy-reset";
 			};
 
 			usbphy1: usb-phy@334 {
@@ -875,6 +877,8 @@
 				clocks = <&cru SCLK_OTGPHY2>;
 				clock-names = "phyclk";
 				#clock-cells = <0>;
+				resets = <&cru SRST_USBHOST1_PHY>;
+				reset-names = "phy-reset";
 			};
 		};
 	};
-- 
2.7.4

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