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From: Jon Mason <jon.mason@broadcom.com>
To: David Miller <davem@davemloft.net>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Florian Fainelli <f.fainelli@gmail.com>
Cc: devicetree@vger.kernel.org, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	bcm-kernel-feedback-list@broadcom.com, rafal@milecki.pl,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 1/7] net: phy: broadcom: add bcm54xx_auxctl_read
Date: Tue,  1 Nov 2016 16:04:36 -0400	[thread overview]
Message-ID: <1478030682-27012-2-git-send-email-jon.mason@broadcom.com> (raw)
In-Reply-To: <1478030682-27012-1-git-send-email-jon.mason@broadcom.com>

Add a helper function to read the AUXCTL register for the BCM54xx.  This
mirrors the bcm54xx_auxctl_write function already present in the code.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
 drivers/net/phy/broadcom.c | 10 ++++++++++
 include/linux/brcmphy.h    |  1 +
 2 files changed, 11 insertions(+)

diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 583ef8a..3a64b3d 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -30,6 +30,16 @@ MODULE_DESCRIPTION("Broadcom PHY driver");
 MODULE_AUTHOR("Maciej W. Rozycki");
 MODULE_LICENSE("GPL");
 
+static int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
+{
+	/* The register must be written to both the Shadow Register Select and
+	 * the Shadow Read Register Selector
+	 */
+	phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
+		  regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
+	return phy_read(phydev, MII_BCM54XX_AUX_CTL);
+}
+
 static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
 {
 	return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 60def78..0ed6691 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -110,6 +110,7 @@
 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX	0x0200
 #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC	0x7000
 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC	0x0007
+#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT	12
 
 #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK	0x0007
 
-- 
2.7.4

  reply	other threads:[~2016-11-01 20:04 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-01 20:04 [PATCH v4 0/7] add NS2 support to bgmac Jon Mason
2016-11-01 20:04 ` Jon Mason [this message]
2016-11-01 20:04 ` [PATCH v4 2/7] Documentation: devicetree: add PHY lane swap binding Jon Mason
     [not found]   ` <1478030682-27012-3-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2016-11-01 20:48     ` Andrew Lunn
     [not found]       ` <20161101204826.GA21010-g2DYL2Zd6BY@public.gmane.org>
2016-11-01 20:59         ` Jon Mason
2016-11-01 21:01           ` Scott Branden
2016-11-01 21:09             ` Andrew Lunn
2016-11-01 20:04 ` [PATCH v4 3/7] net: phy: broadcom: Add BCM54810 PHY entry Jon Mason
2016-11-01 20:04 ` [PATCH v4 4/7] Documentation: devicetree: net: add NS2 bindings to amac Jon Mason
     [not found] ` <1478030682-27012-1-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2016-11-01 20:04   ` [PATCH v4 5/7] net: ethernet: bgmac: device tree phy enablement Jon Mason
2016-11-01 20:04 ` [PATCH v4 6/7] net: ethernet: bgmac: add NS2 support Jon Mason
2016-11-01 20:34   ` Scott Branden
2016-11-01 21:05     ` Jon Mason
2016-11-02 16:53       ` Jon Mason
2016-11-01 20:04 ` [PATCH v4 7/7] arm64: dts: NS2: add AMAC ethernet support Jon Mason

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