From mboxrd@z Thu Jan 1 00:00:00 1970 From: William Wu Subject: [PATCH 2/2] arm64: dts: rockchip: add usb2-phy otg-port support for rk3399 Date: Wed, 2 Nov 2016 15:42:18 +0800 Message-ID: <1478072538-32081-3-git-send-email-wulf@rock-chips.com> References: <1478072538-32081-1-git-send-email-wulf@rock-chips.com> Return-path: In-Reply-To: <1478072538-32081-1-git-send-email-wulf@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org To: kishon@ti.com, heiko@sntech.de Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, robh+dt@kernel.org, frank.wang@rock-chips.com, huangtao@rock-chips.com, dianders@google.com, briannorris@google.com, groeck@google.com, wulf@rock-chips.com List-Id: devicetree@vger.kernel.org Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can be used for USB2.0 part of USB3.0 OTG controller. Signed-off-by: William Wu --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index b65c193..ea2df51 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1095,6 +1095,17 @@ clock-output-names = "clk_usbphy0_480m"; status = "disabled"; + u2phy0_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy0_host: host-port { #phy-cells = <0>; interrupts = ; @@ -1112,6 +1123,16 @@ clock-output-names = "clk_usbphy1_480m"; status = "disabled"; + u2phy1_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + u2phy1_host: host-port { #phy-cells = <0>; interrupts = ; -- 2.0.0