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From: Andrew Jeffery <andrew@aj.id.au>
To: Lee Jones <lee.jones@linaro.org>,
	Linus Walleij <linus.walleij@linaro.org>
Cc: Joel Stanley <joel@jms.id.au>,
	Mark Rutland <mark.rutland@arm.com>,
	Rob Herring <robh+dt@kernel.org>,
	linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	Andrew Jeffery <andrew@aj.id.au>
Subject: [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)
Date: Thu,  3 Nov 2016 01:07:58 +1030	[thread overview]
Message-ID: <1478097481-14895-4-git-send-email-andrew@aj.id.au> (raw)
In-Reply-To: <1478097481-14895-1-git-send-email-andrew@aj.id.au>

The Aspeed LPC Host Controller is presented as a syscon device to
arbitrate access by LPC and pinmux drivers. LPC pinmux configuration on
fifth generation SoCs depends on bits in both the System Control Unit
and the LPC Host Controller.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt

diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
new file mode 100644
index 000000000000..792651488c3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
@@ -0,0 +1,17 @@
+* Device tree bindings for the Aspeed LPC Host Controller (LPCHC)
+
+The LPCHC registers configure LPC behaviour between the BMC and the host
+system. The LPCHC also participates in pinmux requests on g5 SoCs and is
+therefore considered a syscon device.
+
+Required properties:
+- compatible:		"aspeed,ast2500-lpchc", "syscon"
+- reg:			contains offset/length value of the LPCHC memory
+			region.
+
+Example:
+
+lpchc: lpchc@1e7890a0 {
+	compatible = "aspeed,ast2500-lpchc", "syscon";
+	reg = <0x1e7890a0 0xc4>;
+};
-- 
2.7.4

  parent reply	other threads:[~2016-11-02 14:37 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-02 14:37 [PATCH v2 0/6] pinctrl: aspeed: Fixes for g5, implement remaining pins Andrew Jeffery
2016-11-02 14:37 ` [PATCH v2 1/6] pinctrl-aspeed-g5: Never set SCU90[6] Andrew Jeffery
     [not found]   ` <1478097481-14895-2-git-send-email-andrew-zrmu5oMJ5Fs@public.gmane.org>
2016-11-03 22:59     ` Joel Stanley
2016-11-07  9:34       ` Linus Walleij
     [not found]         ` <CACRpkdbH8eubEHwHCsdJsmqVp3hkBW4vb5DCHvJxz+tyfFqbKQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-11-07 22:42           ` Andrew Jeffery
2016-11-07  9:32   ` Linus Walleij
2016-11-02 14:37 ` [PATCH v2 2/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX) Andrew Jeffery
2016-11-09 18:26   ` Rob Herring
2016-11-10  3:19     ` Joel Stanley
2016-11-10 17:40       ` Rob Herring
2016-11-18 18:47   ` Lee Jones
2016-11-02 14:37 ` Andrew Jeffery [this message]
2016-11-03 23:06   ` [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC) Joel Stanley
     [not found]     ` <CACPK8XezumurK6TStNhmTnHdhoJuZBzkJrS3iOArKz1tf1=nLw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-11-04  3:45       ` Andrew Jeffery
     [not found]   ` <1478097481-14895-4-git-send-email-andrew-zrmu5oMJ5Fs@public.gmane.org>
2016-11-18 18:44     ` Lee Jones
     [not found]       ` <20161118184437.GD19884-Re9dqnLqz4GzQB+pC5nmwQ@public.gmane.org>
2016-11-18 18:45         ` Lee Jones
2016-11-22  3:25           ` Andrew Jeffery
     [not found] ` <1478097481-14895-1-git-send-email-andrew-zrmu5oMJ5Fs@public.gmane.org>
2016-11-02 14:37   ` [PATCH v2 4/6] pinctrl: aspeed: Read and write bits in LPCHC and GFX controllers Andrew Jeffery
2016-11-03 23:24     ` Joel Stanley
2016-11-04  3:59       ` Andrew Jeffery
2016-11-09 18:26     ` Rob Herring
2016-11-09 23:50       ` Andrew Jeffery
2016-11-02 14:38   ` [PATCH v2 6/6] pinctrl: aspeed-g5: Add mux configuration for all pins Andrew Jeffery
2016-11-02 14:38 ` [PATCH v2 5/6] pinctrl: aspeed-g4: " Andrew Jeffery

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