From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mirza Krak Subject: [PATCH V4 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table Date: Mon, 7 Nov 2016 09:30:01 +0100 Message-ID: <1478507405-13204-3-git-send-email-mirza.krak@gmail.com> References: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: swarren@wwwdotorg.org, thierry.reding@gmail.com, jonathanh@nvidia.com Cc: mark.rutland@arm.com, gnurou@gmail.com, pgaikwad@nvidia.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, pdeschrijver@nvidia.com, Mirza Krak , sboyd@codeaurora.org, linux@armlinux.org.uk, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-tegra@vger.kernel.org, mturquette@baylibre.com, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org From: Mirza Krak Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which is max rate. The maximum rate value of 127 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Acked-by: Jon Hunter --- Changes in v2: - no changes Changes in v3: - Added comment in commit message where I got the maximum rates from. Changes in V4: - no changes drivers/clk/tegra/clk-tegra30.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 8e2db5e..67f1677 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1252,6 +1252,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 }, { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 }, { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 }, + { TEGRA30_CLK_NOR, TEGRA30_CLK_PLL_P, 127000000, 0 }, { TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 }, { TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 }, { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 }, -- 2.1.4