From: Ritesh Harjani <riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
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Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
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rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
pramod.gurav-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
Ritesh Harjani <riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Subject: [PATCH v7 10/14] arm64: dts: qcom: msm8916: Add ddr support to sdhc1
Date: Mon, 14 Nov 2016 11:30:44 +0530 [thread overview]
Message-ID: <1479103248-9491-11-git-send-email-riteshh@codeaurora.org> (raw)
In-Reply-To: <1479103248-9491-1-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
This adds mmc-ddr-1_8v support to DT for sdhc1 of msm8916.
Signed-off-by: Ritesh Harjani <riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 6265822..5bc187c 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -515,6 +515,7 @@
<&gcc GCC_SDCC1_AHB_CLK>,
<&xo_board 0>;
clock-names = "core", "iface", "xo_clock";
+ mmc-ddr-1_8v;
bus-width = <8>;
non-removable;
status = "disabled";
--
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next prev parent reply other threads:[~2016-11-14 6:00 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-14 6:00 [PATCH v7 00/14] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 02/14] clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops Ritesh Harjani
2016-11-15 0:06 ` Jeremy McNicoll
2016-11-14 6:00 ` [PATCH v7 03/14] mmc: sdhci-msm: Change poor style writel/readl of registers Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 04/14] ARM: dts: Add xo_clock to sdhc nodes on qcom platforms Ritesh Harjani
2016-11-14 20:01 ` Stephen Boyd
[not found] ` <20161114200115.GL5177-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-15 5:10 ` Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 05/14] mmc: sdhci-msm: Update DLL reset sequence Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 06/14] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 08/14] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm Ritesh Harjani
2016-11-14 19:37 ` Stephen Boyd
2016-11-15 5:10 ` Ritesh Harjani
2016-11-15 19:27 ` Stephen Boyd
2016-11-16 4:42 ` Ritesh Harjani
2016-11-16 7:42 ` Adrian Hunter
2016-11-16 8:53 ` Ritesh Harjani
[not found] ` <1479103248-9491-1-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-14 6:00 ` [PATCH v7 01/14] clk: qcom: Add rcg ops to return floor value closest to the requested rate Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 07/14] mmc: sdhci-msm: Enable few quirks Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 09/14] mmc: sdhci-msm: Add clock changes for DDR mode Ritesh Harjani
2016-11-14 6:00 ` Ritesh Harjani [this message]
2016-11-14 6:00 ` [PATCH v7 11/14] mmc: sdhci-msm: Add HS400 platform support Ritesh Harjani
[not found] ` <1479103248-9491-12-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-14 13:53 ` kbuild test robot
2016-11-14 15:44 ` Ulf Hansson
[not found] ` <CAPDyKFoUiGgXhLtW9-+iAxdV6sy4+wgQfW8P5+VwsqHc3QwkqA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-11-15 0:53 ` Fengguang Wu
2016-11-14 6:00 ` [PATCH v7 12/14] mmc: sdhci-msm: Save the calculated tuning phase Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 13/14] mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit Ritesh Harjani
2016-11-14 19:59 ` Stephen Boyd
2016-11-15 4:24 ` Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 14/14] sdhci: sdhci-msm: update dll configuration Ritesh Harjani
2016-11-14 19:57 ` Stephen Boyd
2016-11-15 4:23 ` Ritesh Harjani
2016-11-15 0:06 ` [PATCH v7 00/14] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support Jeremy McNicoll
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