From: Ritesh Harjani <riteshh@codeaurora.org>
To: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org,
adrian.hunter@intel.com, sboyd@codeaurora.org,
andy.gross@linaro.org
Cc: shawn.lin@rock-chips.com, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, david.brown@linaro.org,
linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org,
alex.lemberg@sandisk.com, mateusz.nowak@intel.com,
Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org,
david.griego@linaro.org, stummala@codeaurora.org,
venkatg@codeaurora.org, rnayak@codeaurora.org,
pramod.gurav@linaro.org, jeremymc@redhat.com,
Ritesh Harjani <riteshh@codeaurora.org>
Subject: [PATCH v8 04/16] ARM: dts: Add xo to sdhc clock node on qcom platforms
Date: Thu, 17 Nov 2016 06:13:39 +0530 [thread overview]
Message-ID: <1479343419-29326-1-git-send-email-riteshh@codeaurora.org> (raw)
In-Reply-To: <1479312052-22396-5-git-send-email-riteshh@codeaurora.org>
Add xo entry to sdhc clock node on all qcom platforms.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 16 ++++++++++------
arch/arm/boot/dts/qcom-msm8974.dtsi | 16 ++++++++++------
arch/arm64/boot/dts/qcom/msm8916.dtsi | 10 ++++++----
arch/arm64/boot/dts/qcom/msm8996.dtsi | 9 +++++----
4 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 39eb7a4..f756cbb 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -182,13 +182,13 @@
};
clocks {
- xo_board {
+ xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
- sleep_clk {
+ sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -416,8 +416,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board 0>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
@@ -427,8 +429,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&xo_board 0>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index d210947..6333415 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -220,13 +220,13 @@
};
clocks {
- xo_board {
+ xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
- sleep_clk {
+ sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -558,8 +558,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board 0>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
@@ -569,8 +571,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&xo_board 0>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 466ca57..7bce1b3 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -512,8 +512,9 @@
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board 0>;
+ clock-names = "core", "iface", "xo";
bus-width = <8>;
non-removable;
status = "disabled";
@@ -527,8 +528,9 @@
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>;
- clock-names = "core", "iface";
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&xo_board 0>;
+ clock-names = "core", "iface", "xo";
bus-width = <4>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 338f82a..86bfc2d 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -192,14 +192,14 @@
};
clocks {
- xo_board {
+ xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "xo_board";
};
- sleep_clk {
+ sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
@@ -347,9 +347,10 @@
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clock-names = "iface", "core";
+ clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
- <&gcc GCC_SDCC2_APPS_CLK>;
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&xo_board 0>;
bus-width = <4>;
};
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2016-11-17 0:43 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-16 16:00 [PATCH v8 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 01/16] clk: qcom: Add rcg ops to return floor value closest to the requested rate Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 03/16] mmc: sdhci-msm: Change poor style writel/readl of registers Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 04/16] ARM: dts: Add xo_clock to sdhc nodes on qcom platforms Ritesh Harjani
2016-11-17 0:43 ` Ritesh Harjani [this message]
2016-11-18 3:56 ` [PATCH v8 04/16] ARM: dts: Add xo to sdhc clock node " Andy Gross
2016-11-21 6:30 ` Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 05/16] dt-bindings: sdhci-msm: Add xo_clock property Ritesh Harjani
2016-11-16 19:13 ` Stephen Boyd
2016-11-17 0:41 ` Ritesh Harjani
2016-11-17 0:47 ` [PATCH v8 05/16] dt-bindings: sdhci-msm: Add xo property Ritesh Harjani
2016-11-17 23:03 ` Stephen Boyd
[not found] ` <20161117230352.GO25626-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-21 6:31 ` Ritesh Harjani
[not found] ` <1479343623-31163-1-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-18 14:17 ` Rob Herring
2016-11-16 16:00 ` [PATCH v8 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 11/16] mmc: sdhci-msm: Add clock changes for DDR mode Ritesh Harjani
[not found] ` <1479312052-22396-1-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-16 16:00 ` [PATCH v8 02/16] clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 06/16] mmc: sdhci-msm: Update DLL reset sequence Ritesh Harjani
[not found] ` <1479312052-22396-7-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-17 0:50 ` Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 08/16] mmc: sdhci-msm: Enable few quirks Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 09/16] mmc: sdhci: Factor out sdhci_enable_clock Ritesh Harjani
2016-11-18 13:56 ` Adrian Hunter
2016-11-21 6:31 ` Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 10/16] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm Ritesh Harjani
2016-11-18 14:14 ` Adrian Hunter
2016-11-16 16:00 ` [PATCH v8 12/16] arm64: dts: qcom: msm8916: Add ddr support to sdhc1 Ritesh Harjani
2016-11-17 0:52 ` Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 13/16] mmc: sdhci-msm: Add HS400 platform support Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 16/16] sdhci: sdhci-msm: update dll configuration Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 14/16] mmc: sdhci-msm: Save the calculated tuning phase Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 15/16] mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit Ritesh Harjani
2016-11-17 0:08 ` [PATCH v8 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support Jeremy McNicoll
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