Re: [PATCH v5] drm/mediatek: fixed the calc method of data rate per lane

From: CK Hu <ck.hu@mediatek.com>
To: Daniel Kurtz <djkurtz@chromium.org>
Cc: "Mark Rutland" <mark.rutland@arm.com>,
	stonea168@163.com, dri-devel <dri-devel@lists.freedesktop.org>,
	"Yingjoe Chen (陳英洲)" <yingjoe.chen@mediatek.com>,
	"Ajay Kumar" <ajaykumar.rs@samsung.com>,
	"Vincent Palatin" <vpalatin@chromium.org>,
	"cawa cheng" <cawa.cheng@mediatek.com>,
	"Russell King" <rmk+kernel@arm.linux.org.uk>,
	"open list:OPEN FIRMWARE AND..." <devicetree@vger.kernel.org>,
	"Jitao Shi" <jitao.shi@mediatek.com>,
	"Pawel Moll" <pawel.moll@arm.com>,
	"Ian Campbell" <ijc+devicetree@hellion.org.uk>,
	"Rob Herring" <robh+dt@kernel.org>,
	"moderated list:ARM/Mediatek SoC support"
	<linux-mediatek@lists.infradead.org>,
	"Andy Yan" <andy.yan@rock-chips.com>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	"Eddie Huang (黃智傑)" <eddie.huang@mediatek.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.o>
Subject: Re: [PATCH v5] drm/mediatek: fixed the calc method of data rate per lane
Date: Fri, 18 Nov 2016 13:17:35 +0800	[thread overview]
Message-ID: <1479446255.24375.3.camel@mtksdaap41> (raw)
In-Reply-To: <CAGS+omBpdRH5ZnvcApX_pevwSBHwUon77DhhjX0p9aQXuOy4DA@mail.gmail.com>

Hi, Daniel:

On Fri, 2016-11-18 at 11:22 +0800, Daniel Kurtz wrote:
> Hi CK,
> 
> On Thu, Nov 17, 2016 at 1:36 PM, CK Hu <ck.hu@mediatek.com> wrote:
> > Hi, Jitao:
> >
> >
> > On Wed, 2016-11-16 at 11:20 +0800, Jitao Shi wrote:
> >> Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e.
> >> Tlpx, Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP
> >> mode, those signals will cause h-time larger than normal and reduce FPS.
> >> So need to multiply a coefficient to offset the extra signal's effect.
> >>   coefficient = ((htotal*bpp/lane_number)+Tlpx+Ths_prep+Ths_zero+
> >>                Ths_trail+Ths_exit)/(htotal*bpp/lane_number)
> >>
> >> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> >
> > It looks good to me.
> > But this patch conflict with [1] which is one patch of MT2701 series. I
> > want to apply MT2701 patches first, so please help to refine this patch
> > based on MT2701 patches.
> 
> I don't think the MT2701 DSI patches are quite ready yet (I just
> reviewed the one below).
> Can we instead land Jitao's small targeted change first, and then
> rebase the MT2701 series on top.
> 
> Thanks,
> -Dan

MT2701 series looks still have some defect to be fixed.
Therefore, I would apply this patch first.
Thanks for your help.

Regards,
CK

> >
> > [1] https://patchwork.kernel.org/patch/9422821/
> >
> > Regards,
> > CK
> >
> >> ---
> >> Change since v4:
> >>  - tune the calc comment more clear.
> >>  - define the phy timings as constants.
> >>
> >> Chnage since v3:
> >>  - wrapp the commit msg.
> >>  - fix alignment of some lines.
> >>
> >> Change since v2:
> >>  - move phy timing back to dsi_phy_timconfig.
> >>
> >> Change since v1:
> >>  - phy_timing2 and phy_timing3 refer clock cycle time.
> >>  - define values of LPX HS_PRPR HS_ZERO HS_TRAIL TA_GO TA_SURE TA_GET DA_HS_EXIT.
> >> ---
> >>
> >

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